From patchwork Tue Sep 5 12:08:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1829872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=D/Sp/p2Z; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rg47Q3CQZz1yh1 for ; Tue, 5 Sep 2023 22:09:38 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1DAA33857721 for ; Tue, 5 Sep 2023 12:09:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1DAA33857721 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1693915776; bh=9yMnnDL2v/KSPkny75tqWADU7rNErB8OiTqvf/6HQB0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=D/Sp/p2ZjkPhkhPlQDUwUJ620muX4W3d7DrIdNgyFfTOYYoNoLzbNYAdccLWiPh+3 Z5BJPImlToOHX0PtA08TMEQBmQKyNYnVn1rCL+eehR/o5pTnZeDny0/GUXZvwm+VTG i+PHAgosaruadUi4q/cpL7mDjF4GPoBuQoWtbGQ0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id A92BA3858D32 for ; Tue, 5 Sep 2023 12:09:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A92BA3858D32 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 95933300089; Tue, 5 Sep 2023 12:09:11 +0000 (UTC) To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH v2] RISC-V: Fix Zicond ICE on large constants Date: Tue, 5 Sep 2023 12:08:53 +0000 Message-ID: <37a03341f16da30b83bec1f4ef51dce4e6f25264.1693915537.git.research_trasio@irq.a4lg.com> In-Reply-To: <3cc5403de383d7c8cfd1769948c2bcf9d54b97f9.1693786829.git.research_trasio@irq.a4lg.com> References: <3cc5403de383d7c8cfd1769948c2bcf9d54b97f9.1693786829.git.research_trasio@irq.a4lg.com> Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Gcc-patches From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Tsukasa OI Large constant cons and/or alt will trigger ICEs building GCC target libraries (libgomp and libatomic) when the 'Zicond' extension is enabled. For instance, zicond-ice-2.c (new test case in this commit) will cause an ICE when SOME_NUMBER is 0x1000 or larger. While opposite numbers corresponding cons/alt (two temp2 variables) are checked, cons/alt themselves are not checked and causing 2 ICEs building GCC target libraries as of this writing: 1. gcc/libatomic/config/posix/lock.c 2. gcc/libgomp/fortran.c Coercing a large value into a register will fix the issue. It also coerce a large cons into a register on "imm, imm" case (the author could not reproduce but possible to cause an ICE). gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_conditional_move): Force large constant cons/alt into a register. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-ice-2.c: New test. This is based on an ICE at libat_lock_n func on gcc/libatomic/config/posix/lock.c but heavily minimized. --- gcc/config/riscv/riscv.cc | 21 +++++++++++++------ gcc/testsuite/gcc.target/riscv/zicond-ice-2.c | 11 ++++++++++ 2 files changed, 26 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-2.c base-commit: 72b639760a891c406725854bfb08132c83f0761a diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8d8f7b4f16ed..e306d57814be 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3917,6 +3917,11 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) gen_rtx_IF_THEN_ELSE (mode, cond, CONST0_RTX (mode), alt))); + /* CONS might not fit into a signed 12 bit immediate suitable + for an addi instruction. If that's the case, force it + into a register. */ + if (!SMALL_OPERAND (INTVAL (cons))) + cons = force_reg (mode, cons); riscv_emit_binary (PLUS, dest, dest, cons); return true; } @@ -3940,11 +3945,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) rtx temp1 = gen_reg_rtx (mode); rtx temp2 = gen_int_mode (-1 * INTVAL (cons), mode); - /* TEMP2 might not fit into a signed 12 bit immediate suitable - for an addi instruction. If that's the case, force it into - a register. */ + /* TEMP2 and/or CONS might not fit into a signed 12 bit immediate + suitable for an addi instruction. If that's the case, force it + into a register. */ if (!SMALL_OPERAND (INTVAL (temp2))) temp2 = force_reg (mode, temp2); + if (!SMALL_OPERAND (INTVAL (cons))) + cons = force_reg (mode, cons); riscv_emit_binary (PLUS, temp1, alt, temp2); emit_insn (gen_rtx_SET (dest, @@ -3986,11 +3993,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) rtx temp1 = gen_reg_rtx (mode); rtx temp2 = gen_int_mode (-1 * INTVAL (alt), mode); - /* TEMP2 might not fit into a signed 12 bit immediate suitable - for an addi instruction. If that's the case, force it into - a register. */ + /* TEMP2 and/or ALT might not fit into a signed 12 bit immediate + suitable for an addi instruction. If that's the case, force it + into a register. */ if (!SMALL_OPERAND (INTVAL (temp2))) temp2 = force_reg (mode, temp2); + if (!SMALL_OPERAND (INTVAL (alt))) + alt = force_reg (mode, alt); riscv_emit_binary (PLUS, temp1, cons, temp2); emit_insn (gen_rtx_SET (dest, diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c new file mode 100644 index 000000000000..ffd8dcb5814e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d" { target { rv32 } } } */ + +#define SOME_NUMBER 0x1000 + +unsigned long +d (unsigned long n) +{ + return n > SOME_NUMBER ? SOME_NUMBER : n; +}