From patchwork Fri Aug 11 16:18:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 1820343 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=TePZUnaw; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RMprg11Vlz1yYC for ; Sat, 12 Aug 2023 02:18:59 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qUUq7-0001An-GW; Fri, 11 Aug 2023 12:18:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qUUq5-00019u-13 for qemu-devel@nongnu.org; Fri, 11 Aug 2023 12:18:13 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qUUq3-0002uh-Iz for qemu-devel@nongnu.org; Fri, 11 Aug 2023 12:18:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1691770690; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wDyi34CPiY9sRWLlpPZ1XFJfj8vpMoJLeBIuoJ5wE/0=; b=TePZUnawkO2UzKH6CKMZ7d20dbzQgcG/lAea9pzzMbVe2ARSGudWLZaS8Lx4JS9Dl1Ebjs DQW2RgV57E/m5tavq8ivj9daVxTluU/OValz3ByGFqx49hxO/FIlHIY+o1fwmf0fIKpgLI lbOjS67Q5ZgjEqErfBmbN4qHxDjoyoA= Received: from mail-lf1-f70.google.com (mail-lf1-f70.google.com [209.85.167.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-468-RN0NeuuUNd64E5aXkGIzVA-1; Fri, 11 Aug 2023 12:18:09 -0400 X-MC-Unique: RN0NeuuUNd64E5aXkGIzVA-1 Received: by mail-lf1-f70.google.com with SMTP id 2adb3069b0e04-4fe0f24e801so2123357e87.3 for ; Fri, 11 Aug 2023 09:18:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691770687; x=1692375487; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=wDyi34CPiY9sRWLlpPZ1XFJfj8vpMoJLeBIuoJ5wE/0=; b=kM7ZbGMgvX/9sATCsp5In7g5/RgVpg9Pvn5Iu4rp+IzFkG9n9Y4kZwS1biLw6xqB2U oCRDYbpwpFm4Edml0haYK42pNYvpGE6N5hpUmtiqbuVy71oIL3jMZX+x1IhFlNs+nlmR 3b//N+GUYl8+aakP/bM3km90uqmu2f0fJ98Mh9aChQhpp3Gnr1lg9PZ6Au9iwXJ5R4gt BMSdkkQpX8EG5KAuwCPZ+CzXiZzH2RwekYuYOovk2UttahW9qd42ey83IwAMfAPQnN4f ty9xxr9WWN4kS10jrpkhOD3rfbtLbzPjC5USxhjArD2OvP4WC7PrzyaqknprMgPpUI+5 KImg== X-Gm-Message-State: AOJu0YziVYICWnksIQZ8wsMX64gCnEExENMgu9T5//rs1w8b68Y5YU/W ryU4qJxwgWMg7TfpMALfH+6MWcu0yYyXdZA4prXOyy9FazC9kigi0gSXqspXahodm3CYwe0FJrH Al2KDgDisQ9RcF+93iTR/YTuzmyAUFBFMBja6BSXEFeXgSl6tFos61IaYBAUuXsZzAWBG X-Received: by 2002:a05:6512:3695:b0:4fe:2efa:b847 with SMTP id d21-20020a056512369500b004fe2efab847mr1603962lfs.23.1691770687218; Fri, 11 Aug 2023 09:18:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH3+xPnR9NXlkB7C6ERGYlfdHfeBkbhQor7cFGV8T/JBft6j7Y/q4uTDe9fdAFQZniWsDgZhQ== X-Received: by 2002:a05:6512:3695:b0:4fe:2efa:b847 with SMTP id d21-20020a056512369500b004fe2efab847mr1603937lfs.23.1691770686741; Fri, 11 Aug 2023 09:18:06 -0700 (PDT) Received: from redhat.com ([2.55.42.146]) by smtp.gmail.com with ESMTPSA id ce11-20020a170906b24b00b0097073f1ed84sm2419803ejb.4.2023.08.11.09.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Aug 2023 09:18:06 -0700 (PDT) Date: Fri, 11 Aug 2023 12:18:02 -0400 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Jason Chien , Frank Chang , Jason Wang , Chien@redhat.com, <@redhat.com, Andrey Smirnov , qemu-arm@nongnu.org Subject: [PULL 1/2] hw/pci-host: Allow extended config space access for Designware PCIe host Message-ID: <3d449bc6030904ead784a4e4644c9640c2152796.1691770630.git.mst@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Jason Chien In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root bus is realized as a PCIe bus if its parent bus is a PCIe bus. However, the child bus "dw-pcie" is realized before the parent bus "pcie" which is the root PCIe bus. Thus, the extended configuration space is not accessible on "dw-pcie". The issue can be resolved by adding the PCI_BUS_EXTENDED_CONFIG_SPACE flag to "pcie" before "dw-pcie" is realized. Signed-off-by: Jason Chien Message-Id: <20230809102257.25121-1-jason.chien@sifive.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Frank Chang Signed-off-by: Jason Chien <jason.chien@sifive.com>
--- hw/pci-host/designware.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 9e183caa48..388d252ee2 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -694,6 +694,7 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp) &s->pci.io, 0, 4, TYPE_PCIE_BUS); + pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; memory_region_init(&s->pci.address_space_root, OBJECT(s), From patchwork Fri Aug 11 16:18:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Guoyi Tu , yuanminghao , Marcel Apfelbaum Subject: [PULL 2/2] pci: Fix the update of interrupt disable bit in PCI_COMMAND register Message-ID: <0f936247e8ed0ab5fb7e75827dd8c8f73d5ef4b5.1691770630.git.mst@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Guoyi Tu The PCI_COMMAND register is located at offset 4 within the PCI configuration space and occupies 2 bytes. The interrupt disable bit is at the 10th bit, which corresponds to the byte at offset 5 in the PCI configuration space. In our testing environment, the guest driver may directly updates the byte at offset 5 in the PCI configuration space. The backtrace looks like as following: at hw/pci/pci.c:1442 at hw/virtio/virtio-pci.c:605 val=5, len=1) at hw/pci/pci_host.c:81 In this situation, the range_covers_byte function called by the pci_default_write_config function will return false, resulting in the inability to handle the interrupt disable update event. To fix this issue, we can use the ranges_overlap function instead of range_covers_byte to determine whether the interrupt bit has been updated. Signed-off-by: Guoyi Tu Signed-off-by: yuanminghao Message-Id: Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Fixes: b6981cb57be5 ("pci: interrupt disable bit support") --- hw/pci/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index b8d22e2e74..881d774fb6 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -1613,7 +1613,7 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int range_covers_byte(addr, l, PCI_COMMAND)) pci_update_mappings(d); - if (range_covers_byte(addr, l, PCI_COMMAND)) { + if (ranges_overlap(addr, l, PCI_COMMAND, 2)) { pci_update_irq_disabled(d, was_irq_disabled); memory_region_set_enabled(&d->bus_master_enable_region, (pci_get_word(d->config + PCI_COMMAND)