From patchwork Sat Jul 29 09:13:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Zeng X-Patchwork-Id: 1814486 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RCf2J0sdPz20G2 for ; Sat, 29 Jul 2023 19:13:53 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2B7DD385AFBD for ; Sat, 29 Jul 2023 09:13:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [207.46.229.174]) by sourceware.org (Postfix) with ESMTP id 8CD953858C00 for ; Sat, 29 Jul 2023 09:13:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8CD953858C00 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from localhost.localdomain (unknown [10.12.130.38]) by app1 (Coremail) with SMTP id EwgMCgAXtcQw2MRkFzc4AA--.19323S4; Sat, 29 Jul 2023 17:13:20 +0800 (CST) From: Xiao Zeng To: jeffreyalaw@gmail.com Cc: gcc-patches@gcc.gnu.org, research_trasio@irq.a4lg.com, kito.cheng@gmail.com, zhengyu@eswincomputing.com, eri-sw-toolchain@eswincomputing.com, Xiao Zeng Subject: [PATCH V2] [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Date: Sat, 29 Jul 2023 17:13:08 +0800 Message-Id: <20230729091308.29792-1-zengxiao@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: EwgMCgAXtcQw2MRkFzc4AA--.19323S4 X-Coremail-Antispam: 1UD129KBjvAXoW3ur43JF48Ar45AFW5XFyrZwb_yoW8XF1kXo ZY9F4rA3WrJr1a9r17Ww12gr17XFW8urs7Ja98KrWjkFn7JwnY9ws7K3WDA34jvrnxXrWj vrWFgFWIqas7Jrn8n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYb7AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2 x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8 JVWxJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42xK 82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGw C20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48J MIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMI IF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E 87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JUdHUDUUUUU= X-CM-SenderInfo: p2hqw5xldrqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch recognizes Zicond patterns when the select pattern with condition eq or neq to 0 (using eq as an example), namely: 1 rd = (rs2 == 0) ? non-imm : 0 2 rd = (rs2 == 0) ? non-imm : non-imm 3 rd = (rs2 == 0) ? reg : non-imm 4 rd = (rs2 == 0) ? reg : reg gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize Zicond patterns * config/riscv/riscv.md: Recognize Zicond patterns through movcc gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c: New test. * gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c: New test. * gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c: New test. * gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c: New test. --- gcc/config/riscv/riscv.cc | 144 ++++++++++++++++++ gcc/config/riscv/riscv.md | 4 +- .../zicond-primitiveSemantics_return_0_imm.c | 65 ++++++++ ...zicond-primitiveSemantics_return_imm_imm.c | 73 +++++++++ ...zicond-primitiveSemantics_return_imm_reg.c | 65 ++++++++ ...zicond-primitiveSemantics_return_reg_reg.c | 65 ++++++++ 6 files changed, 414 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 941ea25e1f2..6ac39f63dd7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3516,6 +3516,150 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) cond, cons, alt))); return true; } + else if (TARGET_ZICOND + && (code == EQ || code == NE) + && GET_MODE_CLASS (mode) == MODE_INT) + { + need_eq_ne_p = true; + /* 0 + imm */ + if (GET_CODE (cons) == CONST_INT && cons == const0_rtx + && GET_CODE (alt) == CONST_INT && alt != const0_rtx) + { + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p); + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + alt = force_reg (mode, alt); + emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond, + cons, alt))); + return true; + } + /* imm + imm */ + else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx + && GET_CODE (alt) == CONST_INT && alt != const0_rtx) + { + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p); + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + rtx reg = gen_reg_rtx (mode); + rtx temp = GEN_INT (INTVAL (alt) - INTVAL (cons)); + emit_insn (gen_rtx_SET (reg, temp)); + emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond, + CONST0_RTX (mode), + reg))); + riscv_emit_binary (PLUS, dest, dest, cons); + return true; + } + /* imm + reg */ + else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx + && GET_CODE (alt) == REG) + { + /* Optimize for register value of 0. */ + if (op0 == alt && op1 == const0_rtx) + { + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + cons = force_reg (mode, cons); + emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond, + cons, alt))); + return true; + } + /* Handle the special situation of: -2048 == INTVAL (alt) + to avoid failure due to an unrecognized insn. Let the costing + model determine if the conditional move sequence is better + than the branching sequence. */ + if (-2048 == INTVAL (cons)) + { + rtx reg = gen_reg_rtx (mode); + emit_insn (gen_rtx_SET (reg, cons)); + return riscv_expand_conditional_move (dest, op, reg, alt); + } + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p); + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + rtx temp = GEN_INT (-1 * INTVAL (cons)); + riscv_emit_binary (PLUS, alt, alt, temp); + emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond, + CONST0_RTX (mode), + alt))); + riscv_emit_binary (PLUS, dest, dest, cons); + return true; + } + /* imm + 0 */ + else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx + && GET_CODE (alt) == CONST_INT && alt == const0_rtx) + { + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p); + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + cons = force_reg (mode, cons); + emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond, + cons, alt))); + return true; + } + /* reg + imm */ + else if (GET_CODE (cons) == REG + && GET_CODE (alt) == CONST_INT && alt != const0_rtx) + { + /* Optimize for register value of 0. */ + if (op0 == cons && op1 == const0_rtx) + { + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + alt = force_reg (mode, alt); + emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond, + cons, alt))); + return true; + } + if (-2048 == INTVAL (alt)) + { + rtx reg = gen_reg_rtx (mode); + emit_insn (gen_rtx_SET (reg, alt)); + return riscv_expand_conditional_move (dest, op, cons, reg); + } + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p); + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + rtx temp = GEN_INT (-1 * INTVAL (alt)); + riscv_emit_binary (PLUS, cons, cons, temp); + emit_insn (gen_rtx_SET (dest, + gen_rtx_IF_THEN_ELSE (mode, cond, cons, + CONST0_RTX (mode)))); + riscv_emit_binary (PLUS, dest, dest, alt); + return true; + } + /* reg + reg */ + else if (GET_CODE (cons) == REG && GET_CODE (alt) == REG) + { + /* Optimize for op0 == cons && op1 == const0_rtx. */ + if (op0 == cons && op1 == const0_rtx) + { + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + emit_insn (gen_rtx_SET (dest, + gen_rtx_IF_THEN_ELSE (mode, cond, + CONST0_RTX (mode), + alt))); + return true; + } + /* Optimize for op0 == alt && op1 == const0_rtx. */ + if (op0 == alt && op1 == const0_rtx) + { + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + emit_insn (gen_rtx_SET (dest, + gen_rtx_IF_THEN_ELSE (mode, cond, cons, + CONST0_RTX (mode)))); + return true; + } + rtx reg1 = gen_reg_rtx (mode); + rtx reg2 = gen_reg_rtx (mode); + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p); + rtx cond1 = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + rtx cond2 = gen_rtx_fmt_ee (code == NE ? EQ : NE, + GET_MODE (op0), op0, op1); + emit_insn (gen_rtx_SET (reg2, + gen_rtx_IF_THEN_ELSE (mode, cond2, + CONST0_RTX (mode), + cons))); + emit_insn (gen_rtx_SET (reg1, + gen_rtx_IF_THEN_ELSE (mode, cond1, + CONST0_RTX (mode), + alt))); + riscv_emit_binary (IOR, dest, reg1, reg2); + return true; + } + } return false; } diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 8d8fc93bb14..4b6875aa340 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2484,9 +2484,9 @@ (define_expand "movcc" [(set (match_operand:GPR 0 "register_operand") (if_then_else:GPR (match_operand 1 "comparison_operator") - (match_operand:GPR 2 "reg_or_0_operand") + (match_operand:GPR 2 "sfb_alu_operand") (match_operand:GPR 3 "sfb_alu_operand")))] - "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV" + "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND" { if (riscv_expand_conditional_move (operands[0], operands[1], operands[2], operands[3])) diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c new file mode 100644 index 00000000000..6e45b3f8ae5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os"} } */ + +long primitiveSemantics_return_0_imm_00(long a, long b) { + return a == 0 ? 0 : 3; +} + +long primitiveSemantics_return_0_imm_01(long a, long b) { + return a != 0 ? 0 : 3; +} + +long primitiveSemantics_return_0_imm_02(long a, long b) { + return a == 0 ? 3 : 0; +} + +long primitiveSemantics_return_0_imm_03(long a, long b) { + return a != 0 ? 3 : 0; +} + +long primitiveSemantics_return_0_imm_04(long a, long b) { + if (a) + b = 0; + else + b = 3; + return b; +} + +long primitiveSemantics_return_0_imm_05(long a, long b) { + if (!a) + b = 0; + else + b = 3; + return b; +} + +int primitiveSemantics_return_0_imm_06(int a, int b) { return a == 0 ? 0 : 3; } + +int primitiveSemantics_return_0_imm_07(int a, int b) { return a != 0 ? 0 : 3; } + +int primitiveSemantics_return_0_imm_08(int a, int b) { return a == 0 ? 3 : 0; } + +int primitiveSemantics_return_0_imm_09(int a, int b) { return a != 0 ? 3 : 0; } + +int primitiveSemantics_return_0_imm_10(int a, int b) { + if (a) + b = 0; + else + b = 3; + return b; +} + +int primitiveSemantics_return_0_imm_11(int a, int b) { + if (!a) + b = 0; + else + b = 3; + return b; +} + +/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */ +/* { dg-final { scan-assembler-times "czero.nez" 6 } } */ +/* { dg-final { scan-assembler-not "beq" } } */ +/* { dg-final { scan-assembler-not "bne" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c new file mode 100644 index 00000000000..ebdca521373 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os"} } */ + +long primitiveSemantics_return_imm_imm_00(long a, long b) { + return a == 0 ? 4 : 6; +} + +long primitiveSemantics_return_imm_imm_01(long a, long b) { + return a != 0 ? 4 : 6; +} + +long primitiveSemantics_return_imm_imm_02(long a, long b) { + return a == 0 ? 6 : 4; +} + +long primitiveSemantics_return_imm_imm_03(long a, long b) { + return a != 0 ? 6 : 4; +} + +long primitiveSemantics_return_imm_imm_04(long a, long b) { + if (a) + b = 4; + else + b = 6; + return b; +} + +long primitiveSemantics_return_imm_imm_05(long a, long b) { + if (!a) + b = 4; + else + b = 6; + return b; +} + +int primitiveSemantics_return_imm_imm_06(int a, int b) { + return a == 0 ? 4 : 6; +} + +int primitiveSemantics_return_imm_imm_07(int a, int b) { + return a != 0 ? 4 : 6; +} + +int primitiveSemantics_return_imm_imm_08(int a, int b) { + return a == 0 ? 6 : 4; +} + +int primitiveSemantics_return_imm_imm_09(int a, int b) { + return a != 0 ? 6 : 4; +} + +int primitiveSemantics_return_imm_imm_10(int a, int b) { + if (a) + b = 4; + else + b = 6; + return b; +} + +int primitiveSemantics_return_imm_imm_11(int a, int b) { + if (!a) + b = 4; + else + b = 6; + return b; +} + +/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */ +/* { dg-final { scan-assembler-times "czero.nez" 6 } } */ +/* { dg-final { scan-assembler-not "beq" } } */ +/* { dg-final { scan-assembler-not "bne" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c new file mode 100644 index 00000000000..12c351dbc16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os"} } */ + +long primitiveSemantics_return_imm_reg_00(long a, long b) { + return a == 0 ? 1 : b; +} + +long primitiveSemantics_return_imm_reg_01(long a, long b) { + return a != 0 ? 1 : b; +} + +long primitiveSemantics_return_imm_reg_02(long a, long b) { + return a == 0 ? b : 1; +} + +long primitiveSemantics_return_imm_reg_03(long a, long b) { + return a != 0 ? b : 1; +} + +long primitiveSemantics_return_imm_reg_04(long a, long b) { + if (a) + b = 1; + return b; +} + +long primitiveSemantics_return_imm_reg_05(long a, long b) { + if (!a) + b = 1; + return b; +} + +int primitiveSemantics_return_imm_reg_06(int a, int b) { + return a == 0 ? 1 : b; +} + +int primitiveSemantics_return_imm_reg_07(int a, int b) { + return a != 0 ? 1 : b; +} + +int primitiveSemantics_return_imm_reg_08(int a, int b) { + return a == 0 ? b : 1; +} + +int primitiveSemantics_return_imm_reg_09(int a, int b) { + return a != 0 ? b : 1; +} + +int primitiveSemantics_return_imm_reg_10(int a, int b) { + if (a) + b = 1; + return b; +} + +int primitiveSemantics_return_imm_reg_11(int a, int b) { + if (!a) + b = 1; + return b; +} + +/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */ +/* { dg-final { scan-assembler-times "czero.nez" 6 } } */ +/* { dg-final { scan-assembler-not "beq" } } */ +/* { dg-final { scan-assembler-not "bne" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c new file mode 100644 index 00000000000..4708afa645b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os"} } */ + +long primitiveSemantics_return_reg_reg_00(long a, long b, long c) { + return a == 0 ? c : b; +} + +long primitiveSemantics_return_reg_reg_01(long a, long b, long c) { + return a != 0 ? c : b; +} + +long primitiveSemantics_return_reg_reg_02(long a, long b, long c) { + return a == 0 ? b : c; +} + +long primitiveSemantics_return_reg_reg_03(long a, long b, long c) { + return a != 0 ? b : c; +} + +long primitiveSemantics_return_reg_reg_04(long a, long b, long c) { + if (a) + b = c; + return b; +} + +long primitiveSemantics_return_reg_reg_05(long a, long b, long c) { + if (!a) + b = c; + return b; +} + +int primitiveSemantics_return_reg_reg_06(int a, int b, int c) { + return a == 0 ? c : b; +} + +int primitiveSemantics_return_reg_reg_07(int a, int b, int c) { + return a != 0 ? c : b; +} + +int primitiveSemantics_return_reg_reg_08(int a, int b, int c) { + return a == 0 ? b : c; +} + +int primitiveSemantics_return_reg_reg_09(int a, int b, int c) { + return a != 0 ? b : c; +} + +int primitiveSemantics_return_reg_reg_10(int a, int b, int c) { + if (a) + b = c; + return b; +} + +int primitiveSemantics_return_reg_reg_11(int a, int b, int c) { + if (!a) + b = c; + return b; +} + +/* { dg-final { scan-assembler-times "czero.eqz" 12 } } */ +/* { dg-final { scan-assembler-times "czero.nez" 12 } } */ +/* { dg-final { scan-assembler-not "beq" } } */ +/* { dg-final { scan-assembler-not "bne" } } */