From patchwork Wed Jul 26 16:27:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1813306 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=hOpLhlM0; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R9zpW63tjz1ydm for ; Thu, 27 Jul 2023 02:28:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231172AbjGZQ2B (ORCPT ); Wed, 26 Jul 2023 12:28:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230312AbjGZQ1x (ORCPT ); Wed, 26 Jul 2023 12:27:53 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A0B8269E; Wed, 26 Jul 2023 09:27:51 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4fbf09a9139so11015257e87.2; Wed, 26 Jul 2023 09:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690388869; x=1690993669; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=QoSMNchEXwuX3x9QSSuoNR4qaNrXEAa88B7oBatCh9k=; b=hOpLhlM0bSjFk24PeXZyHUzLwARE7wrYPSZwiP6pVi+jeEE43Zya2TlPdEReScX18r 4y6AvmBcloKqqwgu+9oYQhz7ZmV0htmo4yVxU3JYmiGkfrWJTeQc4y9al7PuBv5e2sQA ljOlOTrvml8f6H6WiGE7wPFtWDm39eE42bynZm6Glj4CXOYqE28qzBHHU5UUh9i4IyzP +jXoxOB/2TAeXuzze5hx52zTYryHTdNgzofFb9dEfwCfYidcXB+FosYK4+o00UfyABRo dICONGcvQc0jCgTU29Tn6F1Gy+s5AUgZjtiFa3kBg/wkNHcb+iSrJ565nm3ZVJxDj/gq zZ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690388869; x=1690993669; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=QoSMNchEXwuX3x9QSSuoNR4qaNrXEAa88B7oBatCh9k=; b=CB1OC+CR5iFadcc2liovoYZ87ZhVo6LhL0PamYqqVS8vpzQEnZd/I6SBBFpzVyo54J E3csC82NbtUo2R8/zs9FSlfafXIhkC1JWGPvuFCvxNLYtpbskstYh6fA9DPC9pXmQJh0 RkzpbpjEefJcqAwqb7QqrgOK5D5Tzx5tFYegaEbYZBQbp6Dv+AECSaJoRSc13DyxZX3h mgsDfPfniU1QfI4lwtLvZAfU1MiCYAH7Vlf+wOVYYHRqNPn6lFdV4SdUojVBBH3fTLI4 Ec7etkGrDDBTYOb9Sa06WO4HDvAKkDLM/8kYc55LlemRJyqxXMBh23J4xNLxnKxgS8SV ouww== X-Gm-Message-State: ABy/qLagcUEZRtQleOZkJEYVjnuoK5I42HAwUimCxVzPhD83dVhh5ock pVEnAArIAWl4vyKlbqBpqsFgVBrPHHY= X-Google-Smtp-Source: APBJJlGD4YeYrOnM8r6fZw0mZaQqcVDl6v+A1YAKQnPKQCXWofJcZg46zV+nF5UAQXVfg7JCWHq1kQ== X-Received: by 2002:a2e:9d0f:0:b0:2b6:df8a:d44b with SMTP id t15-20020a2e9d0f000000b002b6df8ad44bmr1808581lji.36.1690388869011; Wed, 26 Jul 2023 09:27:49 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id q11-20020a170906388b00b00988dbbd1f7esm9655986ejd.213.2023.07.26.09.27.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 09:27:48 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v3 1/7] dt-bindings: arm: tegra: pmc: Improve property descriptions Date: Wed, 26 Jul 2023 18:27:38 +0200 Message-ID: <20230726162744.2113008-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Reformat the description of various properties to make them more consistent with existing ones. Make use of json-schema's ability to provide a description for individual list items to make improve the documentation further. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - instead of rewriting it, drop the reg property description in patch 2 - add Reviewed-by: from Rob .../arm/tegra/nvidia,tegra20-pmc.yaml | 212 +++++++++--------- 1 file changed, 103 insertions(+), 109 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 89191cfdf619..38fe66142547 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -26,12 +26,10 @@ properties: clock-names: items: + # Tegra clock of the same name - const: pclk + # 32 KHz clock input - const: clk32k_in - description: - Must includes entries pclk and clk32k_in. - pclk is the Tegra clock of that name and clk32k_in is 32KHz clock - input to Tegra. clocks: maxItems: 2 @@ -41,105 +39,103 @@ properties: '#clock-cells': const: 1 - description: - Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. - PMC also has blink control which allows 32Khz clock output to - Tegra blink pad. - Consumer of PMC clock should specify the desired clock by having - the clock ID in its "clocks" phandle cell with pmc clock provider. - See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC - clock IDs. + description: | + Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink + control which allows 32Khz clock output to Tegra blink pad. + + Consumer of PMC clock should specify the desired clock by having the + clock ID in its "clocks" phandle cell with PMC clock provider. See + include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs. '#interrupt-cells': const: 2 - description: - Specifies number of cells needed to encode an interrupt source. - The value must be 2. + description: Specifies number of cells needed to encode an interrupt + source. interrupt-controller: true nvidia,invert-interrupt: $ref: /schemas/types.yaml#/definitions/flag - description: Inverts the PMU interrupt signal. - The PMU is an external Power Management Unit, whose interrupt output - signal is fed into the PMC. This signal is optionally inverted, and - then fed into the ARM GIC. The PMC is not involved in the detection - or handling of this interrupt signal, merely its inversion. + description: Inverts the PMU interrupt signal. The PMU is an external Power + Management Unit, whose interrupt output signal is fed into the PMC. This + signal is optionally inverted, and then fed into the ARM GIC. The PMC is + not involved in the detection or handling of this interrupt signal, + merely its inversion. nvidia,core-power-req-active-high: $ref: /schemas/types.yaml#/definitions/flag - description: Core power request active-high. + description: core power request active-high nvidia,sys-clock-req-active-high: $ref: /schemas/types.yaml#/definitions/flag - description: System clock request active-high. + description: system clock request active-high nvidia,combined-power-req: $ref: /schemas/types.yaml#/definitions/flag - description: combined power request for CPU and Core. + description: combined power request for CPU and core nvidia,cpu-pwr-good-en: $ref: /schemas/types.yaml#/definitions/flag - description: - CPU power good signal from external PMIC to PMC is enabled. + description: CPU power good signal from external PMIC to PMC is enabled nvidia,suspend-mode: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2] - description: - The suspend mode that the platform should use. - Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh - Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh - Mode 2 is for LP2, CPU voltage off + description: the suspend mode that the platform should use + oneOf: + - description: LP0, CPU + Core voltage off and DRAM in self-refresh + const: 0 + - description: LP1, CPU voltage off and DRAM in self-refresh + const: 1 + - description: LP2, CPU voltage off + const: 2 nvidia,cpu-pwr-good-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: CPU power good time in uSec. + description: CPU power good time in microseconds nvidia,cpu-pwr-off-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: CPU power off time in uSec. + description: CPU power off time in microseconds nvidia,core-pwr-good-time: $ref: /schemas/types.yaml#/definitions/uint32-array - description: - - Core power good time in uSec. + description: core power good time in microseconds + items: + - description: oscillator stable time + - description: power stable time nvidia,core-pwr-off-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: Core power off time in uSec. + description: core power off time in microseconds nvidia,lp0-vec: $ref: /schemas/types.yaml#/definitions/uint32-array - description: - Starting address and length of LP0 vector. - The LP0 vector contains the warm boot code that is executed - by AVP when resuming from the LP0 state. - The AVP (Audio-Video Processor) is an ARM7 processor and - always being the first boot processor when chip is power on - or resume from deep sleep mode. When the system is resumed - from the deep sleep mode, the warm boot code will restore - some PLLs, clocks and then brings up CPU0 for resuming the - system. + description: | + Starting address and length of LP0 vector. The LP0 vector contains the + warm boot code that is executed by AVP when resuming from the LP0 state. + The AVP (Audio-Video Processor) is an ARM7 processor and always being + the first boot processor when chip is power on or resume from deep sleep + mode. When the system is resumed from the deep sleep mode, the warm boot + code will restore some PLLs, clocks and then brings up CPU0 for resuming + the system. + items: + - description: starting address of LP0 vector + - description: length of LP0 vector core-supply: - description: - Phandle to voltage regulator connected to the SoC Core power rail. + description: phandle to voltage regulator connected to the SoC core power + rail core-domain: type: object - description: | - The vast majority of hardware blocks of Tegra SoC belong to a - Core power domain, which has a dedicated voltage rail that powers - the blocks. - + description: The vast majority of hardware blocks of Tegra SoC belong to a + core power domain, which has a dedicated voltage rail that powers the + blocks. properties: operating-points-v2: - description: - Should contain level, voltages and opp-supported-hw property. - The supported-hw is a bitfield indicating SoC speedo or process - ID mask. + description: Should contain level, voltages and opp-supported-hw + property. The supported-hw is a bitfield indicating SoC speedo or + process ID mask. "#power-domain-cells": const: 0 @@ -152,37 +148,32 @@ properties: i2c-thermtrip: type: object - description: - On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, - hardware-triggered thermal reset will be enabled. - + description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode + exists, hardware-triggered thermal reset will be enabled. properties: nvidia,i2c-controller-id: $ref: /schemas/types.yaml#/definitions/uint32 - description: - ID of I2C controller to send poweroff command to PMU. - Valid values are described in section 9.2.148 - "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference - Manual. + description: ID of I2C controller to send poweroff command to PMU. + Valid values are described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" + of the Tegra K1 Technical Reference Manual. nvidia,bus-addr: $ref: /schemas/types.yaml#/definitions/uint32 - description: Bus address of the PMU on the I2C bus. + description: bus address of the PMU on the I2C bus nvidia,reg-addr: $ref: /schemas/types.yaml#/definitions/uint32 - description: PMU I2C register address to issue poweroff command. + description: PMU I2C register address to issue poweroff command nvidia,reg-data: $ref: /schemas/types.yaml#/definitions/uint32 - description: Poweroff command to write to PMU. + description: power-off command to write to PMU nvidia,pinmux-id: $ref: /schemas/types.yaml#/definitions/uint32 - description: - Pinmux used by the hardware when issuing Poweroff command. - Defaults to 0. Valid values are described in section 12.5.2 - "Pinmux Support" of the Tegra4 Technical Reference Manual. + description: Pinmux used by the hardware when issuing power-off command. + Defaults to 0. Valid values are described in section 12.5.2 "Pinmux + Support" of the Tegra4 Technical Reference Manual. required: - nvidia,i2c-controller-id @@ -195,41 +186,44 @@ properties: powergates: type: object description: | - This node contains a hierarchy of power domain nodes, which should - match the powergates on the Tegra SoC. Each powergate node - represents a power-domain on the Tegra SoC that can be power-gated - by the Tegra PMC. - Hardware blocks belonging to a power domain should contain - "power-domains" property that is a phandle pointing to corresponding - powergate node. - The name of the powergate node should be one of the below. Note that - not every powergate is applicable to all Tegra devices and the following - list shows which powergates are applicable to which devices. - Please refer to Tegra TRM for mode details on the powergate nodes to - use for each power-gate block inside Tegra. - Name Description Devices Applicable - 3d 3D Graphics Tegra20/114/124/210 - 3d0 3D Graphics 0 Tegra30 - 3d1 3D Graphics 1 Tegra30 - aud Audio Tegra210 - dfd Debug Tegra210 - dis Display A Tegra114/124/210 - disb Display B Tegra114/124/210 - heg 2D Graphics Tegra30/114/124/210 - iram Internal RAM Tegra124/210 - mpe MPEG Encode All - nvdec NVIDIA Video Decode Engine Tegra210 - nvjpg NVIDIA JPEG Engine Tegra210 - pcie PCIE Tegra20/30/124/210 - sata SATA Tegra30/124/210 - sor Display interfaces Tegra124/210 - ve2 Video Encode Engine 2 Tegra210 - venc Video Encode Engine All - vdec Video Decode Engine Tegra20/30/114/124 - vic Video Imaging Compositor Tegra124/210 - xusba USB Partition A Tegra114/124/210 - xusbb USB Partition B Tegra114/124/210 - xusbc USB Partition C Tegra114/124/210 + This node contains a hierarchy of power domain nodes, which should match + the powergates on the Tegra SoC. Each powergate node represents a power- + domain on the Tegra SoC that can be power-gated by the Tegra PMC. + + Hardware blocks belonging to a power domain should contain "power-domains" + property that is a phandle pointing to corresponding powergate node. + + The name of the powergate node should be one of the below. Note that not + every powergate is applicable to all Tegra devices and the following list + shows which powergates are applicable to which devices. + + Please refer to Tegra TRM for mode details on the powergate nodes to use + for each power-gate block inside Tegra. + + Name Description Devices Applicable + -------------------------------------------------------------- + 3d 3D Graphics Tegra20/114/124/210 + 3d0 3D Graphics 0 Tegra30 + 3d1 3D Graphics 1 Tegra30 + aud Audio Tegra210 + dfd Debug Tegra210 + dis Display A Tegra114/124/210 + disb Display B Tegra114/124/210 + heg 2D Graphics Tegra30/114/124/210 + iram Internal RAM Tegra124/210 + mpe MPEG Encode All + nvdec NVIDIA Video Decode Engine Tegra210 + nvjpg NVIDIA JPEG Engine Tegra210 + pcie PCIE Tegra20/30/124/210 + sata SATA Tegra30/124/210 + sor Display interfaces Tegra124/210 + ve2 Video Encode Engine 2 Tegra210 + venc Video Encode Engine All + vdec Video Decode Engine Tegra20/30/114/124 + vic Video Imaging Compositor Tegra124/210 + xusba USB Partition A Tegra114/124/210 + xusbb USB Partition B Tegra114/124/210 + xusbc USB Partition C Tegra114/124/210 patternProperties: "^[a-z0-9]+$": From patchwork Wed Jul 26 16:27:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1813308 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=Up+R6SbC; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R9zpX5S2Lz1yYc for ; Thu, 27 Jul 2023 02:28:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230459AbjGZQ2C (ORCPT ); Wed, 26 Jul 2023 12:28:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231320AbjGZQ1x (ORCPT ); Wed, 26 Jul 2023 12:27:53 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4EEB26A8; Wed, 26 Jul 2023 09:27:51 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-51ff0e3d8c1so9908883a12.0; Wed, 26 Jul 2023 09:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690388870; x=1690993670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sYtxsERINvfOgj4TjnONVaidkuvzw8sv8zecGnhSGTU=; b=Up+R6SbCK4R25JybpPE1RDnPYTMXiFQMheC5lvIt5b+v2SbL6y29GQSiGUKpMtmlqN wq2qRmpr+NjwlmVKF4tCjXDIdQ+1RyACFKwD5xmFufYYIEBeiKTqZAt7ESOnOWYe7ncC VhHyuAjSgcDH0Np83ubYHxS9x7pDHt0Wg8menD2d2KD7aIo0b51rDrgxHEocfcdR4Cw+ YWw8wmKm4RRLWhh5p6PQLW6hPkpO0dGylOFX/Phfp6BWU+oYihlKEjBv/5ljHaEvrGEW NSRTRgkncMZVn2gIDb4dlW7oQRLfHAiMLGm/QT+JA8xmD3kPjm9UKqbgHAU5bkXumgsS +gCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690388870; x=1690993670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sYtxsERINvfOgj4TjnONVaidkuvzw8sv8zecGnhSGTU=; b=NjEyuNAWQ91XBFmPZcwplH4UBGHKCLZ57DuuP+UEUWUMWGLWYk711vPigAscLVpkUT vCISl+2vxB0rTR59qbtx+XNMlmc++6ZjVPsJbWOVNjczgOMgDgJlfFep2f+tlRes1n5W 5/1uXMryhWp7RddJLztDWY3Nwr10QIDfhf3JmC0D0jDTpPYMLlqsGHwHmATRcSPEs45i WagnAQmYfKxGnlw9nfQwmePHVCSRdMUe6hMyVSL+cSvqoE0oiDY3MOvUsg/G5GF0usJy KG6weGhspB0lfvvk1lRqaP8JHr8CLryGjSvZ6QZoW1fj1FkMfaGvdeEQtHE5MG1Pq506 fr2w== X-Gm-Message-State: ABy/qLbT/SA4hDlnoX95FqdGi7Cq8cJiH5dEr9z4siA7m8BkQxzCPbJa c5tWhdeXRXBJ1ToVexLt1bc= X-Google-Smtp-Source: APBJJlERoF8DBHU9+zebZYkFfAIEOeM8AYTpjEMG1v4zWHGfF23Sc2xHVI4t/edgPGQm7bIMgtjgwg== X-Received: by 2002:aa7:ca59:0:b0:522:2711:871 with SMTP id j25-20020aa7ca59000000b0052227110871mr1898683edt.1.1690388870053; Wed, 26 Jul 2023 09:27:50 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id w22-20020a056402071600b005221b918e33sm6146730edx.22.2023.07.26.09.27.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 09:27:49 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v3 2/7] dt-bindings: arm: tegra: pmc: Remove useless boilerplate descriptions Date: Wed, 26 Jul 2023 18:27:39 +0200 Message-ID: <20230726162744.2113008-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230726162744.2113008-1-thierry.reding@gmail.com> References: <20230726162744.2113008-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding The descriptions for the clocks and resets properties are no longer useful in the context of json-schema, so drop them. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - drop description of "reg" property - add Reviewed-by: from Rob .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 38fe66142547..0ac258bc7be0 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -21,8 +21,6 @@ properties: reg: maxItems: 1 - description: - Offset and length of the register set for the device. clock-names: items: @@ -33,9 +31,6 @@ properties: clocks: maxItems: 2 - description: - Must contain an entry for each entry in clock-names. - See ../clocks/clocks-bindings.txt for details. '#clock-cells': const: 1 @@ -234,18 +229,10 @@ properties: clocks: minItems: 1 maxItems: 8 - description: - Must contain an entry for each clock required by the PMC - for controlling a power-gate. - See ../clocks/clock-bindings.txt document for more details. resets: minItems: 1 maxItems: 8 - description: - Must contain an entry for each reset required by the PMC - for controlling a power-gate. - See ../reset/reset.txt for more details. power-domains: maxItems: 1 From patchwork Wed Jul 26 16:27:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1813312 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=FLj4+F81; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R9zpZ3r5Fz1yYc for ; Thu, 27 Jul 2023 02:28:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231789AbjGZQ2E (ORCPT ); Wed, 26 Jul 2023 12:28:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231685AbjGZQ1y (ORCPT ); Wed, 26 Jul 2023 12:27:54 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCE8E26AE; Wed, 26 Jul 2023 09:27:52 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-99b9421aaebso525244566b.2; Wed, 26 Jul 2023 09:27:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690388871; x=1690993671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FRDa+hXtdMdC6ZYOUEjHUlfDPteWrj1xebQwjE7g54o=; b=FLj4+F81aNZHX0YoxEp2mF+uBHA5gMb9p5MqM6f12i14QAuHOcN2R8pTw/eSuB71u3 LpHCHBxiUmT4mYOMnWZT4wTQohf7bMPFrBV5CnElUsspZ1y1qdPw+fcMd1902nJThenD L7rX6htJFZ6XS61YqjIR7bs+sF0n1FrjKmrBOi9HMxKHEfJ7M1tACJW091WedrMriQlE vZDJODOG8yutkFXQUJvYeQ0ZC7+uK+Ku/Q54lK0jIDkp9RtkulRTKWbbtAQdPrInNkHf qyjYsE/3wNZ0IHpTrtljRKMQ0JpweCz81fbPTDmoukO174bu7JvsjFTMnm7SY+tYo+Fb cMhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690388871; x=1690993671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FRDa+hXtdMdC6ZYOUEjHUlfDPteWrj1xebQwjE7g54o=; b=Z2rTMl+ob7YFuN+YZvJSlqEgm/zz29EzhkEUGjrAxrYRXbwnVUMJwKGVTg2Nq9gaeW ipWg8Oe2LFZju6PyhPRNWmotpJ6/AMBaqytsK4lRhsLMTl7x0B0U2QzY/CjSd1R1dEaH 2Ki3sEVBcPwWUav/glpx8iiwrDJXZ4YAdbUU00f5NgRB332mf49NpybmE9H4m7Ifv45c Kwz1VR/zI+AfVaOrcUe27Ask2f6D43XBJfD6nFLi4dN7jG+oIMw6HQ9dR6It6cxdGCh1 hxtRL0+2Uba9kDIiuxlJfbIHx79fs8nKHtYbduMuNqYSzfM34k3O/ScDtZLgTEyO/mGZ 9urQ== X-Gm-Message-State: ABy/qLYVKFTqp7GJz9wgcKzDzhPFkMGsFPLE+r7F3pqXds72knEWolqP mzA37ophA8fNh+q6aZg648E= X-Google-Smtp-Source: APBJJlEUh3KU5LH9y4EFPMSZ1xHsmeKWZfXDXyc/XJJg8W+/BzKkIAUuA40vhX0FBW2ykgaYCfW1Mg== X-Received: by 2002:a17:906:7698:b0:994:577:f9dd with SMTP id o24-20020a170906769800b009940577f9ddmr2032836ejm.9.1690388870981; Wed, 26 Jul 2023 09:27:50 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id n10-20020a170906164a00b00977cad140a8sm9766474ejd.218.2023.07.26.09.27.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 09:27:50 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v3 3/7] dt-bindings: arm: tegra: pmc: Move additionalProperties Date: Wed, 26 Jul 2023 18:27:40 +0200 Message-ID: <20230726162744.2113008-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230726162744.2113008-1-thierry.reding@gmail.com> References: <20230726162744.2113008-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding For indented subschemas it can be difficult to understand which block an additionalProperties property belongs to. Moving it closer to the beginning of a block is a good way to clarify this. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - add Reviewed-by: from Rob .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 0ac258bc7be0..d6f2c5862841 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -126,6 +126,7 @@ properties: description: The vast majority of hardware blocks of Tegra SoC belong to a core power domain, which has a dedicated voltage rail that powers the blocks. + additionalProperties: false properties: operating-points-v2: description: Should contain level, voltages and opp-supported-hw @@ -139,12 +140,11 @@ properties: - operating-points-v2 - "#power-domain-cells" - additionalProperties: false - i2c-thermtrip: type: object description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, hardware-triggered thermal reset will be enabled. + additionalProperties: false properties: nvidia,i2c-controller-id: $ref: /schemas/types.yaml#/definitions/uint32 @@ -176,10 +176,9 @@ properties: - nvidia,reg-addr - nvidia,reg-data - additionalProperties: false - powergates: type: object + additionalProperties: false description: | This node contains a hierarchy of power domain nodes, which should match the powergates on the Tegra SoC. Each powergate node represents a power- @@ -224,7 +223,6 @@ properties: "^[a-z0-9]+$": type: object additionalProperties: false - properties: clocks: minItems: 1 @@ -246,8 +244,6 @@ properties: - resets - '#power-domain-cells' - additionalProperties: false - patternProperties: "^[a-f0-9]+-[a-f0-9]+$": type: object From patchwork Wed Jul 26 16:27:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1813310 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=H1a9vdDR; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R9zpY4f0hz1yYc for ; Thu, 27 Jul 2023 02:28:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230102AbjGZQ2D (ORCPT ); Wed, 26 Jul 2023 12:28:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231820AbjGZQ1y (ORCPT ); Wed, 26 Jul 2023 12:27:54 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7546269E; Wed, 26 Jul 2023 09:27:53 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-51e429e1eabso10155935a12.2; Wed, 26 Jul 2023 09:27:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690388872; x=1690993672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lsEowniGr6Wk6wqHwLPaL+irpr9VN82cw7vXn+mEKas=; b=H1a9vdDRRR819uM5nfpyUg3KbCzHQ0VB8mH5XJ9IIApTLYJSZvzIV2h5eHKYuWoWJC fzlYkJ3v1ic8GlBu/Qhf2dS798nm//R9/pWB9xvZqHMqltepEdv/jyAQZNwvMdl1xHS7 hTGJwOeYi6ilHt7ExWhwn6cE+IRdip1eBIyD2D6hAmLKNdUbPsZA/ZU9nfEUaLQqPZzu TCzLhs9w+CIWqVnr8XxpasMyOyA7IwmwQZp1iwVPXAoBTNCEtaDHprVEagFavoZxlvBa /lrH/eWcBsq/E8e/J1LoftpCYUJLoeDMBHOTQmCDkjhpKINr5ZYB3I1Wcq1KD4VAG0bo UU9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690388872; x=1690993672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lsEowniGr6Wk6wqHwLPaL+irpr9VN82cw7vXn+mEKas=; b=I98doVuHRq96tgis0IQFF4Mf8533Iq6SfgaKQDjEGqXlVXjMRN6orwY63E23WbMTXW lXUhtDUNlKh+dpphaOK5WlKH/rdbxp7mxg/1NB2z/XrHpBqdMW5AWt+MZ3fp9E2HzmYY Mx3sYqMjbuuNC1A9a/BW8dkgKJbttwEY1niltsrfCwKsvAqQ6pRmf9hQSAPtX9IJj/0h ygutk4Dh79eJgEeMnh75bab8+83s8p9HffWXwk5PJ2o7I6FEoJtuwT4gvGv69ryfIQ0e bj+OHGMsQ+yoxH2P9u4VVVsFz/v3K5BwOGQp2AF+EUfjrTb9MgWjZJdy/TV4sq7V9ILh K8iQ== X-Gm-Message-State: ABy/qLarn+CwMbQTXaZzhoYFK1Do2y7Qj8dXI27FsuWaGVMvLvN0oonA dEyGAo8d5/V+FkDRIS9go1M= X-Google-Smtp-Source: APBJJlGncj+O28VUzSn0902FqhpKnKY2t1ZvAuNe19swUVOlL+4RDlv6VKIcjPDIkFYOu2xl6JQjtA== X-Received: by 2002:aa7:df8b:0:b0:522:1fd2:ca7a with SMTP id b11-20020aa7df8b000000b005221fd2ca7amr2040106edy.29.1690388872113; Wed, 26 Jul 2023 09:27:52 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id bc14-20020a056402204e00b0051e0be09297sm9027325edb.53.2023.07.26.09.27.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 09:27:51 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v3 4/7] dt-bindings: arm: tegra: pmc: Increase maximum number of clocks per powergate Date: Wed, 26 Jul 2023 18:27:41 +0200 Message-ID: <20230726162744.2113008-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230726162744.2113008-1-thierry.reding@gmail.com> References: <20230726162744.2113008-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Some powergate definitions need more than 8 clocks, so bump the number up to 10, which is the current maximum in any known device tree file. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - add Acked-by: from Rob .../devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index d6f2c5862841..a336a75d8b82 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -226,7 +226,7 @@ properties: properties: clocks: minItems: 1 - maxItems: 8 + maxItems: 10 resets: minItems: 1 From patchwork Wed Jul 26 16:27:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1813315 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=GouSE/Qn; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R9zpb5ymnz1yYc for ; Thu, 27 Jul 2023 02:28:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231820AbjGZQ2F (ORCPT ); Wed, 26 Jul 2023 12:28:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232146AbjGZQ14 (ORCPT ); Wed, 26 Jul 2023 12:27:56 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C797D26A6; Wed, 26 Jul 2023 09:27:54 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-52227142a27so5375519a12.1; Wed, 26 Jul 2023 09:27:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690388873; x=1690993673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0L6qU+JLeMKGvCz89GoBCTy3/nCx4gl/pCLxBD3xdYk=; b=GouSE/QnbBR3XgiJ7iqjva/uK1g7KFEi9xwnxndKG0EHgMlGHyjVbdUWzbMaC/enhc z2K6lmXBpBU0P9Bgwblsq/y1g82UPlMVwPbsDBcR6J98USfunrSiCz4RMB14viRD3vqA pzkb6JfsriXBGo4tyxRJFnl9LGRYHcYgUTr7IIeLSgB96GRE0HRcrKZuugC8S/Rsj/qr iAVamD7PemGjEfwoRfVLA76Yj4+fJ5UXMdWPVQ9njY65cXEiN9LwEXywIA6u+jEZI3Xx qJFBM2RSzQBNuG7MQxHmyXarzm1ebn/eHvulUO7LszQ2AvYDh0LAvCeTDJnwsw7mXKrh EQPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690388873; x=1690993673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0L6qU+JLeMKGvCz89GoBCTy3/nCx4gl/pCLxBD3xdYk=; b=Mg9WffXSfcWA8Qx/IyYIwJWai8ZSSiVz1r3EqnwgJjQMidhqzm3Jc6moPmh3C4eaem myZjMbijO0lJyAsMb9jKNvEtwhgd9sn4shlyP+ssQT2gZUt9glFlfjbUJ8IJzBSIWA40 vCRtZ9B69wDd8hOzuN2/rDiHqeUkZLN6fdjTVHKvxBuD5BZnDgav2xOXFbC7Oa0wQ/DD WnpEazRtVpKwPm0cO0cI+3L9gS9dOypG8kCKQ1FvPBjLl9hBuVxywtaSjrMfUta1d0JM z2vGcV+UBijRC5fQYAGf2+HkeTv8pXe0ds0FTyvqZKwHxksv9CwmiGXj8jQnDviZaY6j eqQg== X-Gm-Message-State: ABy/qLb4UsEnp8XxP90KLQR5+7Lmmw6TzNdZ3FC5g80X/yz1vbVlWL3i DnJAMi7YsABAWkAJkkxDZ5c= X-Google-Smtp-Source: APBJJlG3pbya0WJEyZ6B3LvvC2reSNTwQLjBSjysRvn7AM/+ljIQV/gCZnSefVuwIU38hoCYgYNJBg== X-Received: by 2002:aa7:c1d2:0:b0:51e:eaf:4fea with SMTP id d18-20020aa7c1d2000000b0051e0eaf4feamr1763282edp.35.1690388873087; Wed, 26 Jul 2023 09:27:53 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id p6-20020a05640210c600b0052217b3a10dsm6229588edu.63.2023.07.26.09.27.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 09:27:52 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v3 5/7] dt-bindings: arm: tegra: pmc: Restructure pad configuration node schema Date: Wed, 26 Jul 2023 18:27:42 +0200 Message-ID: <20230726162744.2113008-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230726162744.2113008-1-thierry.reding@gmail.com> References: <20230726162744.2113008-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding The pad configuration node schema in its current form can accidentally match other properties as well. Restructure the schema to better match how the device trees are using these. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- Changes in v3: - remove quirks that are no longer needed with latest dt-schema Changes in v2: - highlight quirks working around possible core schema - use phandle: true instead of fully redefining it - drop unneeded status property definition .../arm/tegra/nvidia,tegra20-pmc.yaml | 171 +++++++++++------- 1 file changed, 109 insertions(+), 62 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index a336a75d8b82..de1b23167658 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -244,69 +244,76 @@ properties: - resets - '#power-domain-cells' -patternProperties: - "^[a-f0-9]+-[a-f0-9]+$": + pinmux: type: object - description: - This is a Pad configuration node. On Tegra SOCs a pad is a set of - pins which are configured as a group. The pin grouping is a fixed - attribute of the hardware. The PMC can be used to set pad power state - and signaling voltage. A pad can be either in active or power down mode. - The support for power state and signaling voltage configuration varies - depending on the pad in question. 3.3V and 1.8V signaling voltages - are supported on pins where software controllable signaling voltage - switching is available. - - The pad configuration state nodes are placed under the pmc node and they - are referred to by the pinctrl client properties. For more information - see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. - The pad name should be used as the value of the pins property in pin - configuration nodes. - - The following pads are present on Tegra124 and Tegra132 - audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, - hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, - sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. - - The following pads are present on Tegra210 - audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, - debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, - hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, - sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. - - properties: - pins: - $ref: /schemas/types.yaml#/definitions/string - description: Must contain name of the pad(s) to be configured. - - low-power-enable: - $ref: /schemas/types.yaml#/definitions/flag - description: Configure the pad into power down mode. - - low-power-disable: - $ref: /schemas/types.yaml#/definitions/flag - description: Configure the pad into active mode. - - power-source: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or - TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - Power state can be configured on all Tegra124 and Tegra132 - pads. None of the Tegra124 or Tegra132 pads support signaling - voltage switching. - All of the listed Tegra210 pads except pex-cntrl support power - state configuration. Signaling voltage switching is supported - on below Tegra210 pads. - audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, - sdmmc3, spi, spi-hv, and uart. - - required: - - pins - - additionalProperties: false + additionalProperties: + type: object + description: | + This is a pad configuration node. On Tegra SoCs a pad is a set of pins + which are configured as a group. The pin grouping is a fixed attribute + of the hardware. The PMC can be used to set pad power state and + signaling voltage. A pad can be either in active or power down mode. + The support for power state and signaling voltage configuration varies + depending on the pad in question. 3.3V and 1.8V signaling voltages are + supported on pins where software controllable signaling voltage + switching is available. + + The pad configuration state nodes are placed under the pmc node and + they are referred to by the pinctrl client properties. For more + information see: + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + + The pad name should be used as the value of the pins property in pin + configuration nodes. + + The following pads are present on Tegra124 and Tegra132: + + audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, + hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, + pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, + usb_bias + + The following pads are present on Tegra210: + + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, + debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, + hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, + sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias + additionalProperties: false + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: Must contain name of the pad(s) to be configured. + + low-power-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into power down mode. + + low-power-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into active mode. + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The + values are defined in: + + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h + + Power state can be configured on all Tegra124 and Tegra132 pads. + None of the Tegra124 or Tegra132 pads support signaling voltage + switching. All of the listed Tegra210 pads except pex-cntrl support + power state configuration. Signaling voltage switching is supported + on the following Tegra210 pads: + + audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3, + spi, spi-hv, uart + + required: + - pins required: - compatible @@ -315,6 +322,46 @@ required: - clocks - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra124-pmc + then: + properties: + pinmux: + additionalProperties: + type: object + properties: + pins: + items: + enum: [ audio, bb, cam, comp, csia, csb, cse, dsi, dsib, + dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand, + pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, + usb_bias ] + + - if: + properties: + compatible: + contains: + const: nvidia,tegra210-pmc + then: + properties: + pinmux: + additionalProperties: + type: object + properties: + pins: + items: + enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie, + csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, + dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias, + pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, + usb-bias ] + additionalProperties: false dependencies: From patchwork Wed Jul 26 16:27:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1813313 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=MXJOVQ94; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R9zpZ6qC1z1ydm for ; Thu, 27 Jul 2023 02:28:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229715AbjGZQ2E (ORCPT ); Wed, 26 Jul 2023 12:28:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232311AbjGZQ15 (ORCPT ); Wed, 26 Jul 2023 12:27:57 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0887626A1; Wed, 26 Jul 2023 09:27:56 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-992ca792065so1135532066b.2; Wed, 26 Jul 2023 09:27:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690388874; x=1690993674; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nDS7h6vfbqbdn44ZCx2nQW3rrOLUzA1WpqdTNa3vHJE=; b=MXJOVQ949OZGG+0GVwiDV7Ojwb2r50qRb4Ec75dymMICXiZCu0x5/8AkprH+57GMuh 2e4VD7Qo1AoYkawt76X7owJw5t3g7M/upNalH9MXsG+12/c1dSrdSZ+xPD9ffrgDJ7XG 8dF4fD3Rp+wucxiQmQ0tKwP1DjZCQ98PQ1hje3BXlDZj1LkH21aGj044+b5Q23DKqsBL H3qvpV6uuG/6t/R41Vh2/TI8vPivw26NRdKgQOz4cKJH+ZjNVrL+0Iuq8tDOQv/HgOfp TsTP1Q9qR0yXu4Ta7RtrufHJWuarFd73VYZ8mZ0G7HzpRHOl0cL1xO0eEVxR3K3kK1WD JPiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690388874; x=1690993674; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nDS7h6vfbqbdn44ZCx2nQW3rrOLUzA1WpqdTNa3vHJE=; b=T2WEMnAq4zH1R4tbME15gjde+tUf2zKIRayAyYVSV5j3j/UtTZouNtiV4ShrzFCP7y gDJA0tsrvXi0qVuyFwZ5i4aFijZKpM5LJ9Lcy/7/6T7uk13OtkIxx581Czejfyuvd4nN 7VvZXqER6gqmhnocqS/4o3PfmeYufjoZD69FTNtaKYZeuyGCBhwVcTm1n0qAxkxVD1Ng +8QSOO2p1JiqGVgEqMOXHoMEx/v9BuTppLpu2bBPzLCQPFNFUymcNmiuvPzI1wa1wVro eHc2tFvdTOlqDKLcsZAbgIsZkTF4UW/dlEzgL3oh7s439kjWrAYgR/LD9SxINxmm3NaC W1Hg== X-Gm-Message-State: ABy/qLYERobokVs7PywqzKq+JxM8XhTG5UKgzYropM7oTVvc7Mnd5J5q 3mct5vFFiJRseUYH/vndCoVySb41n1w= X-Google-Smtp-Source: APBJJlGku7X3d+Slx7ozbqDE9ElTrdc4+nkl2jlBTEdb/3kOiwP0AJSzn2lgfnwuz+XJJhEqacscuA== X-Received: by 2002:a17:906:2219:b0:99b:cf7a:c8f1 with SMTP id s25-20020a170906221900b0099bcf7ac8f1mr847616ejs.70.1690388874450; Wed, 26 Jul 2023 09:27:54 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id o2-20020a1709061b0200b00992f309cfe8sm9860934ejg.178.2023.07.26.09.27.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 09:27:53 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v3 6/7] dt-bindings: arm: tegra: pmc: Reformat example Date: Wed, 26 Jul 2023 18:27:43 +0200 Message-ID: <20230726162744.2113008-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230726162744.2113008-1-thierry.reding@gmail.com> References: <20230726162744.2113008-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Reformat the example using 4 spaces for indentation. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - add Acked-by: from Rob .../arm/tegra/nvidia,tegra20-pmc.yaml | 77 +++++++++---------- 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index de1b23167658..a54b562e2a1c 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -371,47 +371,46 @@ dependencies: examples: - | - #include #include #include - tegra_pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x7000e400 0x400>; - core-supply = <®ulator>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #clock-cells = <1>; - - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <4587 3876>; - nvidia,core-pwr-off-time = <39065>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - pd_core: core-domain { - operating-points-v2 = <&core_opp_table>; - #power-domain-cells = <0>; - }; - - powergates { - pd_audio: aud { - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - resets = <&tegra_car 198>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_xusbss: xusba { - clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; - resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - }; + pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x7000e400 0x400>; + core-supply = <®ulator>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + pd_core: core-domain { + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + + powergates { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; }; From patchwork Wed Jul 26 16:27:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1813318 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; 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[2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id z5-20020a1709063ac500b009882e53a42csm9794261ejd.81.2023.07.26.09.27.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 09:27:55 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v3 7/7] dt-bindings: arm: tegra: pmc: Relicense and move into soc/tegra directory Date: Wed, 26 Jul 2023 18:27:44 +0200 Message-ID: <20230726162744.2113008-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230726162744.2113008-1-thierry.reding@gmail.com> References: <20230726162744.2113008-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Dual-license this binding for consistency with other Tegra bindings and move it into the soc/tegra directory. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - add Reviewed-by: from Rob .../bindings/{arm => soc}/tegra/nvidia,tegra20-pmc.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/{arm => soc}/tegra/nvidia,tegra20-pmc.yaml (99%) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml similarity index 99% rename from Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml rename to Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml index a54b562e2a1c..b86f6f53ca95 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml @@ -1,7 +1,7 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# +$id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Tegra Power Management Controller (PMC)