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Tue, 25 Jul 2023 14:39:56 -0400 (EDT) Received: from SSI-EX2.ssi.samsung.com (105.128.2.227) by SSI-EX1.ssi.samsung.com (105.128.2.226) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2375.24; Tue, 25 Jul 2023 11:39:55 -0700 Received: from SSI-EX2.ssi.samsung.com ([105.128.2.227]) by SSI-EX2.ssi.samsung.com ([105.128.2.227]) with mapi id 15.01.2375.024; Tue, 25 Jul 2023 11:39:55 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [Qemu PATCH v2 1/9] hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output payload of identify memory device command Thread-Topic: [Qemu PATCH v2 1/9] hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output payload of identify memory device command Thread-Index: AQHZvydoRKWfeAB5G06EOZO9oxzjmQ== Date: Tue, 25 Jul 2023 18:39:55 +0000 Message-ID: <20230725183939.2741025-2-fan.ni@samsung.com> In-Reply-To: <20230725183939.2741025-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrLKsWRmVeSWpSXmKPExsWy7djX87p/xA6kGCzbbWHRfX4Do8X0qRcY LVbfXMNo0dD0iMWiZfd7Jov9T5+zWKxaeI3N4vysUywWzyc+Z7JYuuQRs8Xx3h0sDtweFyZP YPVY3ODqsXPWXXaPliNvgbw9L5k8Nn78z+7x5NpmJo/Nr18we0ydXe/xeZNcAFcUl01Kak5m WWqRvl0CV8b6Q7sYC27zVvT92s/ewNjL3cXIySEhYCKxY1kHaxcjF4eQwEpGiaX3prNDOK1M ElNb/rLBVE18P4MdxBYSWMsoMWlWFETRJ0aJrjN/WSCcZYwSra2nWUGq2AQUJfZ1bQfrFhEw ljh2eAkzSBGzwFsWiY9r3oB1CAt0MEoce/MVLCMi0MsosXDWG2aIFj2JeVPXs4DYLAKqEh0r dzCB2LwClhK/z20GO4RTwEri2ZfZYOsYBcQkvp9aA1bDLCAucevJfCaIwwUlFs3ewwxhi0n8 2/UQ6iF5ick/ZkDZihL3v79kh+jVk7gxdQobhK0tsWzha2aIvYISJ2c+YYGol5Q4uOIG2AcS AtM5JSY2/INa5iLRsegJI4QtLfH37jKgOAeQnSyx6iMXRDhHYv6SLVBzrCUW/lnPNIFRZRaS s2chOWMWkjNmITljASPLKkbx0uLi3PTUYuO81HK94sTc4tK8dL3k/NxNjMAUd/rf4YIdjLdu fdQ7xMjEwXiIUYKDWUmE1zBmX4oQb0piZVVqUX58UWlOavEhRmkOFiVxXkPbk8lCAumJJanZ qakFqUUwWSYOTqkGpqztsjPeZs1jVxCcpT/rzYzqzzc1HJodBVX2nlhnVRC0LfNyWVlZ18QA m5//fHUqmF0ObIxs9/bcJfXt3OkVSn8+ndLPiJcU5j3ZKebaemNr5tZJlvNW9rSsNfB0ncma 9OXpfRlX1rdZhVwB1+d67E9cvW/xxm1lqwQdWPMOhC6fMPeLNwvbi9qImZPOXNx9rejAgYQJ 1Q2ykb3tIa4ZtwL1F4lZ87H/O8B4ub1tpuQ57wafOX9XbxTq3B931XaGkPDbkNtMbadll/ml VrR23vZ9/GB64TxTFvFfp7lTXT1En/8WSvb0Z7e9sG/K+oLlZ1NO+iwvv7NqJn/czlof+Ssh bv78/0x7+LpLPv9+pcRSnJFoqMVcVJwIAEdHWNPgAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJIsWRmVeSWpSXmKPExsWS2cA0UfeP2IEUg+nPZC26z29gtJg+9QKj xeqbaxgtGpoesVi07H7PZLH/6XMWi1ULr7FZnJ91isXi+cTnTBZLlzxitjjeu4PFgdvjwuQJ rB6LG1w9ds66y+7RcuQtkLfnJZPHxo//2T2eXNvM5LH59Qtmj6mz6z0+b5IL4IrisklJzcks Sy3St0vgylh/aBdjwW3eir5f+9kbGHu5uxg5OSQETCQmvp/B3sXIxSEksJpRou/vcijnE6PE 9fM/mCGcZYwSiw8vYAdpYRNQlNjXtZ0NxBYRMJY4dngJM4jNLPCaReLbRW6QBmGBDkaJY2++ MkMU9TJKNF4whbD1JOZNXc8CYrMIqEp0rNzBBGLzClhK/D63GWgBB9A2S4mtE+NAwpwCVhLP vsxmBbEZBcQkvp9awwSxS1zi1pP5TBAvCEgs2XOeGcIWlXj5+B8rhC0vMfnHDDYIW1Hi/veX 7BC9ehI3pk5hg7C1JZYtfM0McYKgxMmZT1gg6iUlDq64wTKBUWIWknWzkLTPQtI+C0n7AkaW VYzipcXFuekVxUZ5qeV6xYm5xaV56XrJ+bmbGIGp4fS/w9E7GG/f+qh3iJGJg/EQowQHs5II r2HMvhQh3pTEyqrUovz4otKc1OJDjNIcLErivC+jJsYLCaQnlqRmp6YWpBbBZJk4OKUamHgm fd9z7/+NZcxrfwSsNd3eorZ9gessoW8SHK0vG6LnzbUWFtlu7nPWS1cs4Mj60/cz3/c5zPVr OhRteXmPs9L+7Q4aUd6T01bNm5OfupLNOIBxS/yau44TBcxVAmdViaZyrbGYxu//rYv74J1b jHHc37gyK3QmGC+dnlBw6fWcrcbX/3X1z3mq5SAU9oSlveF8Q81Xs5fZl+c46l6tY42ecPPG 5kl+/w7PvdEVs+dP8dqS571XnYw2eUpOyVu+8zbvJO9+o6Zpl4w39Fjvf2Nvynnsw5zlE/zZ N1Qddym+N6cm6emWF+afrvpdlPHSLEgz8k6TO2C06RWH2Y/vLrbla18d+XVJznpdoti+3f+U WIozEg21mIuKEwF9Cw0WfAMAAA== X-CMS-MailID: 20230725183956uscas1p17a64ec512cdf5b9348451926d6f0b224 CMS-TYPE: 301P X-CMS-RootMailID: 20230725183956uscas1p17a64ec512cdf5b9348451926d6f0b224 References: <20230725183939.2741025-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.12; envelope-from=fan.ni@samsung.com; helo=mailout2.w2.samsung.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fan Ni Based on CXL spec 3.0 Table 8-94 (Identify Memory Device Output Payload), dynamic capacity event log size should be part of output of the Identify command. Add dc_event_log_size to the output payload for the host to get the info. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index ad7a6116e4..b013e30314 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -21,6 +21,8 @@ #include "sysemu/hostmem.h" #define CXL_CAPACITY_MULTIPLIER (256 * MiB) +/* Experimental value: dynamic capacity event log size */ +#define CXL_DC_EVENT_LOG_SIZE 8 /* * How to add a new command, example. The command set FOO, with cmd BAR. @@ -519,8 +521,9 @@ static CXLRetCode cmd_identify_memory_device(struct cxl_cmd *cmd, uint16_t inject_poison_limit; uint8_t poison_caps; uint8_t qos_telemetry_caps; + uint16_t dc_event_log_size; } QEMU_PACKED *id; - QEMU_BUILD_BUG_ON(sizeof(*id) != 0x43); + QEMU_BUILD_BUG_ON(sizeof(*id) != 0x45); CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d); @@ -543,6 +546,7 @@ static CXLRetCode cmd_identify_memory_device(struct cxl_cmd *cmd, st24_le_p(id->poison_list_max_mer, 256); /* No limit - so limited by main poison record limit */ stw_le_p(&id->inject_poison_limit, 0); + stw_le_p(&id->dc_event_log_size, CXL_DC_EVENT_LOG_SIZE); *len = sizeof(*id); return CXL_MBOX_SUCCESS; From patchwork Tue Jul 25 18:39:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 1812822 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Tue, 25 Jul 2023 11:39:55 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [Qemu PATCH v2 2/9] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support Thread-Topic: [Qemu PATCH v2 2/9] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support Thread-Index: AQHZvydoz7fRgsZIjkm5D4vXR5iWWg== Date: Tue, 25 Jul 2023 18:39:55 +0000 Message-ID: <20230725183939.2741025-3-fan.ni@samsung.com> In-Reply-To: <20230725183939.2741025-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrLKsWRmVeSWpSXmKPExsWy7djXc7p/xA6kGEz8ZmbRfX4Do8X0qRcY LVbfXMNo0dD0iMWiZfd7Jov9T5+zWKxaeI3N4vysUywWzyc+Z7JYuuQRs8Xx3h0sDtweFyZP YPVY3ODqsXPWXXaPliNvgbw9L5k8Nn78z+7x5NpmJo/Nr18we0ydXe/xeZNcAFcUl01Kak5m WWqRvl0CV8ar1XPYCnYbVSyYtZ+pgXGuWhcjJ4eEgIlE17ONrF2MXBxCAisZJfbdWM4I4bQy SZy5tZAJpmrC+RksEIm1jBJ/H/5ngnA+MUrM+7cTylnGKNHaepoVpIVNQFFiX9d2NhBbRMBY 4tjhJcwgRcwCb1kkPq55wwKSEBaol2h89hWsW0SghVGi4/0fRogOPYmV8/eDFbEIqEp0rNwB dgivgKXE1I7LYDWcAlYSz77MBtvGKCAm8f3UGrAaZgFxiVtP5kMdLiixaPYeZghbTOLfrods ELa8xOQfM6BsRYn731+yQ/TqSdyYOoUNwtaWWLbwNTPEXkGJkzOfsEDUS0ocXHEDHBgSAtM5 Jaas2cwIkXCR+N7dBLVYWmL6mstARRxAdrLEqo9cEOEciflLtkDNsZZY+Gc90wRGlVlIzp6F 5IxZSM6YheSMBYwsqxjFS4uLc9NTi43zUsv1ihNzi0vz0vWS83M3MQJT3Ol/hwt2MN669VHv ECMTB+MhRgkOZiURXsOYfSlCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeQ1tTyYLCaQnlqRmp6YW pBbBZJk4OKUamEx+nDv1gnvBR+W/PQK1zwzLbFnmplmGKH3o/ad/Vueu2KPYfX9XaywXL9yk EfP8xQIGhqAqRYGmgiyvnZO81gtsiwo558i8gK9Co3ez9sk3vFVKRzz6tt5LLfsdzHTpQPIU hWeVm2dYKOxXO6Fpz9N+VXlB+Hqv+M0Tn1nWrNpkkvHMOOjkkmzrb5r2k1++/H+Gc26NKO/v 38bi//s14o5/4KqfuOx85C/+9QxvFshM3JFnsez1xXOCcxp+FGptN635LWl19tPfpS7iGWb3 Q3Ii85PuSHRN0awTeigd4+spEJa4/cD0LfpWO5+uP7xr9US3DxqC/NYvPWe1frwz2Tj497PL V5i0v5w5u9Pl+jElluKMREMt5qLiRABR4GZy4AMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJIsWRmVeSWpSXmKPExsWS2cA0SfeP2IEUg+a98hbd5zcwWkyfeoHR YvXNNYwWDU2PWCxadr9nstj/9DmLxaqF19gszs86xWLxfOJzJoulSx4xWxzv3cHiwO1xYfIE Vo/FDa4eO2fdZfdoOfIWyNvzkslj48f/7B5Prm1m8tj8+gWzx9TZ9R6fN8kFcEVx2aSk5mSW pRbp2yVwZbxaPYetYLdRxYJZ+5kaGOeqdTFyckgImEhMOD+DpYuRi0NIYDWjROOmS0wQzidG iUv9DYwQzjJGicWHF7CDtLAJKErs69rOBmKLCBhLHDu8hBnEZhZ4zSLx7SI3iC0sUC/R+Owr 2CQRgRZGiVfHJzBCNOhJrJy/nwXEZhFQlehYuYMJxOYVsJSY2nEZqIYDaJulxNaJcSBhTgEr iWdfZrOC2IwCYhLfT61hgtglLnHryXwmiBcEJJbsOc8MYYtKvHz8jxXClpeY/GMGG4StKHH/ +0t2iF49iRtTp7BB2NoSyxa+ZoY4QVDi5MwnLBD1khIHV9xgmcAoMQvJullI2mchaZ+FpH0B I8sqRvHS4uLc9Ipi47zUcr3ixNzi0rx0veT83E2MwNRw+t/hmB2M92591DvEyMTBeIhRgoNZ SYTXMGZfihBvSmJlVWpRfnxRaU5q8SFGaQ4WJXFej9iJ8UIC6YklqdmpqQWpRTBZJg5OqQam CbcK4i8f8I/23rvTbZHKVg25yWziuX3aVevOf+6U5l4SOPGQpsHir5qnErJChUR8TQzLb8le SkpwPaQmNm2/V3KjwfPM2Bihcs2snL9e99otH897e/P05muHkg5Um625eKT0ghCT47R1LLXH fn1zeDH/3a7nK3PdzFbr959OC10dfnyP+6sIvaaAxZOVjSw3hj348b2vyDCl8dyfXUV5+oln 9jbOmpP0MrX2S4xCy43DrSrp/Q/+d3r6Rc3+kS4p8KZeXvCgnKdKpqjpNaeKoxtSXXbY32w5 ki11d+WHM5+eHmR6dmUnkyXHy8bg+F8uLxKCtijJOVmYfxcu5rRqFeouM/72fte1o4dfS55R YinOSDTUYi4qTgQAuFnZTHwDAAA= X-CMS-MailID: 20230725183956uscas1p296403063c710f4b546d4fec7650915c4 CMS-TYPE: 301P X-CMS-RootMailID: 20230725183956uscas1p296403063c710f4b546d4fec7650915c4 References: <20230725183939.2741025-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.12; envelope-from=fan.ni@samsung.com; helo=mailout2.w2.samsung.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fan Ni Per cxl spec 3.0, add dynamic capacity region representative based on Table 8-126 and extend the cxl type3 device definition to include dc region information. Also, based on info in 8.2.9.8.9.1, add 'Get Dynamic Capacity Configuration' mailbox support. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 72 +++++++++++++++++++++++++++++++++++++ hw/mem/cxl_type3.c | 6 ++++ include/hw/cxl/cxl_device.h | 17 +++++++++ 3 files changed, 95 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index b013e30314..0fe9f3eb5d 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -81,6 +81,8 @@ enum { #define GET_POISON_LIST 0x0 #define INJECT_POISON 0x1 #define CLEAR_POISON 0x2 + DCD_CONFIG = 0x48, /*r3.0: 8.2.9.8.9*/ + #define GET_DC_CONFIG 0x0 PHYSICAL_SWITCH = 0x51 #define IDENTIFY_SWITCH_DEVICE 0x0 }; @@ -939,6 +941,71 @@ static CXLRetCode cmd_media_clear_poison(struct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } +/* + * cxl spec 3.0: 8.2.9.8.9.1 + * Get Dynamic Capacity Configuration + **/ +static CXLRetCode cmd_dcd_get_dyn_cap_config(struct cxl_cmd *cmd, + CXLDeviceState *cxl_dstate, + uint16_t *len) +{ + struct get_dyn_cap_config_in_pl { + uint8_t region_cnt; + uint8_t start_region_id; + } QEMU_PACKED; + + struct get_dyn_cap_config_out_pl { + uint8_t num_regions; + uint8_t rsvd1[7]; + struct { + uint64_t base; + uint64_t decode_len; + uint64_t region_len; + uint64_t block_size; + uint32_t dsmadhandle; + uint8_t flags; + uint8_t rsvd2[3]; + } QEMU_PACKED records[]; + } QEMU_PACKED; + + struct get_dyn_cap_config_in_pl *in = (void *)cmd->payload; + struct get_dyn_cap_config_out_pl *out = (void *)cmd->payload; + struct CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, + cxl_dstate); + uint16_t record_count = 0, i; + uint16_t out_pl_len; + uint8_t start_region_id = in->start_region_id; + + if (start_region_id >= ct3d->dc.num_regions) { + return CXL_MBOX_INVALID_INPUT; + } + + record_count = MIN(ct3d->dc.num_regions - in->start_region_id, + in->region_cnt); + + out_pl_len = sizeof(*out) + record_count * sizeof(out->records[0]); + assert(out_pl_len <= CXL_MAILBOX_MAX_PAYLOAD_SIZE); + + memset(out, 0, out_pl_len); + out->num_regions = record_count; + for (i = 0; i < record_count; i++) { + stq_le_p(&out->records[i].base, + ct3d->dc.regions[start_region_id + i].base); + stq_le_p(&out->records[i].decode_len, + ct3d->dc.regions[start_region_id + i].decode_len); + stq_le_p(&out->records[i].region_len, + ct3d->dc.regions[start_region_id + i].len); + stq_le_p(&out->records[i].block_size, + ct3d->dc.regions[start_region_id + i].block_size); + stl_le_p(&out->records[i].dsmadhandle, + ct3d->dc.regions[start_region_id + i].dsmadhandle); + out->records[i].flags = ct3d->dc.regions[start_region_id + i].flags; + } + + *len = out_pl_len; + return CXL_MBOX_SUCCESS; +} + #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_DATA_CHANGE (1 << 2) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -977,6 +1044,8 @@ static struct cxl_cmd cxl_cmd_set[256][256] = { cmd_media_inject_poison, 8, 0 }, [MEDIA_AND_POISON][CLEAR_POISON] = { "MEDIA_AND_POISON_CLEAR_POISON", cmd_media_clear_poison, 72, 0 }, + [DCD_CONFIG][GET_DC_CONFIG] = { "DCD_GET_DC_CONFIG", + cmd_dcd_get_dyn_cap_config, 2, 0 }, }; static struct cxl_cmd cxl_cmd_set_sw[256][256] = { @@ -1164,6 +1233,9 @@ void cxl_initialize_mailbox(CXLDeviceState *cxl_dstate, bool switch_cci) } for (int set = 0; set < 256; set++) { for (int cmd = 0; cmd < 256; cmd++) { + if (!cxl_dstate->is_dcd && set == DCD_CONFIG) { + continue; + } if (cxl_dstate->cxl_cmd_set[set][cmd].handler) { struct cxl_cmd *c = &cxl_dstate->cxl_cmd_set[set][cmd]; struct cel_log *log = diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 862107c5ef..4d68824dfe 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1046,6 +1046,12 @@ static void ct3d_reset(DeviceState *dev) uint32_t *reg_state = ct3d->cxl_cstate.crb.cache_mem_registers; uint32_t *write_msk = ct3d->cxl_cstate.crb.cache_mem_regs_write_mask; + if (ct3d->dc.num_regions) { + ct3d->cxl_dstate.is_dcd = true; + } else { + ct3d->cxl_dstate.is_dcd = false; + } + cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DEVICE); cxl_device_register_init_common(&ct3d->cxl_dstate); } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index cd7f28dba8..dae39da438 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -212,6 +212,7 @@ typedef struct cxl_device_state { uint64_t mem_size; uint64_t pmem_size; uint64_t vmem_size; + bool is_dcd; struct cxl_cmd (*cxl_cmd_set)[256]; CPMUState cpmu[CXL_NUM_CPMU_INSTANCES]; @@ -382,6 +383,17 @@ typedef struct CXLPoison { typedef QLIST_HEAD(, CXLPoison) CXLPoisonList; #define CXL_POISON_LIST_LIMIT 256 +#define DCD_MAX_REGION_NUM 8 + +typedef struct CXLDCD_Region { + uint64_t base; + uint64_t decode_len; /* in multiples of 256MB */ + uint64_t len; + uint64_t block_size; + uint32_t dsmadhandle; + uint8_t flags; +} CXLDCD_Region; + struct CXLType3Dev { /* Private */ PCIDevice parent_obj; @@ -413,6 +425,11 @@ struct CXLType3Dev { unsigned int poison_list_cnt; bool poison_list_overflowed; uint64_t poison_list_overflow_ts; + + struct dynamic_capacity { + uint8_t num_regions; /* 0-8 regions */ + struct CXLDCD_Region regions[DCD_MAX_REGION_NUM]; + } dc; }; #define TYPE_CXL_TYPE3 "cxl-type3" From patchwork Tue Jul 25 18:39:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 1812813 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Tue, 25 Jul 2023 11:39:55 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [Qemu PATCH v2 3/9] include/hw/cxl/cxl_device: Rename mem_size as static_mem_size for type3 memory devices Thread-Topic: [Qemu PATCH v2 3/9] include/hw/cxl/cxl_device: Rename mem_size as static_mem_size for type3 memory devices Thread-Index: AQHZvydogN6RnRodckK9r+0ZvWb2uQ== Date: Tue, 25 Jul 2023 18:39:55 +0000 Message-ID: <20230725183939.2741025-4-fan.ni@samsung.com> In-Reply-To: <20230725183939.2741025-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJKsWRmVeSWpSXmKPExsWy7djX87p/xA6kGExqt7ToPr+B0WL61AuM FqtvrmG0aGh6xGLRsvs9k8X+p89ZLFYtvMZmcX7WKRaL5xOfM1ksXfKI2eJ47w4WB26PC5Mn sHosbnD12DnrLrtHy5G3QN6el0weGz/+Z/d4cm0zk8fm1y+YPabOrvf4vEkugCuKyyYlNSez LLVI3y6BK2NjXztzQbNMxbsHp1kaGDeJdTFycEgImEjMe6XXxcjFISSwklFi+/QNrF2MnEBO K5PE+WnKIDZIzfWXP9kgitYySvSu3cUEUfSJUWLRdDOIxDJGidbW02DdbAKKEvu6trOB2CIC xhLHDi9hBiliFnjLIvFxzRsWkISwQKnE/Bm7WSCKqiQurFsP1aAn8XfXBbA4i4CqRMfKHWDb eAUsJRYeWs0IYnMKWEk8+zIbbBmjgJjE91NrwGqYBcQlbj2ZzwRxtqDEotl7mCFsMYl/ux6y QdjyEpN/zICyFSXuf3/JDtGrJ3Fj6hQ2CFtbYtnC18wQewUlTs58wgJRLylxcMUNFpBnJAQm c0q0XzgNlXCRmLJ8MSOELS3x9+4yJkj4Jkus+sgFEc6RmL9kC1S5tcTCP+uZJjCqzEJy9iwk Z8xCcsYsJGcsYGRZxSheWlycm55abJSXWq5XnJhbXJqXrpecn7uJEZjaTv87nL+D8fqtj3qH GJk4GA8xSnAwK4nwGsbsSxHiTUmsrEotyo8vKs1JLT7EKM3BoiTOa2h7MllIID2xJDU7NbUg tQgmy8TBKdXAtOLTFusnLayvHBzceEwvKv/nnROs/C32gKteZPGbPaxT+l6n7Tleuyvp6yTW A9evs688eHH6jXDvLrkTWVqR1+U0mXx1D/l8mNvLnGZkqvLgYGa+BHvzgjdvBVy8HK41NO8R 3bM0h1P4/78HbhatgdZm3K4uT0JX9TJ/mLwxgY119obYgx0Nk9jW3VphoFMU564b2tihEFit Hmpvu/6tf5bN3AfHLlz0LNxt07ho5e+Lfkl8McLpL27fcfK7ckL+tpqMyTqxQmUjsRX6TL5q 516vM/9/86V/lMv/T45xB56ZMXjOWyt3h7nQr7Xzo+/8iYtXOGS67WD8PIste9aX2dOWVziH TgjMvqnDdlRaiaU4I9FQi7moOBEApGarQdwDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOIsWRmVeSWpSXmKPExsWS2cA0SfeP2IEUgy0TlSy6z29gtJg+9QKj xeqbaxgtGpoesVi07H7PZLH/6XMWi1ULr7FZnJ91isXi+cTnTBZLlzxitjjeu4PFgdvjwuQJ rB6LG1w9ds66y+7RcuQtkLfnJZPHxo//2T2eXNvM5LH59Qtmj6mz6z0+b5IL4IrisklJzcks Sy3St0vgytjY185c0CxT8e7BaZYGxk1iXYycHBICJhLXX/5k62Lk4hASWM0osezORjaQhJDA J0aJ7W0uEIlljBKLDy9gB0mwCShK7OvaDlYkImAscezwEmYQm1ngNYvEt4vcILawQKnE/Bm7 WSBqqiRWdZ1jhrD1JP7uugAWZxFQlehYuYMJxOYVsJRYeGg1YxcjB9AyS4mtE+NAwpwCVhLP vsxmBbEZBcQkvp9awwSxSlzi1pP5TBAPCEgs2XOeGcIWlXj5+B8rhC0vMfnHDDYIW1Hi/veX 7BC9ehI3pk5hg7C1JZYtfM0McYKgxMmZT1gg6iUlDq64wTKBUWIWknWzkLTPQtI+C0n7AkaW VYzipcXFuekVxUZ5qeV6xYm5xaV56XrJ+bmbGIFp4fS/w9E7GG/f+qh3iJGJg/EQowQHs5II r2HMvhQh3pTEyqrUovz4otKc1OJDjNIcLErivC+jJsYLCaQnlqRmp6YWpBbBZJk4OKUamKZ9 Y3e5fdm9uTK/PHaeoOhLppwDU/2c74fMEf1h1XvdpHeFRIDT5RmT8rdrh21fukg399QP7flf 7N7yScYtVL+5OvDSLc/X952UQxn7nlT52l4O7bdIlzumJymzcvmdwqLdpUF3A84uC11+s1W8 3mJtY+1W52thdz/4GwVu33GkmHluY1n1DEUfmRPxacdSeebNUvRpu8qwy7Vgx6FinSkrFoXG BbCvfZWTsJtFTvWcnIpS03PO6HXrnPa/vrDX8Po95g27dr4UqRS6e49ZmPPRstqk1e3HbuUF +R3WaVv3q8OMbw2Xw1758vzySk41620Wi6PjTv4uUXlwtFgn38BRs3b+ss98Wb6eETFRSizF GYmGWsxFxYkA1BosnnoDAAA= X-CMS-MailID: 20230725183956uscas1p153242eb4b12cb9cb6529476b4e9058c4 CMS-TYPE: 301P X-CMS-RootMailID: 20230725183956uscas1p153242eb4b12cb9cb6529476b4e9058c4 References: <20230725183939.2741025-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.12; envelope-from=fan.ni@samsung.com; helo=mailout2.w2.samsung.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fan Ni Rename mem_size as static_mem_size for type3 memdev to cover static RAM and pmem capacity, preparing for the introduction of dynamic capacity to support dynamic capacity devices. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 5 +++-- hw/mem/cxl_type3.c | 8 ++++---- include/hw/cxl/cxl_device.h | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 0fe9f3eb5d..dd5ea95af8 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -540,7 +540,8 @@ static CXLRetCode cmd_identify_memory_device(struct cxl_cmd *cmd, snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0); - stq_le_p(&id->total_capacity, cxl_dstate->mem_size / CXL_CAPACITY_MULTIPLIER); + stq_le_p(&id->total_capacity, + cxl_dstate->static_mem_size / CXL_CAPACITY_MULTIPLIER); stq_le_p(&id->persistent_capacity, cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER); stq_le_p(&id->volatile_capacity, cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER); stl_le_p(&id->lsa_size, cvc->get_lsa_size(ct3d)); @@ -879,7 +880,7 @@ static CXLRetCode cmd_media_clear_poison(struct cxl_cmd *cmd, struct clear_poison_pl *in = (void *)cmd->payload; dpa = ldq_le_p(&in->dpa); - if (dpa + CXL_CACHE_LINE_SIZE > cxl_dstate->mem_size) { + if (dpa + CXL_CACHE_LINE_SIZE > cxl_dstate->static_mem_size) { return CXL_MBOX_INVALID_PA; } diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 4d68824dfe..3d7acffcb7 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -748,7 +748,7 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) } address_space_init(&ct3d->hostvmem_as, vmr, v_name); ct3d->cxl_dstate.vmem_size = memory_region_size(vmr); - ct3d->cxl_dstate.mem_size += memory_region_size(vmr); + ct3d->cxl_dstate.static_mem_size += memory_region_size(vmr); g_free(v_name); } @@ -771,7 +771,7 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) } address_space_init(&ct3d->hostpmem_as, pmr, p_name); ct3d->cxl_dstate.pmem_size = memory_region_size(pmr); - ct3d->cxl_dstate.mem_size += memory_region_size(pmr); + ct3d->cxl_dstate.static_mem_size += memory_region_size(pmr); g_free(p_name); } @@ -984,7 +984,7 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d, return -EINVAL; } - if (*dpa_offset > ct3d->cxl_dstate.mem_size) { + if (*dpa_offset > ct3d->cxl_dstate.static_mem_size) { return -EINVAL; } @@ -1148,7 +1148,7 @@ static bool set_cacheline(CXLType3Dev *ct3d, uint64_t dpa_offset, uint8_t *data) return false; } - if (dpa_offset + CXL_CACHE_LINE_SIZE > ct3d->cxl_dstate.mem_size) { + if (dpa_offset + CXL_CACHE_LINE_SIZE > ct3d->cxl_dstate.static_mem_size) { return false; } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index dae39da438..503c344326 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -209,7 +209,7 @@ typedef struct cxl_device_state { } timestamp; /* memory region size, HDM */ - uint64_t mem_size; + uint64_t static_mem_size; uint64_t pmem_size; uint64_t vmem_size; bool is_dcd; From patchwork Tue Jul 25 18:39:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 1812814 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Tue, 25 Jul 2023 11:39:56 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [Qemu PATCH v2 4/9] hw/mem/cxl_type3: Add support to create DC regions to type3 memory devices Thread-Topic: [Qemu PATCH v2 4/9] hw/mem/cxl_type3: Add support to create DC regions to type3 memory devices Thread-Index: AQHZvydoCwFjnM0gJE6KDcVANjM/Og== Date: Tue, 25 Jul 2023 18:39:55 +0000 Message-ID: <20230725183939.2741025-5-fan.ni@samsung.com> In-Reply-To: <20230725183939.2741025-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJKsWRmVeSWpSXmKPExsWy7djXc7p/xQ6kGCzayWLRfX4Do8X0qRcY LVbfXMNo0dD0iMWiZfd7Jov9T5+zWKxaeI3N4vysUywWzyc+Z7JYuuQRs8Xx3h0sDtweFyZP YPVY3ODqsXPWXXaPliNvgbw9L5k8Nn78z+7x5NpmJo/Nr18we0ydXe/xeZNcAFcUl01Kak5m WWqRvl0CV8ad5v9MBSskKhY1XGNsYNwt3MXIySEhYCLxa/N+dhBbSGAlo8SKpbxdjFxAdiuT xPIpv9lhik5f+8QOkVjLKLHxxwYWCOcTo0TD6wdMEM4yRok37b+YQVrYBBQl9nVtZwOxRQSM JY4dXsIMUsQs8JZF4uOaNywgCWGBTIl9246zQBTlSdz5uRzK1pO43r0HzGYRUJXoWLmDCcTm FbCUmPVkE9hQTgEriWdfZrOC2IwCYhLfT60Bq2EWEJe49WQ+E8TdghKLZu9hhrDFJP7tesgG YctLTP4xA8pWlLj//SU7RK+exI2pU9ggbG2JZQtfM0PsFZQ4OfMJC0S9pMTBFTeg7MmcEs/P 23QxcgDZLhL7/qpAhKUlrl6fygwRTpZY9ZELIpwjMX/JFqhOa4mFf9YzTWBUmYXk6FlIjpiF 5IhZSI5YwMiyilG8tLg4Nz212DgvtVyvODG3uDQvXS85P3cTIzC1nf53uGAH461bH/UOMTJx MB5ilOBgVhLhNYzZlyLEm5JYWZValB9fVJqTWnyIUZqDRUmc19D2ZLKQQHpiSWp2ampBahFM lomDU6qBacL8qHIrz7oZ3FcFWQLXenA+/LXnwJ7psjsndhp+uuckHLbx79aPtUFvXkjtcNFY v25u6sXfF9wPKS6dGNO3PWGXl0U529YrDOJRsyet+6e3Zff5Y2tF7Nl4J9VzXV4wYcv2VUl6 19aesV3rb6R2g2lK3rNQ0Vj/s1qGK5ckGUQwPVAzLjLc1jrjKnORhMC/7AMru2P3uF/p3d8k 2ni6/Yna6ZwkdtN7Sz5srfZvY9fcXflgnebPE61PNvPPyb7yqFLuRu7rO+cCnncbtP10rPp1 SqdmXu/mYrWHYTHyGj61iT9X5AS+P8CQPq2KL/rk439Lf+SVHFdYmPJVeP+UnxvqJ/tkPJ5c nMH202fag5tKLMUZiYZazEXFiQDh7ToF3AMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOIsWRmVeSWpSXmKPExsWS2cA0UfeP2IEUg+ZbWhbd5zcwWkyfeoHR YvXNNYwWDU2PWCxadr9nstj/9DmLxaqF19gszs86xWLxfOJzJoulSx4xWxzv3cHiwO1xYfIE Vo/FDa4eO2fdZfdoOfIWyNvzkslj48f/7B5Prm1m8tj8+gWzx9TZ9R6fN8kFcEVx2aSk5mSW pRbp2yVwZdxp/s9UsEKiYlHDNcYGxt3CXYycHBICJhKnr31i72Lk4hASWM0ocXF3BxOE84lR om3RaWYIZxmjxPzFqxlBWtgEFCX2dW1nA7FFBIwljh1ewgxiMwu8ZpH4dpEbxBYWyJTYt+04 SxcjB1BNnsT36/IQ5XoS17v3sIDYLAKqEh0rdzCB2LwClhKznmxiAykXArK3TowDCXMKWEk8 +zKbFcRmFBCT+H5qDRPEJnGJW0/mM0E8ICCxZM95ZghbVOLl43+sELa8xOQfM9ggbEWJ+99f skP06kncmDqFDcLWlli28DUzxAmCEidnPmGBqJeUOLjiBssERolZSNbNQtI+C0n7LCTtCxhZ VjGKlxYX56ZXFBvmpZbrFSfmFpfmpesl5+duYgSmhdP/DkfuYDx666PeIUYmDsZDjBIczEoi vIYx+1KEeFMSK6tSi/Lji0pzUosPMUpzsCiJ8wq5TowXEkhPLEnNTk0tSC2CyTJxcEo1MImu a/q+c11zlr5K8+Poitnr9s2Uyr5sJf9iSXTPNsVSz8qF09SP8Uc9ei4ufXOjYvJlibxOXpGi l7u3+hTZKLot/bZZ+QnH5XNmqrNDvnQ7GHzLTm6wen5rj/f88h4zw8fzVq7fXjG3XvdrVPNs vpIaeU431onCr4TZq6auCYsO+fPEyF3U3MOap2fzPo/y5A/d872uyn14eucIZ5exFe9tCaZr OoWnzq1Z8f1UzAEfntWXlcLKu+VPhsdxH246W3CQq/65Sk1cpvt0prrUpL+VaTyhB/zXLo0P 37bwTbiI86yGL90fBV5m7d7Eey9OsTJHKvjfLu/jm2zjeh+9Kde7WsnmcfW9pkl1kfNMJZbi jERDLeai4kQAM1kx7HoDAAA= X-CMS-MailID: 20230725183956uscas1p2008fba59779b70405c74d28a30e4fbaa CMS-TYPE: 301P X-CMS-RootMailID: 20230725183956uscas1p2008fba59779b70405c74d28a30e4fbaa References: <20230725183939.2741025-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.11; envelope-from=fan.ni@samsung.com; helo=mailout1.w2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fan Ni With the change, when setting up memory for type3 memory device, we can create DC regions A property 'num-dc-regions' is added to ct3_props to allow users to pass the number of DC regions to create. To make it easier, other region parameters like region base, length, and block size are hard coded. If needed, these parameters can be added easily. With the change, we can create DC regions with proper kernel side support as below: region=$(cat /sys/bus/cxl/devices/decoder0.0/create_dc_region) echo $region> /sys/bus/cxl/devices/decoder0.0/create_dc_region echo 256 > /sys/bus/cxl/devices/$region/interleave_granularity echo 1 > /sys/bus/cxl/devices/$region/interleave_ways echo "dc0" >/sys/bus/cxl/devices/decoder2.0/mode echo 0x40000000 >/sys/bus/cxl/devices/decoder2.0/dpa_size echo 0x40000000 > /sys/bus/cxl/devices/$region/size echo "decoder2.0" > /sys/bus/cxl/devices/$region/target0 echo 1 > /sys/bus/cxl/devices/$region/commit echo $region > /sys/bus/cxl/drivers/cxl_region/bind Signed-off-by: Fan Ni --- hw/mem/cxl_type3.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 3d7acffcb7..b29bb2309a 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -707,6 +707,34 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, } } +/* + * Create a dc region to test "Get Dynamic Capacity Configuration" command. + */ +static int cxl_create_dc_regions(CXLType3Dev *ct3d) +{ + int i; + uint64_t region_base = (ct3d->hostvmem ? ct3d->hostvmem->size : 0) + + (ct3d->hostpmem ? ct3d->hostpmem->size : 0); + uint64_t region_len = (uint64_t)2 * 1024 * 1024 * 1024; + uint64_t decode_len = 4; /* 4*256MB */ + uint64_t blk_size = 2 * 1024 * 1024; + struct CXLDCD_Region *region; + + for (i = 0; i < ct3d->dc.num_regions; i++) { + region = &ct3d->dc.regions[i]; + region->base = region_base; + region->decode_len = decode_len; + region->len = region_len; + region->block_size = blk_size; + /* dsmad_handle is set when creating cdat table entries */ + region->flags = 0; + + region_base += region->len; + } + + return 0; +} + static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { DeviceState *ds = DEVICE(ct3d); @@ -775,6 +803,10 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) g_free(p_name); } + if (cxl_create_dc_regions(ct3d)) { + return false; + } + return true; } @@ -1068,6 +1100,7 @@ static Property ct3_props[] = { DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename), DEFINE_PROP_UINT16("spdm", CXLType3Dev, spdm_port, 0), + DEFINE_PROP_UINT8("num-dc-regions", CXLType3Dev, dc.num_regions, 0), DEFINE_PROP_END_OF_LIST(), }; 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Tue, 25 Jul 2023 14:39:56 -0400 (EDT) Received: from SSI-EX2.ssi.samsung.com (105.128.2.227) by SSI-EX3.ssi.samsung.com (105.128.2.228) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2375.24; Tue, 25 Jul 2023 11:39:56 -0700 Received: from SSI-EX2.ssi.samsung.com ([105.128.2.227]) by SSI-EX2.ssi.samsung.com ([105.128.2.227]) with mapi id 15.01.2375.024; Tue, 25 Jul 2023 11:39:56 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [Qemu PATCH v2 5/9] hw/mem/cxl_type3: Add host backend and address space handling for DC regions Thread-Topic: [Qemu PATCH v2 5/9] hw/mem/cxl_type3: Add host backend and address space handling for DC regions Thread-Index: AQHZvydo9CDYVoLKukCzVG4QTwqoCg== Date: Tue, 25 Jul 2023 18:39:56 +0000 Message-ID: <20230725183939.2741025-6-fan.ni@samsung.com> In-Reply-To: <20230725183939.2741025-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFKsWRmVeSWpSXmKPExsWy7djXc7p/xQ6kGDzaJ2HRfX4Do8X0qRcY LVbfXMNo0dD0iMWiZfd7Jov9T5+zWKxaeI3N4vysUywWzyc+Z7JYuuQRs8Xx3h0sDtweFyZP YPVY3ODqsXPWXXaPliNvgbw9L5k8Nn78z+7x5NpmJo/Nr18we0ydXe/xeZNcAFcUl01Kak5m WWqRvl0CV8bGtZ2MBQ0TGCuezr/D2sC4Ka2LkZNDQsBE4sz550xdjFwcQgIrGSXOtZ1nh3Ba mSSWLXnODFO15F4nVNVaRondPR1sIAkhgU+MEm/ueEIklgHZ7b/AOtgEFCX2dW0HKxIRMJY4 dngJM0gRs8BbFomPa96wdDFycAgLZEvcvMoLUVMg0fTiHFS9nkRHF8QCFgFViRtHjjCClPMK WEpMPmQJEuYUsJJ49mU2K4jNKCAm8f3UGiYQm1lAXOLWk/lMEEcLSiyavQfqATGJf7seskHY 8hKTf8yAshUl7n9/yQ7RqydxY+oUNghbW2LZwtdgvbxAc07OfMICUS8pcXDFDRaQVyQEJnNK LF7cDpVwkTi8ZysrhC0tMX3NZbAXJQSSJVZ95III50jMX7IFqtxaYuGf9UwTGFVmITl7FpIz ZiE5YxaSMxYwsqxiFC8tLs5NTy02ykst1ytOzC0uzUvXS87P3cQITG6n/x3O38F4/dZHvUOM TByMhxglOJiVRHgNY/alCPGmJFZWpRblxxeV5qQWH2KU5mBREuc1tD2ZLCSQnliSmp2aWpBa BJNl4uCUamCKX5DE6lQ6w+V+2sKqrY0Xmso3N870LP0Wv0T/7F21d/8/+puZCpyRkLrKtspv 8YnQJx1aEw/efrvr3X7JK3Hv/NcKftdWj+metnnJm/Zw+3cWnadXWFyukOD7+u3l8bbAoLPV 82L2+93Qr7E1aTdewdYQfPF5O9PZc7VndpkaLXDJ3rEzUlu1vUbZ8yCTotKJlRfZX3jLpTVV iYqrrfj4UsG45PT88CzWWM1wIzuDP7brfN1XyyX58sbNy1vHXN4iUHnSpaz15aw/p7L+vf48 p2kGT/PNKYv+urf8m7B1+ZrFt+Z2heTPuMhVqOVTXXzogOOEl9Mvyih2WQcuPTGRzVZq7bNH /9uXSeZ3Z3xUYinOSDTUYi4qTgQA+m51Xd0DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOIsWRmVeSWpSXmKPExsWS2cA0SfeP2IEUg08bTC26z29gtJg+9QKj xeqbaxgtGpoesVi07H7PZLH/6XMWi1ULr7FZnJ91isXi+cTnTBZLlzxitjjeu4PFgdvjwuQJ rB6LG1w9ds66y+7RcuQtkLfnJZPHxo//2T2eXNvM5LH59Qtmj6mz6z0+b5IL4IrisklJzcks Sy3St0vgyti4tpOxoGECY8XT+XdYGxg3pXUxcnJICJhILLnXydTFyMUhJLCaUeLGhH2sEM4n Rolzp15BOcsYJeYvXs0I0sImoCixr2s7G4gtImAscezwEmYQm1ngNYvEt4vcXYwcHMIC2RI3 r/JClBRI/Nv3jwnC1pPo6OoAa2URUJW4ceQII0g5r4ClxORDliCmEJC5dWIcSAWngJXEsy+z WUFsRgExie+n1jBBLBKXuPVkPhPE/QISS/acZ4awRSVePv7HCmHLS0z+MYMNwlaUuP/9JTtE r57EjalT2CBsbYllC1+D9fIKCEqcnPmEBaJeUuLgihssExglZiFZNwtJ+ywk7bOQtC9gZFnF KF5aXJybXlFsnJdarlecmFtcmpeul5yfu4kRmBZO/zscs4Px3q2PeocYmTgYDzFKcDArifAa xuxLEeJNSaysSi3Kjy8qzUktPsQozcGiJM7rETsxXkggPbEkNTs1tSC1CCbLxMEp1cBUKvL0 3uH1OQecOuSmFGvP/Xjt9rW7m25vODHt9rK1de9r/TmF2oxLrd/LX31UoaPnlVcZ+u28qsQ9 0xmTeJiM+c7+7BXN3n71QPki8bbU6ogS4TciNTJct64mie6PttafFr0m93fvh943SalX7h9f feKsBkeR3yPbOcuWrRaqz+VRyckL+ifmmMl7nktmfdMlcdOMI5HKR8JdjinarHvJsfLo9sZ6 3gDT3Z/uhBRum/brdPUaFVs1ns1RhzKNPYRm8i8uPi/zr2rmNqW1z6ZsFp/yO/vkjG2fjzPN PjT1gTPzNQ7bpRlfrOsWNZ/OOdCUH/P794mWxYuqH5gZ/Y3oOWFYr2lnrcEjay/4w/qpEktx RqKhFnNRcSIAFCKCiXoDAAA= X-CMS-MailID: 20230725183957uscas1p1eeb8e8eccc6c00b460d183027642374b CMS-TYPE: 301P X-CMS-RootMailID: 20230725183957uscas1p1eeb8e8eccc6c00b460d183027642374b References: <20230725183939.2741025-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.11; envelope-from=fan.ni@samsung.com; helo=mailout1.w2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fan Ni Add (file/memory backed) host backend, all the dynamic capacity regions will share a single, large enough host backend. Set up address space for DC regions to support read/write operations to dynamic capacity for DCD. With the change, following supports are added: 1. add a new property to type3 device "nonvolatile-dc-memdev" to point to host memory backend for dynamic capacity; 2. add namespace for dynamic capacity for read/write support; 3. create cdat entries for each dynamic capacity region; 4. fix dvsec range registers to include DC regions. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 19 +++- hw/mem/cxl_type3.c | 203 +++++++++++++++++++++++++++++------- include/hw/cxl/cxl_device.h | 4 + 3 files changed, 185 insertions(+), 41 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index dd5ea95af8..0511b8e6f7 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -388,9 +388,11 @@ static CXLRetCode cmd_firmware_update_get_info(struct cxl_cmd *cmd, char fw_rev4[0x10]; } QEMU_PACKED *fw_info; QEMU_BUILD_BUG_ON(sizeof(*fw_info) != 0x50); + CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); if ((cxl_dstate->vmem_size < CXL_CAPACITY_MULTIPLIER) || - (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER)) { + (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER) || + (ct3d->dc.total_capacity < CXL_CAPACITY_MULTIPLIER)) { return CXL_MBOX_INTERNAL_ERROR; } @@ -531,7 +533,8 @@ static CXLRetCode cmd_identify_memory_device(struct cxl_cmd *cmd, CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d); if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER)) || - (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))) { + (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER)) || + (!QEMU_IS_ALIGNED(ct3d->dc.total_capacity, CXL_CAPACITY_MULTIPLIER))) { return CXL_MBOX_INTERNAL_ERROR; } @@ -566,9 +569,11 @@ static CXLRetCode cmd_ccls_get_partition_info(struct cxl_cmd *cmd, uint64_t next_pmem; } QEMU_PACKED *part_info = (void *)cmd->payload; QEMU_BUILD_BUG_ON(sizeof(*part_info) != 0x20); + CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER)) || - (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))) { + (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER)) || + (!QEMU_IS_ALIGNED(ct3d->dc.total_capacity, CXL_CAPACITY_MULTIPLIER))) { return CXL_MBOX_INTERNAL_ERROR; } @@ -880,7 +885,13 @@ static CXLRetCode cmd_media_clear_poison(struct cxl_cmd *cmd, struct clear_poison_pl *in = (void *)cmd->payload; dpa = ldq_le_p(&in->dpa); - if (dpa + CXL_CACHE_LINE_SIZE > cxl_dstate->static_mem_size) { + if (dpa + CXL_CACHE_LINE_SIZE >= cxl_dstate->static_mem_size + && ct3d->dc.num_regions == 0) { + return CXL_MBOX_INVALID_PA; + } + + if (ct3d->dc.num_regions && dpa + CXL_CACHE_LINE_SIZE >= + cxl_dstate->static_mem_size + ct3d->dc.total_capacity) { return CXL_MBOX_INVALID_PA; } diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index b29bb2309a..76bbd9f785 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -20,6 +20,7 @@ #include "hw/pci/spdm.h" #define DWORD_BYTE 4 +#define CXL_CAPACITY_MULTIPLIER (256 * MiB) /* Default CDAT entries for a memory region */ enum { @@ -33,8 +34,8 @@ enum { }; static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table, - int dsmad_handle, MemoryRegion *mr, - bool is_pmem, uint64_t dpa_base) + int dsmad_handle, uint8_t flags, + uint64_t dpa_base, uint64_t size) { g_autofree CDATDsmas *dsmas = NULL; g_autofree CDATDslbis *dslbis0 = NULL; @@ -53,9 +54,9 @@ static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table, .length = sizeof(*dsmas), }, .DSMADhandle = dsmad_handle, - .flags = is_pmem ? CDAT_DSMAS_FLAG_NV : 0, + .flags = flags, .DPA_base = dpa_base, - .DPA_length = memory_region_size(mr), + .DPA_length = size, }; /* For now, no memory side cache, plausiblish numbers */ @@ -137,9 +138,9 @@ static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table, * NV: Reserved - the non volatile from DSMAS matters * V: EFI_MEMORY_SP */ - .EFI_memory_type_attr = is_pmem ? 2 : 1, + .EFI_memory_type_attr = flags ? 2 : 1, .DPA_offset = 0, - .DPA_length = memory_region_size(mr), + .DPA_length = size, }; /* Header always at start of structure */ @@ -158,21 +159,28 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) g_autofree CDATSubHeader **table = NULL; CXLType3Dev *ct3d = priv; MemoryRegion *volatile_mr = NULL, *nonvolatile_mr = NULL; + MemoryRegion *dc_mr = NULL; int dsmad_handle = 0; int cur_ent = 0; int len = 0; int rc, i; + uint64_t vmr_size = 0, pmr_size = 0; - if (!ct3d->hostpmem && !ct3d->hostvmem) { + if (!ct3d->hostpmem && !ct3d->hostvmem && !ct3d->dc.num_regions) { return 0; } + if (ct3d->hostpmem && ct3d->hostvmem && ct3d->dc.host_dc) { + warn_report("The device has static ram and pmem and dynamic capacity"); + } + if (ct3d->hostvmem) { volatile_mr = host_memory_backend_get_memory(ct3d->hostvmem); if (!volatile_mr) { return -EINVAL; } len += CT3_CDAT_NUM_ENTRIES; + vmr_size = volatile_mr->size; } if (ct3d->hostpmem) { @@ -181,6 +189,19 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) return -EINVAL; } len += CT3_CDAT_NUM_ENTRIES; + pmr_size = nonvolatile_mr->size; + } + + if (ct3d->dc.num_regions) { + if (ct3d->dc.host_dc) { + dc_mr = host_memory_backend_get_memory(ct3d->dc.host_dc); + if (!dc_mr) { + return -EINVAL; + } + len += CT3_CDAT_NUM_ENTRIES * ct3d->dc.num_regions; + } else { + return -EINVAL; + } } table = g_malloc0(len * sizeof(*table)); @@ -190,8 +211,8 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) /* Now fill them in */ if (volatile_mr) { - rc = ct3_build_cdat_entries_for_mr(table, dsmad_handle++, volatile_mr, - false, 0); + rc = ct3_build_cdat_entries_for_mr(table, dsmad_handle++, + 0, 0, vmr_size); if (rc < 0) { return rc; } @@ -200,14 +221,37 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) if (nonvolatile_mr) { rc = ct3_build_cdat_entries_for_mr(&(table[cur_ent]), dsmad_handle++, - nonvolatile_mr, true, - (volatile_mr ? - memory_region_size(volatile_mr) : 0)); + CDAT_DSMAS_FLAG_NV, vmr_size, pmr_size); if (rc < 0) { goto error_cleanup; } cur_ent += CT3_CDAT_NUM_ENTRIES; } + + if (dc_mr) { + uint64_t region_base = vmr_size + pmr_size; + + /* + * Currently we create cdat entries for each region, should we only + * create dsmas table instead?? + * We assume all dc regions are non-volatile for now. + * + */ + for (i = 0; i < ct3d->dc.num_regions; i++) { + rc = ct3_build_cdat_entries_for_mr(&(table[cur_ent]) + , dsmad_handle++ + , CDAT_DSMAS_FLAG_NV | CDAT_DSMAS_FLAG_DYNAMIC_CAP + , region_base, ct3d->dc.regions[i].len); + if (rc < 0) { + goto error_cleanup; + } + ct3d->dc.regions[i].dsmadhandle = dsmad_handle - 1; + + cur_ent += CT3_CDAT_NUM_ENTRIES; + region_base += ct3d->dc.regions[i].len; + } + } + assert(len == cur_ent); *cdat_table = g_steal_pointer(&table); @@ -435,11 +479,24 @@ static void build_dvsecs(CXLType3Dev *ct3d) range2_size_hi = ct3d->hostpmem->size >> 32; range2_size_lo = (2 << 5) | (2 << 2) | 0x3 | (ct3d->hostpmem->size & 0xF0000000); + } else if (ct3d->dc.host_dc) { + range2_size_hi = ct3d->dc.host_dc->size >> 32; + range2_size_lo = (2 << 5) | (2 << 2) | 0x3 | + (ct3d->dc.host_dc->size & 0xF0000000); } - } else { + } else if (ct3d->hostpmem) { range1_size_hi = ct3d->hostpmem->size >> 32; range1_size_lo = (2 << 5) | (2 << 2) | 0x3 | (ct3d->hostpmem->size & 0xF0000000); + if (ct3d->dc.host_dc) { + range2_size_hi = ct3d->dc.host_dc->size >> 32; + range2_size_lo = (2 << 5) | (2 << 2) | 0x3 | + (ct3d->dc.host_dc->size & 0xF0000000); + } + } else { + range1_size_hi = ct3d->dc.host_dc->size >> 32; + range1_size_lo = (2 << 5) | (2 << 2) | 0x3 | + (ct3d->dc.host_dc->size & 0xF0000000); } dvsec = (uint8_t *)&(CXLDVSECDevice){ @@ -708,7 +765,8 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, } /* - * Create a dc region to test "Get Dynamic Capacity Configuration" command. + * Create dc regions. + * TODO: region parameters are hard coded, may need to change in the future. */ static int cxl_create_dc_regions(CXLType3Dev *ct3d) { @@ -739,7 +797,8 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { DeviceState *ds = DEVICE(ct3d); - if (!ct3d->hostmem && !ct3d->hostvmem && !ct3d->hostpmem) { + if (!ct3d->hostmem && !ct3d->hostvmem && !ct3d->hostpmem + && !ct3d->dc.num_regions) { error_setg(errp, "at least one memdev property must be set"); return false; } else if (ct3d->hostmem && ct3d->hostpmem) { @@ -807,6 +866,50 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) return false; } + ct3d->dc.total_capacity = 0; + if (ct3d->dc.host_dc) { + MemoryRegion *dc_mr; + char *dc_name; + uint64_t total_region_size = 0; + int i; + + dc_mr = host_memory_backend_get_memory(ct3d->dc.host_dc); + if (!dc_mr) { + error_setg(errp, "dynamic capacity must have backing device"); + return false; + } + /* FIXME: set dc as nonvolatile for now */ + memory_region_set_nonvolatile(dc_mr, true); + memory_region_set_enabled(dc_mr, true); + host_memory_backend_set_mapped(ct3d->dc.host_dc, true); + if (ds->id) { + dc_name = g_strdup_printf("cxl-dcd-dpa-dc-space:%s", ds->id); + } else { + dc_name = g_strdup("cxl-dcd-dpa-dc-space"); + } + address_space_init(&ct3d->dc.host_dc_as, dc_mr, dc_name); + + for (i = 0; i < ct3d->dc.num_regions; i++) { + total_region_size += ct3d->dc.regions[i].len; + } + /* Make sure the host backend is large enough to cover all dc range */ + if (total_region_size > memory_region_size(dc_mr)) { + error_setg(errp, + "too small host backend size, increase to %lu MiB or more", + total_region_size / 1024 / 1024); + return false; + } + + if (dc_mr->size % CXL_CAPACITY_MULTIPLIER != 0) { + error_setg(errp, "DC region size is unaligned to %lx", + CXL_CAPACITY_MULTIPLIER); + return false; + } + + ct3d->dc.total_capacity = total_region_size; + g_free(dc_name); + } + return true; } @@ -916,6 +1019,9 @@ err_release_cdat: err_free_special_ops: g_free(regs->special_ops); err_address_space_free: + if (ct3d->dc.host_dc) { + address_space_destroy(&ct3d->dc.host_dc_as); + } if (ct3d->hostpmem) { address_space_destroy(&ct3d->hostpmem_as); } @@ -935,6 +1041,9 @@ static void ct3_exit(PCIDevice *pci_dev) cxl_doe_cdat_release(cxl_cstate); spdm_sock_fini(ct3d->doe_spdm.socket); g_free(regs->special_ops); + if (ct3d->dc.host_dc) { + address_space_destroy(&ct3d->dc.host_dc_as); + } if (ct3d->hostpmem) { address_space_destroy(&ct3d->hostpmem_as); } @@ -999,16 +1108,24 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d, AddressSpace **as, uint64_t *dpa_offset) { - MemoryRegion *vmr = NULL, *pmr = NULL; + MemoryRegion *vmr = NULL, *pmr = NULL, *dc_mr = NULL; + uint64_t vmr_size = 0, pmr_size = 0, dc_size = 0; if (ct3d->hostvmem) { vmr = host_memory_backend_get_memory(ct3d->hostvmem); + vmr_size = memory_region_size(vmr); } if (ct3d->hostpmem) { pmr = host_memory_backend_get_memory(ct3d->hostpmem); + pmr_size = memory_region_size(pmr); + } + if (ct3d->dc.host_dc) { + dc_mr = host_memory_backend_get_memory(ct3d->dc.host_dc); + /* Do we want dc_size to be dc_mr->size or not?? */ + dc_size = ct3d->dc.total_capacity; } - if (!vmr && !pmr) { + if (!vmr && !pmr && !dc_mr) { return -ENODEV; } @@ -1016,19 +1133,19 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d, return -EINVAL; } - if (*dpa_offset > ct3d->cxl_dstate.static_mem_size) { + if ((*dpa_offset >= vmr_size + pmr_size + dc_size) || + (*dpa_offset >= vmr_size + pmr_size && ct3d->dc.num_regions == 0)) { return -EINVAL; } - if (vmr) { - if (*dpa_offset < memory_region_size(vmr)) { - *as = &ct3d->hostvmem_as; - } else { - *as = &ct3d->hostpmem_as; - *dpa_offset -= memory_region_size(vmr); - } - } else { + if (*dpa_offset < vmr_size) { + *as = &ct3d->hostvmem_as; + } else if (*dpa_offset < vmr_size + pmr_size) { *as = &ct3d->hostpmem_as; + *dpa_offset -= vmr_size; + } else { + *as = &ct3d->dc.host_dc_as; + *dpa_offset -= (vmr_size + pmr_size); } return 0; @@ -1101,6 +1218,8 @@ static Property ct3_props[] = { DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename), DEFINE_PROP_UINT16("spdm", CXLType3Dev, spdm_port, 0), DEFINE_PROP_UINT8("num-dc-regions", CXLType3Dev, dc.num_regions, 0), + DEFINE_PROP_LINK("nonvolatile-dc-memdev", CXLType3Dev, dc.host_dc, + TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_END_OF_LIST(), }; @@ -1167,33 +1286,43 @@ static void set_lsa(CXLType3Dev *ct3d, const void *buf, uint64_t size, static bool set_cacheline(CXLType3Dev *ct3d, uint64_t dpa_offset, uint8_t *data) { - MemoryRegion *vmr = NULL, *pmr = NULL; + MemoryRegion *vmr = NULL, *pmr = NULL, *dc_mr = NULL; AddressSpace *as; + uint64_t vmr_size = 0, pmr_size = 0, dc_size = 0; if (ct3d->hostvmem) { vmr = host_memory_backend_get_memory(ct3d->hostvmem); + vmr_size = memory_region_size(vmr); } if (ct3d->hostpmem) { pmr = host_memory_backend_get_memory(ct3d->hostpmem); + pmr_size = memory_region_size(pmr); } + if (ct3d->dc.host_dc) { + dc_mr = host_memory_backend_get_memory(ct3d->dc.host_dc); + dc_size = ct3d->dc.total_capacity; + } - if (!vmr && !pmr) { + if (!vmr && !pmr && !dc_mr) { return false; } - if (dpa_offset + CXL_CACHE_LINE_SIZE > ct3d->cxl_dstate.static_mem_size) { + if (dpa_offset >= vmr_size + pmr_size + dc_size) { + return false; + } + if (dpa_offset + CXL_CACHE_LINE_SIZE >= vmr_size + pmr_size + && ct3d->dc.num_regions == 0) { return false; } - if (vmr) { - if (dpa_offset < memory_region_size(vmr)) { - as = &ct3d->hostvmem_as; - } else { - as = &ct3d->hostpmem_as; - dpa_offset -= memory_region_size(vmr); - } - } else { + if (dpa_offset < vmr_size) { + as = &ct3d->hostvmem_as; + } else if (dpa_offset < vmr_size + pmr_size) { as = &ct3d->hostpmem_as; + dpa_offset -= vmr->size; + } else { + as = &ct3d->dc.host_dc_as; + dpa_offset -= (vmr_size + pmr_size); } address_space_write(as, dpa_offset, MEMTXATTRS_UNSPECIFIED, &data, diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 503c344326..1c99b05a66 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -427,6 +427,10 @@ struct CXLType3Dev { uint64_t poison_list_overflow_ts; struct dynamic_capacity { + HostMemoryBackend *host_dc; + AddressSpace host_dc_as; + uint64_t total_capacity; /* 256M aligned */ + uint8_t num_regions; /* 0-8 regions */ struct CXLDCD_Region regions[DCD_MAX_REGION_NUM]; } dc; From patchwork Tue Jul 25 18:39:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 1812818 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 header.s=mail20170921 header.b=g4EYZf8C; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R9Qs645lxz1yXx for ; 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Tue, 25 Jul 2023 18:39:57 +0000 (GMT) X-AuditID: cbfec36d-8a3ff7000001c913-42-64c016fd02fb Received: from SSI-EX2.ssi.samsung.com ( [105.128.2.145]) by ussmgxs1new.samsung.com (USCPEXMTA) with SMTP id A3.54.38326.CF610C46; Tue, 25 Jul 2023 14:39:57 -0400 (EDT) Received: from SSI-EX2.ssi.samsung.com (105.128.2.227) by SSI-EX2.ssi.samsung.com (105.128.2.227) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2375.24; Tue, 25 Jul 2023 11:39:56 -0700 Received: from SSI-EX2.ssi.samsung.com ([105.128.2.227]) by SSI-EX2.ssi.samsung.com ([105.128.2.227]) with mapi id 15.01.2375.024; Tue, 25 Jul 2023 11:39:56 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [Qemu PATCH v2 6/9] hw/mem/cxl_type3: Add DC extent list representative and get DC extent list mailbox support Thread-Topic: [Qemu PATCH v2 6/9] hw/mem/cxl_type3: Add DC extent list representative and get DC extent list mailbox support Thread-Index: AQHZvydobNJU5Smx1kW/FPcC4N6b9Q== Date: Tue, 25 Jul 2023 18:39:56 +0000 Message-ID: <20230725183939.2741025-7-fan.ni@samsung.com> In-Reply-To: <20230725183939.2741025-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJKsWRmVeSWpSXmKPExsWy7djXc7p/xQ6kGGzdI2XRfX4Do8X0qRcY LVbfXMNo0dD0iMWiZfd7Jov9T5+zWKxaeI3N4vysUywWzyc+Z7JYuuQRs8Xx3h0sDtweFyZP YPVY3ODqsXPWXXaPliNvgbw9L5k8Nn78z+7x5NpmJo/Nr18we0ydXe/xeZNcAFcUl01Kak5m WWqRvl0CV0bD4/iCz1oV794fZWlgfKfQxcjJISFgItG19TNLFyMXh5DASkaJqZeWsEI4rUwS K99MBcpwgFW9nC0JEV/LKNF/cAkjhPOJUaLh9QMmCGcZo8Sb9l/MIHPZBBQl9nVtZwOxRQSM JY4dXsIMUsQs8JZF4uOaNywgCWGBSolDZ54yQRTVSVzt3cwIsk5EQE/i83kvkDCLgKrEjSNH GEFsXgFLic2LHoLN5xSwknj2ZTYriM0oICbx/dQasDHMAuISt57MZ4L4TVBi0ew9zBC2mMS/ XQ/ZIGx5ick/ZkDZihL3v79kh+jVk7gxdQobhK0tsWzha2aIvYISJ2c+YYGol5Q4uOIGOLwk BKZzSjz9s48VIuEicX33GXYIW1ri6vWpzJCgS5ZY9ZELIpwjMX/JFqg51hIL/6xnmsCoMgvJ 2bOQnDELyRmzkJyxgJFlFaN4aXFxbnpqsWFearlecWJucWleul5yfu4mRmBqO/3vcO4Oxh23 PuodYmTiYDzEKMHBrCTCaxizL0WINyWxsiq1KD++qDQntfgQozQHi5I4r6HtyWQhgfTEktTs 1NSC1CKYLBMHp1QD0wru4rDgB9tcD+841dp0bHrHIR2LpX+i2x4oblNetsPgzlbrpxPXPfu0 Nf5NqFb5LQkP949Mv7yeMTd7Ovy10/tc9DJDbZG+00YPwyWeFx9XZqpcdXRpcuyrmJhw0GYX /zPrl50J6+N2HzjvNUfe+XGeyf9/M1b+iAhX80v+e1R0No/R3/m9du9Wmz9tNTT/s/z4uneH l/+yLJkrHKr7UDzAV2xFbdF95eVbl/w5Gp93ZY+zYuHSX22LN31haf77c8o67fnlNw7e4zgj O2v7pKSdBYeX3HFTOWCslu8ddaSQOaEhW45f5orODJu0tdudDkSqJE7S1f354dHXPbtbTaa0 PdzQxTytWtnNyoRtjbYSS3FGoqEWc1FxIgCLUL5n3AMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0hTYRjG+845Ho8T47Q0Pwu7DCq0Wo0sjiVhLOtYRhcCK0odeZoznWtH S4Ny1BCaWC5b1kRMnRZqWNrFzOu8rLw0s4tmSV62qUh5JRMzcx0C//s97/c87/P98RIo34ot J2TyWEYpl0QJcB4mUyHaTbPLasK3NJQiVLL5MaDSdW2AKvxcBCjV1T6MUr8aQahq6wBGFWR/ wimzvgmjBrQDCJVn6EMpU0oZ5u9Mt6WlOtC5qgD6pb7bkVbXf59XFUMI/WRszpG2fCpF6NLh QZTWZSTSEyUrD/NO8vzCmSjZBUa5eVcYL0LVH6qY8I7/MdKAqcCP1RpAEJD0gUMZHhrAI/hk IYAPk+pwTowDmJTTjHIiH8Cs3EKgAU4ETq6BVZoXuJ1dya2wsc6A2hklhzH4852znZeSCdDY YkU4zxXYUdaI29tcSSGcMO+3jzFyLeysr/+30oX0haU5vajdwp/nZ9oQ+9iJ3AFtkxkOdgbk MjjVVIRwTe6wy5L1jyFJQkOFGeXYDQ71/3HgeBVM+3UX53gN/DY15MhlhbBTdxvneAPMzx5G uS8sgW/uWTDO7wFrH3ZiqQDqF9TpF8T1C+L6BfH7ACsA7nEsGy2NZ0Vy5qKQlUSzcXKp8ExM dAmYv4TmP3UnykBD15jQCBACGAEkUIGri+hUVTjfJVyScIlRxoQq46IY1ghWEJjA3YUfoA3l k1JJLHOOYRSM8v8rQjgtVyFwfaS3ZK5GIZ6LMbUqrIK3vq+vzXpaieKdjY7be9JL8kKCtp35 6h/YU7X1dJLJ9mS38nNN+7EJdWumwuvm8yO5MnG8jRgvPho29qDNz1/aP/p4z9GCtGHPaXxy ClSVewUY2xUGdU/Jtpabi6RZeyvLT91LPGjyyxWd7S4u/3jnwHlxgGJgbZh544dxTXp+h0+K 4Xp1YrvJMGsZGSW8+bKOjmA+LC7MieiTB/amVT71lIQS/Xcd9tmmL8cFqwOdT67LVuuTMw+J E48v1qXagr6II5nf2ket21NnvJpdsd9eg6o8UZNFHfECcXvuo/mY0pV8f6Y89tYoXXuD1c28 F2BshETkjSpZyV/wthbdeAMAAA== X-CMS-MailID: 20230725183957uscas1p28b38d294f90b97f99769466cc533b4de CMS-TYPE: 301P X-CMS-RootMailID: 20230725183957uscas1p28b38d294f90b97f99769466cc533b4de References: <20230725183939.2741025-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.12; envelope-from=fan.ni@samsung.com; helo=mailout2.w2.samsung.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fan Ni Add dynamic capacity extent list representative to the definition of CXLType3Dev and add get DC extent list mailbox command per CXL.spec.3.0:.8.2.9.8.9.2. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 71 +++++++++++++++++++++++++++++++++++++ hw/mem/cxl_type3.c | 1 + include/hw/cxl/cxl_device.h | 23 ++++++++++++ 3 files changed, 95 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 0511b8e6f7..3d25a9697e 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -83,6 +83,7 @@ enum { #define CLEAR_POISON 0x2 DCD_CONFIG = 0x48, /*r3.0: 8.2.9.8.9*/ #define GET_DC_CONFIG 0x0 + #define GET_DYN_CAP_EXT_LIST 0x1 PHYSICAL_SWITCH = 0x51 #define IDENTIFY_SWITCH_DEVICE 0x0 }; @@ -1018,6 +1019,73 @@ static CXLRetCode cmd_dcd_get_dyn_cap_config(struct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } +/* + * cxl spec 3.0: 8.2.9.8.9.2 + * Get Dynamic Capacity Extent List (Opcode 4810h) + */ +static CXLRetCode cmd_dcd_get_dyn_cap_ext_list(struct cxl_cmd *cmd, + CXLDeviceState *cxl_dstate, + uint16_t *len) +{ + struct get_dyn_cap_ext_list_in_pl { + uint32_t extent_cnt; + uint32_t start_extent_id; + } QEMU_PACKED; + + struct get_dyn_cap_ext_list_out_pl { + uint32_t count; + uint32_t total_extents; + uint32_t generation_num; + uint8_t rsvd[4]; + CXLDCExtent_raw records[]; + } QEMU_PACKED; + + struct get_dyn_cap_ext_list_in_pl *in = (void *)cmd->payload; + struct get_dyn_cap_ext_list_out_pl *out = (void *)cmd->payload; + struct CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, + cxl_dstate); + uint16_t record_count = 0, i = 0, record_done = 0; + CXLDCDExtentList *extent_list = &ct3d->dc.extents; + CXLDCD_Extent *ent; + uint16_t out_pl_len; + uint32_t start_extent_id = in->start_extent_id; + + if (start_extent_id > ct3d->dc.total_extent_count) { + return CXL_MBOX_INVALID_INPUT; + } + + record_count = MIN(in->extent_cnt, + ct3d->dc.total_extent_count - start_extent_id); + + out_pl_len = sizeof(*out) + record_count * sizeof(out->records[0]); + /* May need more processing here in the future */ + assert(out_pl_len <= CXL_MAILBOX_MAX_PAYLOAD_SIZE); + + memset(out, 0, out_pl_len); + stl_le_p(&out->count, record_count); + stl_le_p(&out->total_extents, ct3d->dc.total_extent_count); + stl_le_p(&out->generation_num, ct3d->dc.ext_list_gen_seq); + + if (record_count > 0) { + QTAILQ_FOREACH(ent, extent_list, node) { + if (i++ < start_extent_id) { + continue; + } + stq_le_p(&out->records[record_done].start_dpa, ent->start_dpa); + stq_le_p(&out->records[record_done].len, ent->len); + memcpy(&out->records[record_done].tag, ent->tag, 0x10); + stw_le_p(&out->records[record_done].shared_seq, ent->shared_seq); + record_done++; + if (record_done == record_count) { + break; + } + } + } + + *len = out_pl_len; + return CXL_MBOX_SUCCESS; +} + #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_DATA_CHANGE (1 << 2) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -1058,6 +1126,9 @@ static struct cxl_cmd cxl_cmd_set[256][256] = { cmd_media_clear_poison, 72, 0 }, [DCD_CONFIG][GET_DC_CONFIG] = { "DCD_GET_DC_CONFIG", cmd_dcd_get_dyn_cap_config, 2, 0 }, + [DCD_CONFIG][GET_DYN_CAP_EXT_LIST] = { + "DCD_GET_DYNAMIC_CAPACITY_EXTENT_LIST", cmd_dcd_get_dyn_cap_ext_list, + 8, 0 }, }; static struct cxl_cmd cxl_cmd_set_sw[256][256] = { diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 76bbd9f785..f1170b8047 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -789,6 +789,7 @@ static int cxl_create_dc_regions(CXLType3Dev *ct3d) region_base += region->len; } + QTAILQ_INIT(&ct3d->dc.extents); return 0; } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 1c99b05a66..3a338b3b37 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -385,6 +385,25 @@ typedef QLIST_HEAD(, CXLPoison) CXLPoisonList; #define DCD_MAX_REGION_NUM 8 +typedef struct CXLDCD_Extent_raw { + uint64_t start_dpa; + uint64_t len; + uint8_t tag[0x10]; + uint16_t shared_seq; + uint8_t rsvd[0x6]; +} QEMU_PACKED CXLDCExtent_raw; + +typedef struct CXLDCD_Extent { + uint64_t start_dpa; + uint64_t len; + uint8_t tag[0x10]; + uint16_t shared_seq; + uint8_t rsvd[0x6]; + + QTAILQ_ENTRY(CXLDCD_Extent) node; +} CXLDCD_Extent; +typedef QTAILQ_HEAD(, CXLDCD_Extent) CXLDCDExtentList; + typedef struct CXLDCD_Region { uint64_t base; uint64_t decode_len; /* in multiples of 256MB */ @@ -433,6 +452,10 @@ struct CXLType3Dev { uint8_t num_regions; /* 0-8 regions */ struct CXLDCD_Region regions[DCD_MAX_REGION_NUM]; + CXLDCDExtentList extents; + + uint32_t total_extent_count; + uint32_t ext_list_gen_seq; } dc; }; From patchwork Tue Jul 25 18:39:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 1812815 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 header.s=mail20170921 header.b=bKmNuMJA; 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Tue, 25 Jul 2023 18:39:57 +0000 (GMT) X-AuditID: cbfec370-b17ff7000001f31d-95-64c016fd5f19 Received: from SSI-EX2.ssi.samsung.com ( [105.128.2.145]) by ussmgxs1new.samsung.com (USCPEXMTA) with SMTP id 74.54.38326.DF610C46; Tue, 25 Jul 2023 14:39:57 -0400 (EDT) Received: from SSI-EX2.ssi.samsung.com (105.128.2.227) by SSI-EX2.ssi.samsung.com (105.128.2.227) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2375.24; Tue, 25 Jul 2023 11:39:56 -0700 Received: from SSI-EX2.ssi.samsung.com ([105.128.2.227]) by SSI-EX2.ssi.samsung.com ([105.128.2.227]) with mapi id 15.01.2375.024; Tue, 25 Jul 2023 11:39:56 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [Qemu PATCH v2 7/9] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response Thread-Topic: [Qemu PATCH v2 7/9] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response Thread-Index: AQHZvydoEWnb5qMfxEi9SRoRqte0zA== Date: Tue, 25 Jul 2023 18:39:56 +0000 Message-ID: <20230725183939.2741025-8-fan.ni@samsung.com> In-Reply-To: <20230725183939.2741025-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNKsWRmVeSWpSXmKPExsWy7djXc7p/xQ6kGEydoWfRfX4Do8X0qRcY LVbfXMNo0dD0iMWiZfd7Jov9T5+zWKxaeI3N4vysUywWzyc+Z7JYuuQRs8Xx3h0sDtweFyZP YPVY3ODqsXPWXXaPliNvgbw9L5k8Nn78z+7x5NpmJo/Nr18we0ydXe/xeZNcAFcUl01Kak5m WWqRvl0CV8behS2MBQsCK27uqG9g3GrZxcjJISFgIjFp2jmWLkYuDiGBlYwSl29OZYVwWpkk Hs7oZIOp6plylREisRaoqvE9VNUnRomG1w+YIJxljBJv2n8xg7SwCShK7OvaDtYuImAscezw EmaQImaBtywSH9e8YQFJCAvUSfy7+w8sISLQzCgxa+EiVogOPYlrG9+wg9gsAqoSN44cAVrO wcErYClxfI8VSJhTwEri2ZfZYOWMAmIS30+tYQKxmQXEJW49mc8EcbegxKLZe5ghbDGJf7se Qv0jLzH5xwwoW1Hi/veX7BC9ehI3pk5hg7C1JZYtfA3Wyws05+TMJywQ9ZISB1fcAIeYhMBk TontTz+xQiRcJO7e+QlVJC1x9fpUZpCbJQSSJVZ95III50jMX7IFqsRaYuGf9UwTGFVmITl7 FpIzZiE5YxaSMxYwsqxiFC8tLs5NTy02zkst1ytOzC0uzUvXS87P3cQITG+n/x0u2MF469ZH vUOMTByMhxglOJiVRHgNY/alCPGmJFZWpRblxxeV5qQWH2KU5mBREuc1tD2ZLCSQnliSmp2a WpBaBJNl4uCUamCSX/3E3iJkyukn/srJGVJc0erm2158mxCxyWJ/64QQr/um0W4tMitClj8R r4hS3eN0+MSrgN1H7zDNULPdo1WcO7uZ5d19IdGU20ueTj+i98F9LfuCP7+u6zD+3xYrNaVi 4V6ztW2JS6/4v9nWlD/v23wvg7XrIx0t+D7fcjtvf8SS9/ty52DPaxWZT79P9V5knnpV54bC Nt715nPyao8o/TgmJ2564NnLaSuX2psxpNyR0zi25tTd56L3dnEEftn30fqiXuav/Zkq3KcN RFkLX7fMDWGxPJ16vTmn1DHuMsPLxztu6rs8WpxX8rhFPuLdKpcMvvn7j+tcfJ4uv/NHgVE8 U96bavGETu23E/yPKrEUZyQaajEXFScCABc2v7TeAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOIsWRmVeSWpSXmKPExsWS2cA0Ufev2IEUg6YzEhbd5zcwWkyfeoHR YvXNNYwWDU2PWCxadr9nstj/9DmLxaqF19gszs86xWLxfOJzJoulSx4xWxzv3cHiwO1xYfIE Vo/FDa4eO2fdZfdoOfIWyNvzkslj48f/7B5Prm1m8tj8+gWzx9TZ9R6fN8kFcEVx2aSk5mSW pRbp2yVwZexd2MJYsCCw4uaO+gbGrZZdjJwcEgImEj1TrjJ2MXJxCAmsZpRoPrydBcL5xCjR tug0M4SzjFFi/uLVjCAtbAKKEvu6trOB2CICxhLHDi9hBrGZBV6zSHy7yA1iCwvUSRx+O50N pFlEoJlR4vLck0wQDXoS1za+YQexWQRUJW4cOQI0lIODV8BS4vgeKxBTCMjcOjEOpIJTwEri 2ZfZrCA2o4CYxPdTa5ggVolL3HoynwniAwGJJXvOM0PYohIvH/9jhbDlJSb/mMEGYStK3P/+ kh2iV0/ixtQpbBC2tsSyha/BenkFBCVOznzCAlEvKXFwxQ2WCYwSs5Csm4WkfRaS9llI2hcw sqxiFC8tLs5Nryg2zEst1ytOzC0uzUvXS87P3cQITAun/x2O3MF49NZHvUOMTByMhxglOJiV RHgNY/alCPGmJFZWpRblxxeV5qQWH2KU5mBREucVcp0YLySQnliSmp2aWpBaBJNl4uCUamDS eLqKuUw053qmxkNhm7R/zVUqXtt2ztxyNZh1h03ehgLLxeFbRc6pVPXOzxLw1LwqdmHi/q+d Rlcli5n9r26pfWaUvYDf+FPjqvR/zq//KxlHnPPeZfs4U+rC5ru68gKnZlmsb/0ml/j/ynyf mDWzbAtjO468SVpZf3u30i3LdisXNsU4nkVKPXuPFHU9yWCZ8cav1yB5mZWEdq5EieDavvgn LVvzHs0OlTtcJCz3Vf7AbsGrLfOlLjAzLQ8r3Fhqbl5g3RhjW3Np7WQ1kwzPoNinZouFHA84 WNX98W82qz3VuszRuFW6cu3F+7xHIqpjAxMn/FtZVpH9zvCgtfOqrTpzzKuv9gj+Y4ubrMRS nJFoqMVcVJwIAA+iSr96AwAA X-CMS-MailID: 20230725183957uscas1p2a076b6f7b694d2e632a0b8025ec331d7 CMS-TYPE: 301P X-CMS-RootMailID: 20230725183957uscas1p2a076b6f7b694d2e632a0b8025ec331d7 References: <20230725183939.2741025-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.11; envelope-from=fan.ni@samsung.com; helo=mailout1.w2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fan Ni Per CXL spec 3.0, two mailbox commands are implemented: Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and Release Dynamic Capacity (Opcode 4803h) 8.2.9.8.9.4. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 253 ++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 3 +- 2 files changed, 255 insertions(+), 1 deletion(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 3d25a9697e..1e4944da95 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -84,6 +84,8 @@ enum { DCD_CONFIG = 0x48, /*r3.0: 8.2.9.8.9*/ #define GET_DC_CONFIG 0x0 #define GET_DYN_CAP_EXT_LIST 0x1 + #define ADD_DYN_CAP_RSP 0x2 + #define RELEASE_DYN_CAP 0x3 PHYSICAL_SWITCH = 0x51 #define IDENTIFY_SWITCH_DEVICE 0x0 }; @@ -1086,6 +1088,251 @@ static CXLRetCode cmd_dcd_get_dyn_cap_ext_list(struct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } +/* + * Check whether the bits at addr between [nr, nr+size) are all set, + * return 1 if all 1s, else return 0 + */ +static inline int test_bits(const unsigned long *addr, int nr, int size) +{ + unsigned long res = find_next_zero_bit(addr, size + nr, nr); + + return (res >= nr + size) ? 1 : 0; +} + +/* + * Find dynamic capacity region id based on dpa range [dpa, dpa+len) + */ +static uint8_t find_region_id(struct CXLType3Dev *dev, uint64_t dpa, + uint64_t len) +{ + int8_t i = dev->dc.num_regions - 1; + + while (i > 0 && dpa < dev->dc.regions[i].base) { + i--; + } + + if (dpa < dev->dc.regions[i].base + || dpa + len > dev->dc.regions[i].base + dev->dc.regions[i].len) { + return dev->dc.num_regions; + } + + return i; +} + +static void insert_extent_to_extent_list(CXLDCDExtentList *list, uint64_t dpa, + uint64_t len, uint8_t *tag, uint16_t shared_seq) +{ + CXLDCD_Extent *extent; + extent = g_new0(CXLDCD_Extent, 1); + extent->start_dpa = dpa; + extent->len = len; + if (tag) { + memcpy(extent->tag, tag, 0x10); + } else { + memset(extent->tag, 0, 0x10); + } + extent->shared_seq = shared_seq; + + QTAILQ_INSERT_TAIL(list, extent, node); +} + +typedef struct updated_dc_extent_list_in_pl { + uint32_t num_entries_updated; + uint8_t rsvd[4]; + struct { /* r3.0: Table 8-130 */ + uint64_t start_dpa; + uint64_t len; + uint8_t rsvd[8]; + } QEMU_PACKED updated_entries[]; +} QEMU_PACKED updated_dc_extent_list_in_pl; + +/* + * The function only check the input extent list against itself. + */ +static CXLRetCode detect_malformed_extent_list(CXLType3Dev *dev, + const updated_dc_extent_list_in_pl *in) +{ + unsigned long *blk_bitmap; + uint64_t min_block_size = dev->dc.regions[0].block_size; + struct CXLDCD_Region *region = &dev->dc.regions[0]; + uint32_t i; + uint64_t dpa, len; + uint8_t rid; + CXLRetCode ret; + + for (i = 1; i < dev->dc.num_regions; i++) { + region = &dev->dc.regions[i]; + if (min_block_size > region->block_size) { + min_block_size = region->block_size; + } + } + + blk_bitmap = bitmap_new((region->len + region->base + - dev->dc.regions[0].base) / min_block_size); + + for (i = 0; i < in->num_entries_updated; i++) { + dpa = in->updated_entries[i].start_dpa; + len = in->updated_entries[i].len; + + rid = find_region_id(dev, dpa, len); + if (rid == dev->dc.num_regions) { + ret = CXL_MBOX_INVALID_PA; + goto out; + } + + region = &dev->dc.regions[rid]; + if (dpa % region->block_size || len % region->block_size) { + ret = CXL_MBOX_INVALID_EXTENT_LIST; + goto out; + } + /* the dpa range already covered by some other extents in the list */ + if (test_bits(blk_bitmap, dpa / min_block_size, len / min_block_size)) { + ret = CXL_MBOX_INVALID_EXTENT_LIST; + goto out; + } + bitmap_set(blk_bitmap, dpa / min_block_size, len / min_block_size); + } + + ret = CXL_MBOX_SUCCESS; + +out: + g_free(blk_bitmap); + return ret; +} + +/* + * cxl spec 3.0: 8.2.9.8.9.3 + * Add Dynamic Capacity Response (opcode 4802h) + * Assume an extent is added only after the response is processed successfully + * TODO: for better extent list validation, a better solution would be + * maintaining a pending extent list and use it to verify the extent list in + * the response. + */ +static CXLRetCode cmd_dcd_add_dyn_cap_rsp(struct cxl_cmd *cmd, + CXLDeviceState *cxl_dstate, uint16_t *len_unused) +{ + updated_dc_extent_list_in_pl *in = (void *)cmd->payload; + struct CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, + cxl_dstate); + CXLDCDExtentList *extent_list = &ct3d->dc.extents; + CXLDCD_Extent *ent; + uint32_t i; + uint64_t dpa, len; + CXLRetCode ret; + + if (in->num_entries_updated == 0) { + ret = CXL_MBOX_SUCCESS; + goto out; + } + + ret = detect_malformed_extent_list(ct3d, in); + if (ret != CXL_MBOX_SUCCESS) { + goto out; + } + + for (i = 0; i < in->num_entries_updated; i++) { + dpa = in->updated_entries[i].start_dpa; + len = in->updated_entries[i].len; + + /* + * Check if the DPA range of the to-be-added extent overlaps with + * existing extent list maintained by the device. + */ + QTAILQ_FOREACH(ent, extent_list, node) { + if (ent->start_dpa == dpa && ent->len == len) { + ret = CXL_MBOX_INVALID_PA; + goto out; + } else if (ent->start_dpa <= dpa + && dpa + len <= ent->start_dpa + ent->len) { + ret = CXL_MBOX_INVALID_PA; + goto out; + } else if ((dpa < ent->start_dpa + ent->len + && dpa + len > ent->start_dpa + ent->len) + || (dpa < ent->start_dpa && dpa + len > ent->start_dpa)) { + ret = CXL_MBOX_INVALID_PA; + goto out; + } + } + + /* + * TODO: add a pending extent list based on event log record and verify + * the input response + */ + + insert_extent_to_extent_list(extent_list, dpa, len, NULL, 0); + } + ret = CXL_MBOX_SUCCESS; + +out: + return ret; +} + +/* + * Spec 3.0: 8.2.9.8.9.4 + * Release Dynamic Capacity (opcode 4803h) + **/ +static CXLRetCode cmd_dcd_release_dyn_cap(struct cxl_cmd *cmd, + CXLDeviceState *cxl_dstate, + uint16_t *len_unused) +{ + updated_dc_extent_list_in_pl *in = (void *)cmd->payload; + struct CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, + cxl_dstate); + CXLDCDExtentList *extent_list = &ct3d->dc.extents; + CXLDCD_Extent *ent; + uint32_t i; + uint64_t dpa, len; + CXLRetCode ret; + + if (in->num_entries_updated == 0) { + return CXL_MBOX_INVALID_INPUT; + } + + ret = detect_malformed_extent_list(ct3d, in); + if (ret != CXL_MBOX_SUCCESS) { + return ret; + } + + for (i = 0; i < in->num_entries_updated; i++) { + dpa = in->updated_entries[i].start_dpa; + len = in->updated_entries[i].len; + + QTAILQ_FOREACH(ent, extent_list, node) { + if (ent->start_dpa == dpa && ent->len == len) { + break; + } else if (ent->start_dpa < dpa + && dpa + len <= ent->start_dpa + ent->len) { + /* remove partial extent */ + uint64_t len1 = dpa - ent->start_dpa; + uint64_t len2 = ent->start_dpa + ent->len - dpa - len; + + if (len1) { + insert_extent_to_extent_list(extent_list, ent->start_dpa, + len1, NULL, 0); + } + if (len2) { + insert_extent_to_extent_list(extent_list, dpa + len, len2, + NULL, 0); + } + break; + } else if ((dpa < ent->start_dpa + ent->len + && dpa + len > ent->start_dpa + ent->len) + || (dpa < ent->start_dpa && dpa + len > ent->start_dpa)) + return CXL_MBOX_INVALID_EXTENT_LIST; + } + + if (ent) { + QTAILQ_REMOVE(extent_list, ent, node); + g_free(ent); + } else { + /* Try to remove a non-existing extent */ + return CXL_MBOX_INVALID_PA; + } + } + + return CXL_MBOX_SUCCESS; +} + #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_DATA_CHANGE (1 << 2) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -1129,6 +1376,12 @@ static struct cxl_cmd cxl_cmd_set[256][256] = { [DCD_CONFIG][GET_DYN_CAP_EXT_LIST] = { "DCD_GET_DYNAMIC_CAPACITY_EXTENT_LIST", cmd_dcd_get_dyn_cap_ext_list, 8, 0 }, + [DCD_CONFIG][ADD_DYN_CAP_RSP] = { + "ADD_DCD_DYNAMIC_CAPACITY_RESPONSE", cmd_dcd_add_dyn_cap_rsp, + ~0, IMMEDIATE_DATA_CHANGE }, + [DCD_CONFIG][RELEASE_DYN_CAP] = { + "RELEASE_DCD_DYNAMIC_CAPACITY", cmd_dcd_release_dyn_cap, + ~0, IMMEDIATE_DATA_CHANGE }, }; static struct cxl_cmd cxl_cmd_set_sw[256][256] = { diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 3a338b3b37..01a5eaca48 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -130,7 +130,8 @@ typedef enum { CXL_MBOX_INCORRECT_PASSPHRASE = 0x14, CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15, CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16, - CXL_MBOX_MAX = 0x17 + CXL_MBOX_INVALID_EXTENT_LIST = 0x1E, /* cxl r3.0: Table 8-34*/ + CXL_MBOX_MAX = 0x1F } CXLRetCode; struct cxl_cmd; From patchwork Tue Jul 25 18:39:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 1812817 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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Tue, 25 Jul 2023 11:39:56 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [Qemu PATCH v2 8/9] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents Thread-Topic: [Qemu PATCH v2 8/9] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents Thread-Index: AQHZvydoteAcJguFu0q3LwS06vqHoA== Date: Tue, 25 Jul 2023 18:39:56 +0000 Message-ID: <20230725183939.2741025-9-fan.ni@samsung.com> In-Reply-To: <20230725183939.2741025-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrDKsWRmVeSWpSXmKPExsWy7djX87r/xA6kGNzaw2HRfX4Do8X0qRcY LVbfXMNo0dD0iMWiZfd7Jov9T5+zWKxaeI3N4vysUywWzyc+Z7JYuuQRs8Xx3h0sDtweFyZP YPVY3ODqsXPWXXaPliNvgbw9L5k8Nn78z+7x5NpmJo/Nr18we0ydXe/xeZNcAFcUl01Kak5m WWqRvl0CV8bbxjlMBU0eFZfOvWRpYHxp2sXIySEhYCJx6+Aaxi5GLg4hgZWMEj8bjjFDOK1M Ev/eLGeHqzq1E6pqLaPEyveX2CCcT4wS95a+hHKWMUq8af/FDNLCJqAosa9rOxuILSJgLHHs 8BKwucwCb1kkPq55wwKSEBbIkDg16xMLRFGuxMr99xkhbD2J/gtLmEBsFgFViRtHjoDFeQUs JQ7O/swKYnMKWEk8+zIbzGYUEJP4fmoNWD2zgLjErSfzmSDuFpRYNHsPM4QtJvFv10M2CFte YvKPGVC2osT97y/ZIXr1JG5MncIGYWtLLFv4mhlir6DEyZlPWCDqJSUOrrjBAvKMhMBkTomu D5ehlrlIfJrzDKpIWuLq9alAzRxAdrLEqo9cEOEciflLtkCVWEss/LOeaQKjyiwkZ89CcsYs JGfMQnLGAkaWVYzipcXFuempxUZ5qeV6xYm5xaV56XrJ+bmbGIEJ7vS/w/k7GK/f+qh3iJGJ g/EQowQHs5IIr2HMvhQh3pTEyqrUovz4otKc1OJDjNIcLErivIa2J5OFBNITS1KzU1MLUotg skwcnFINTI2SG+p2nrv9aXJy07Z6E32j6Wv5S6/0CZxlejk9JvafVgDbqn/nPi5oLdyw0+GT hdDrhTvSoxVORMTFKOlXrr0deLvLa+rVAs43vbsSsuMF566MWHJlLn/Qi9uKh3799s5wrCjJ PcBYMGPRM+aA569vCMxnfcgnN2dH9oE6W3fPVw5zFRPZs6XbP/vNu/+W9XgDk6ic5GfJP5xc K08pvn/02PD//OALWmuW6FxNl9ureLY6LGL6211OnQxz72xYflx1T1+O/Nd9ztdDpMKW//oQ 3yVjb7q/ztTIb23P50avlmeX+ZaGmpSLCD5z8lw7/ZuxiU70h4m7X6d9OPvkW0ab4/d1ndwt FRcfbLS5YajEUpyRaKjFXFScCACL3ZRu3wMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA02Sf0gTYRjHee9u2zkbXMv01ULTstBotiw6V1SUxlX/jCDKsmy1wy23ZTst S6glq0Cz3FTSWz9xpalEaVmSVOqy1GibyJhDK5Y1x4ooy/WDrK0j8L/P93m+3/d5HnhxVOzD 4nC1rpDW6xSaJL4QUxsQ05Lf0U+US++a0shy+21AXqhxALJ5uAWQhlIvRhoffkLIx+98GNl0 zcUn7Ww/RvpMPoS8bvWi5LOKB9i6SMpRVcmj6g1ZVAc7KqCMto8h1elHqDuf/wioMVcbQrUF xlGqxnKCmmiNlwt3ClcraY36MK1PW7NXqPp48iJSUEoVD770YwbgX1EGInBILIee/g5QBoS4 mGgG0D5qRDjxBcA+6ycBJ24AeKW+GYQjfCIRPiq7zw9zFJEOe3usaJhRIoDBSWdkmGcRKhio bgrV8ZBHCxt75ZxdAs87rEiYMSIZum22f0+KiAzYZZnghe3iEN8z7QmXIwgZfP/VwgszIKJh sL8F4SbFQM/YFYQ7gIDWTjvK8WzofzvF4zgBVn2v5XOcCF8H/QIuK4Hummo+x4vhjWsBlFth JuyrG8M4fyzsanRjlQCy08ax0+LstDg7LX4VYE0gpohhtHnFjFRHH5EwCi1TpMuT7D+obQWh vzAw1ZP9ADz1fJZ0AwQH3QDiaFKUSJrzSCkWKRVHj9H6g7n6Ig3NdIM5OJYUIxJnmXLFRJ6i kM6n6QJa/7+L4BFxBqR8pHzr5Rf+b9K8eT9Hbjr7XzWIfiwcv7R6frbl1njdyj+42yqjzHxT aoW48tAydIXcdrwhRebadDM5Mz2dYBuPREm63p7+1TmYWMfOT840Lw6smTn0zGXR9KROVp0o N3qlwoSJA6c3xFtaneeYd7t6sWKHswRkD9h41wMt7rQU+Y7j+84Y5wTb1fkF8rNTNbe2bR/b uHn9h82ZZscHMzA/yUXa9BVbGmqDA+3VmqgO8pXdiZ0zSLLMZV3m3dHKRWlvVgli8zPavHOD rZdK1m4smWVeamv3LCkYqWf75hl86ycWeJc3xsq0z+sT+NF1qpOnZoiGzgzvSFR5InMkSRij UkhTUT2j+AviSwS6egMAAA== X-CMS-MailID: 20230725183957uscas1p1ebf676c30d21896d1fd7f9b652250449 CMS-TYPE: 301P X-CMS-RootMailID: 20230725183957uscas1p1ebf676c30d21896d1fd7f9b652250449 References: <20230725183939.2741025-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.11; envelope-from=fan.ni@samsung.com; helo=mailout1.w2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fan Ni Since fabric manager emulation is not supported yet, the change implements the functions to add/release dynamic capacity extents as QMP interfaces. 1. Add dynamic capacity extents: For example, the command to add two continuous extents (each is 128MB long) to region 0 (starting at dpa offset 0 and 128MB) looks like below: { "execute": "qmp_capabilities" } { "execute": "cxl-add-dynamic-capacity-event", "arguments": { "path": "/machine/peripheral/cxl-dcd0", "extents": [ { "region-id": 0, "dpa": 0, "len": 128 }, { "region-id": 0, "dpa": 128, "len": 128 } ] } } 2. Release dynamic capacity extents: For example, the command to release an extent of size 128MB from region 0 (starting at dpa offset 128MB) look like below: { "execute": "cxl-release-dynamic-capacity-event", "arguments": { "path": "/machine/peripheral/cxl-dcd0", "extents": [ { "region-id": 0, "dpa": 128, "len": 128 } ] } } Signed-off-by: Fan Ni --- hw/mem/cxl_type3.c | 145 ++++++++++++++++++++++++++++++++++++ hw/mem/cxl_type3_stubs.c | 6 ++ include/hw/cxl/cxl_events.h | 16 ++++ qapi/cxl.json | 49 ++++++++++++ 4 files changed, 216 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index f1170b8047..41a828598a 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1817,6 +1817,151 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log, } } +static const QemuUUID dynamic_capacity_uuid = { + .data = UUID(0xca95afa7, 0xf183, 0x4018, 0x8c, 0x2f, + 0x95, 0x26, 0x8e, 0x10, 0x1a, 0x2a), +}; + +/* + * cxl r3.0: Table 8-47 + * 00h: add capacity + * 01h: release capacity + * 02h: forced capacity release + * 03h: region configuration updated + * 04h: Add capacity response + * 05h: capacity released + */ +enum DC_Event_Type { + DC_EVENT_ADD_CAPACITY, + DC_EVENT_RELEASE_CAPACITY, + DC_EVENT_FORCED_RELEASE_CAPACITY, + DC_EVENT_REGION_CONFIG_UPDATED, + DC_EVENT_ADD_CAPACITY_RSP, + DC_EVENT_CAPACITY_RELEASED, + DC_EVENT_NUM +}; + +#define MEM_BLK_SIZE_MB 128 +static void qmp_cxl_process_dynamic_capacity_event(const char *path, + CxlEventLog log, enum DC_Event_Type type, + uint16_t hid, CXLDCExtentRecordList *records, Error **errp) +{ + Object *obj = object_resolve_path(path, NULL); + CXLEventDynamicCapacity dCap; + CXLEventRecordHdr *hdr = &dCap.hdr; + CXLDeviceState *cxlds; + CXLType3Dev *dcd; + uint8_t flags = 1 << CXL_EVENT_TYPE_INFO; + uint32_t num_extents = 0; + CXLDCExtentRecordList *list = records; + CXLDCExtent_raw *extents; + uint64_t dpa, len; + uint8_t rid = 0; + int i; + + if (!obj) { + error_setg(errp, "Unable to resolve path"); + return; + } + if (!object_dynamic_cast(obj, TYPE_CXL_TYPE3)) { + error_setg(errp, "Path not point to a valid CXL type3 device"); + return; + } + + dcd = CXL_TYPE3(obj); + cxlds = &dcd->cxl_dstate; + memset(&dCap, 0, sizeof(dCap)); + + if (!dcd->dc.num_regions) { + error_setg(errp, "No dynamic capacity support from the device"); + return; + } + + while (list) { + dpa = list->value->dpa * 1024 * 1024; + len = list->value->len * 1024 * 1024; + rid = list->value->region_id; + + if (rid >= dcd->dc.num_regions) { + error_setg(errp, "region id is too large"); + return; + } + + if (dpa % dcd->dc.regions[rid].block_size + || len % dcd->dc.regions[rid].block_size) { + error_setg(errp, "dpa or len is not aligned to region block size"); + return; + } + + if (dpa + len > dcd->dc.regions[rid].decode_len * 256 * 1024 * 1024) { + error_setg(errp, "extent range is beyond the region end"); + return; + } + + num_extents++; + list = list->next; + } + + i = 0; + list = records; + extents = g_new0(CXLDCExtent_raw, num_extents); + while (list) { + dpa = list->value->dpa * 1024 * 1024; + len = list->value->len * 1024 * 1024; + rid = list->value->region_id; + + extents[i].start_dpa = dpa + dcd->dc.regions[rid].base; + extents[i].len = len; + memset(extents[i].tag, 0, 0x10); + extents[i].shared_seq = 0; + + list = list->next; + i++; + } + + /* + * 8.2.9.1.5 + * All Dynamic Capacity event records shall set the Event Record + * Severity field in the Common Event Record Format to Informational + * Event. All Dynamic Capacity related events shall be logged in the + * Dynamic Capacity Event Log. + */ + cxl_assign_event_header(hdr, &dynamic_capacity_uuid, flags, sizeof(dCap), + cxl_device_get_timestamp(&dcd->cxl_dstate)); + + dCap.type = type; + stw_le_p(&dCap.host_id, hid); + /* only valid for DC_REGION_CONFIG_UPDATED event */ + dCap.updated_region_id = rid; + for (i = 0; i < num_extents; i++) { + memcpy(&dCap.dynamic_capacity_extent, &extents[i] + , sizeof(CXLDCExtent_raw)); + + if (cxl_event_insert(cxlds, CXL_EVENT_TYPE_DYNAMIC_CAP, + (CXLEventRecordRaw *)&dCap)) { + cxl_event_irq_assert(dcd); + } + } + + g_free(extents); +} + +void qmp_cxl_add_dynamic_capacity_event(const char *path, + struct CXLDCExtentRecordList *records, + Error **errp) +{ + qmp_cxl_process_dynamic_capacity_event(path, CXL_EVENT_LOG_INFORMATIONAL, + DC_EVENT_ADD_CAPACITY, 0, records, errp); +} + +void qmp_cxl_release_dynamic_capacity_event(const char *path, + struct CXLDCExtentRecordList *records, + Error **errp) +{ + qmp_cxl_process_dynamic_capacity_event(path, CXL_EVENT_LOG_INFORMATIONAL, + DC_EVENT_RELEASE_CAPACITY, 0, records, errp); +} + static void ct3_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c index f3e4a9fa72..482229f3bd 100644 --- a/hw/mem/cxl_type3_stubs.c +++ b/hw/mem/cxl_type3_stubs.c @@ -56,3 +56,9 @@ void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type, { error_setg(errp, "CXL Type 3 support is not compiled in"); } + +void qmp_cxl_add_dynamic_capacity_event(const char *path, + struct CXLDCExtentRecordList *records, Error **errp) {} + +void qmp_cxl_release_dynamic_capacity_event(const char *path, + struct CXLDCExtentRecordList *records, Error **errp) {} diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h index 089ba2091f..3baf745f8d 100644 --- a/include/hw/cxl/cxl_events.h +++ b/include/hw/cxl/cxl_events.h @@ -165,4 +165,20 @@ typedef struct CXLEventMemoryModule { uint8_t reserved[0x3d]; } QEMU_PACKED CXLEventMemoryModule; +/* + * Dynamic Capacity Event Record + * CXL Rev 3.0 Section 8.2.9.2.1.5: Table 8-47 + * All fields little endian. + */ +typedef struct CXLEventDynamicCapacity { + CXLEventRecordHdr hdr; + uint8_t type; + uint8_t reserved1; + uint16_t host_id; + uint8_t updated_region_id; + uint8_t reserved2[3]; + uint8_t dynamic_capacity_extent[0x28]; /* defined in cxl_device.h */ + uint8_t reserved[0x20]; +} QEMU_PACKED CXLEventDynamicCapacity; + #endif /* CXL_EVENTS_H */ diff --git a/qapi/cxl.json b/qapi/cxl.json index 05c560cfe5..fb04ec4c41 100644 --- a/qapi/cxl.json +++ b/qapi/cxl.json @@ -369,3 +369,52 @@ ## {'command': 'cxl-inject-correctable-error', 'data': {'path': 'str', 'type': 'CxlCorErrorType'}} + +## +# @CXLDCExtentRecord: +# +# Record of a single extent to add/release +# +# @region-id: id of the region where the extent to add/release +# @dpa: start dpa (in MiB) of the extent, related to region base address +# @len: extent size (in MiB) +# +# Since: 8.0 +## +{ 'struct': 'CXLDCExtentRecord', + 'data': { + 'region-id': 'uint8', + 'dpa':'uint64', + 'len': 'uint64' + } +} + +## +# @cxl-add-dynamic-capacity-event: +# +# Command to add dynamic capacity extent event +# +# @path: CXL DCD canonical QOM path +# @extents: Extents to add +# +## +{ 'command': 'cxl-add-dynamic-capacity-event', + 'data': { 'path': 'str', + 'extents': [ 'CXLDCExtentRecord' ] + } +} + +## +# @cxl-release-dynamic-capacity-event: +# +# Command to release dynamic capacity extent event +# +# @path: CXL DCD canonical QOM path +# @extents: Extents to release +# +## +{ 'command': 'cxl-release-dynamic-capacity-event', + 'data': { 'path': 'str', + 'extents': [ 'CXLDCExtentRecord' ] + } +} From patchwork Tue Jul 25 18:39:56 2023 Content-Type: text/plain; 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Tue, 25 Jul 2023 14:39:57 -0400 (EDT) Received: from SSI-EX2.ssi.samsung.com (105.128.2.227) by SSI-EX3.ssi.samsung.com (105.128.2.228) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2375.24; Tue, 25 Jul 2023 11:39:56 -0700 Received: from SSI-EX2.ssi.samsung.com ([105.128.2.227]) by SSI-EX2.ssi.samsung.com ([105.128.2.227]) with mapi id 15.01.2375.024; Tue, 25 Jul 2023 11:39:56 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [Qemu PATCH v2 9/9] hw/mem/cxl_type3: Add dpa range validation for accesses to dc regions Thread-Topic: [Qemu PATCH v2 9/9] hw/mem/cxl_type3: Add dpa range validation for accesses to dc regions Thread-Index: AQHZvydoZ/a421rE4EydfsE7dZC6xQ== Date: Tue, 25 Jul 2023 18:39:56 +0000 Message-ID: <20230725183939.2741025-10-fan.ni@samsung.com> In-Reply-To: <20230725183939.2741025-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA01SfVCLcRz3e55n27Nl7jHUT3k5qePEKOG5ZHXo7kGHc905ImZ7rFjFnhI5 TJpeKKpFbZSojuSGXIlUJjH+mM5dKrlOV021Ysh7Y9uTu/77fD8v39/ne/fDUZGJ44nHxCXQ qjip0psrwKqbR8yLRt0b5Uu0mmDyjPk2IC/mvwLkzfZKQKpTujEy9eFHhGzotWBkRUkrlzTr XmCkJceCkGWl3Sj5LOs+FupGvco7z6GuqcOoWt07HpXaNOSY6voR6o7tL4/qaa1CqKrBDyiV rz9Bfbk7a7NguyBYTitjDtGqxZLdgujczj7sgDn4cOHXNJ4aZCzMBHwcEoGwtyCfmwkEuIi4 AaA9tx+wgwaBP+3p3P+ugbdtY8ItAAc6P3Kcgoj4DKC1cx0rlDtw2i/UKXCJObA+s8aVnkos hc1PSlGnCSWGMGirtGJOYQohh9aUGow1xUBz6zMOi8Ww7luLi8cIX9jW1OR4GseFRBBsORvk pPkO2PdV77IDwh1+f1GJODFKeMCOnmKEbT0ZXtXXoSx2h/YH78eumQ3zfhSM4Tmw63s/j82K YVu+lstiP1heMujKCh17TIU9GOufDh9fb8Oct0Aijw/tKXZXN0isha8frWE9XvBi5WuMpWWw wiZgaSUsLr03tmYlLPljQM4DH9241rpxLXTjWujGtbgCsArgkcgwsQqaCYijk8SMNJZJjFOI ZfGxd4Hjt720P4m/D9502MRGgODACCCOek8V+u+ol4uEcumRZFoVv0uVqKQZI/DCMW8Pof8q k0xEKKQJ9H6aPkCr/qsIzvdUI8UjBh+9p/6ob+2oum9GHlN77eSjnIUjiqRcpdfp5aNb02ol UacsO7fI+VvClTn1WXONkiVFwzMV27TP0yfRy7IjTdpsrvXP24KG6nKFR+SKkCRNBJ087e/t li7PCWU5Bl/AZGQEDUfdLNq46GfawbpJjNZvaHi3IYbX8JSfuj7CPi/qEh4YGWopS86aGN0p O1e0fk82x0sSOn9f1V7gVhPqk04eEouPbAo0HXsc5aduHAgbVAZ+urXsXEhA44+EisZuk4w2 ruLuiDi+QGMPkYV8SKxarW+/7N9uVWokmVeOb7AF/A5w64jt6qm+oOptDiP6Mh4eM8zVisJX /xaD694YEy31X4CqGOk/gPhra9wDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOIsWRmVeSWpSXmKPExsWS2cA0Ufev2IEUg5kHZSy6z29gtJg+9QKj xeqbaxgtGpoesVi07H7PZLH/6XMWi1ULr7FZnJ91isXi+cTnTBZLlzxitjjeu4PFgdvjwuQJ rB6LG1w9ds66y+7RcuQtkLfnJZPHxo//2T2eXNvM5LH59Qtmj6mz6z0+b5IL4IrisklJzcks Sy3St0vgyph05xlLwXmbiplf2tkbGDt1uhg5OSQETCRe3b7B2MXIxSEksJpRYtfGk6wQzidG iXOnXkE5yxgl5i9ezQjSwiagKLGvazsbiC0iYCxx7PASZhCbWeA1i8S3i9wgtrBAisSbpu0s EDWZElen72aGsPUk9ny7CBZnEVCVuHHkCNBMDg5eASuJiz1WIKaQgKXE1olxIBWcQNFnX2az gtiMAmIS30+tYYLYJC5x68l8JogHBCSW7DnPDGGLSrx8/I8VwpaXmPxjBhuErShx//tLdohe PYkbU6ewQdjaEssWvgbr5RUQlDg58wkLRL2kxMEVN1gmMErMQrJuFpL2WUjaZyFpX8DIsopR vLS4ODe9otg4L7Vcrzgxt7g0L10vOT93EyMwLZz+dzhmB+O9Wx/1DjEycTAeYpTgYFYS4TWM 2ZcixJuSWFmVWpQfX1Sak1p8iFGag0VJnNcjdmK8kEB6YklqdmpqQWoRTJaJg1OqgSlOZX25 lECk6fkzJ/QTXB2qF+2Jmav+zcr6pODh5eoWBzMSeAUf8Zbxb53U9OVDskjcuWDulSW/Vk0p Pj7Di+etupV6n0jKdav9T7+IrTxZvuXr2+SgLfbJyQeeTF6jdmzFgcPHH+r0da67IxNf+f29 C/eDpp6JV1K0q/iqzjwIivui+ZTpyJLCIn/GJ2nS3PuNrWfYXpQx7j7boTeJwSfJzHJe9Mzz m20OLp4bvlafp71eYV7XxG8rJZnKHtuvzvd7aHSOK3lzB++JGW8ijiWvCGt+1TfhMZNA5p2J a1wD7koyht53DpfoeecXe/DJ26n7Q92NXx/nvuF41KKc4ZK+0s9H5tq6XDtSeJ+cPK/EUpyR aKjFXFScCADcXZpwegMAAA== X-CMS-MailID: 20230725183957uscas1p2ca5293c7229ab989ad1a2d95395436a6 CMS-TYPE: 301P X-CMS-RootMailID: 20230725183957uscas1p2ca5293c7229ab989ad1a2d95395436a6 References: <20230725183939.2741025-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.12; envelope-from=fan.ni@samsung.com; helo=mailout2.w2.samsung.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fan Ni Not all dpa range in the dc regions is valid to access until an extent covering the range has been added. Add a bitmap for each region to record whether a dc block in the region has been backed by dc extent. For the bitmap, a bit in the bitmap represents a dc block. When a dc extent is added, all the bits of the blocks in the extent will be set, which will be cleared when the extent is released. Signed-off-by: Fan Ni --- hw/mem/cxl_type3.c | 155 ++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 1 + 2 files changed, 156 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 41a828598a..51943a36fc 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -787,13 +787,37 @@ static int cxl_create_dc_regions(CXLType3Dev *ct3d) /* dsmad_handle is set when creating cdat table entries */ region->flags = 0; + region->blk_bitmap = bitmap_new(region->len / region->block_size); + if (!region->blk_bitmap) { + break; + } + region_base += region->len; } + + if (i < ct3d->dc.num_regions) { + while (--i >= 0) { + g_free(ct3d->dc.regions[i].blk_bitmap); + } + return -1; + } + QTAILQ_INIT(&ct3d->dc.extents); return 0; } +static void cxl_destroy_dc_regions(CXLType3Dev *ct3d) +{ + int i; + struct CXLDCD_Region *region; + + for (i = 0; i < ct3d->dc.num_regions; i++) { + region = &ct3d->dc.regions[i]; + g_free(region->blk_bitmap); + } +} + static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { DeviceState *ds = DEVICE(ct3d); @@ -1021,6 +1045,7 @@ err_free_special_ops: g_free(regs->special_ops); err_address_space_free: if (ct3d->dc.host_dc) { + cxl_destroy_dc_regions(ct3d); address_space_destroy(&ct3d->dc.host_dc_as); } if (ct3d->hostpmem) { @@ -1043,6 +1068,7 @@ static void ct3_exit(PCIDevice *pci_dev) spdm_sock_fini(ct3d->doe_spdm.socket); g_free(regs->special_ops); if (ct3d->dc.host_dc) { + cxl_destroy_dc_regions(ct3d); address_space_destroy(&ct3d->dc.host_dc_as); } if (ct3d->hostpmem) { @@ -1053,6 +1079,110 @@ static void ct3_exit(PCIDevice *pci_dev) } } +/* + * This function will marked the dpa range [dpa, dap + len) to be backed and + * accessible, this happens when a dc extent is added and accepted by the + * host. + */ +static void set_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, + uint64_t len) +{ + int i; + CXLDCD_Region *region = &ct3d->dc.regions[0]; + + if (dpa < region->base + || dpa >= region->base + ct3d->dc.total_capacity) + return; + + /* + * spec 3.0 9.13.3: Regions are used in increasing-DPA order, with + * Region 0 being used for the lowest DPA of Dynamic Capacity and + * Region 7 for the highest DPA. + * So we check from the last region to find where the dpa belongs. + * access across multiple regions is not allowed. + **/ + for (i = ct3d->dc.num_regions - 1; i >= 0; i--) { + region = &ct3d->dc.regions[i]; + if (dpa >= region->base) { + break; + } + } + + bitmap_set(region->blk_bitmap, (dpa - region->base) / region->block_size, + len / region->block_size); +} + +/* + * This function check whether a dpa range [dpa, dpa + len) has been backed + * with dc extents, used when validating read/write to dc regions + */ +static bool test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, + uint64_t len) +{ + int i; + CXLDCD_Region *region = &ct3d->dc.regions[0]; + uint64_t nbits; + long nr; + + if (dpa < region->base + || dpa >= region->base + ct3d->dc.total_capacity) + return false; + + /* + * spec 3.0 9.13.3: Regions are used in increasing-DPA order, with + * Region 0 being used for the lowest DPA of Dynamic Capacity and + * Region 7 for the highest DPA. + * So we check from the last region to find where the dpa belongs. + * access across multiple regions is not allowed. + */ + for (i = ct3d->dc.num_regions - 1; i >= 0; i--) { + region = &ct3d->dc.regions[i]; + if (dpa >= region->base) { + break; + } + } + + nr = (dpa - region->base) / region->block_size; + nbits = len / region->block_size; + return find_next_zero_bit(region->blk_bitmap, nbits, nr) >= nr + nbits; +} + +/* + * This function will marked the dpa range [dpa, dap + len) to be unbacked and + * inaccessible, this happens when a dc extent is added and accepted by the + * host. + */ +static void clear_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, + uint64_t len) +{ + int i; + CXLDCD_Region *region = &ct3d->dc.regions[0]; + uint64_t nbits; + long nr; + + if (dpa < region->base + || dpa >= region->base + ct3d->dc.total_capacity) + return; + + /* + * spec 3.0 9.13.3: Regions are used in increasing-DPA order, with + * Region 0 being used for the lowest DPA of Dynamic Capacity and + * Region 7 for the highest DPA. + * So we check from the last region to find where the dpa belongs. + * access across multiple regions is not allowed. + */ + for (i = ct3d->dc.num_regions - 1; i >= 0; i--) { + region = &ct3d->dc.regions[i]; + if (dpa >= region->base) { + break; + } + } + + nr = (dpa - region->base) / region->block_size; + nbits = len / region->block_size; + bitmap_clear(region->blk_bitmap, nr, nbits); +} + static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr host_addr, uint64_t *dpa) { uint32_t *cache_mem = ct3d->cxl_cstate.crb.cache_mem_registers; @@ -1145,6 +1275,10 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d, *as = &ct3d->hostpmem_as; *dpa_offset -= vmr_size; } else { + if (!test_region_block_backed(ct3d, *dpa_offset, size)) { + return -ENODEV; + } + *as = &ct3d->dc.host_dc_as; *dpa_offset -= (vmr_size + pmr_size); } @@ -1944,6 +2078,27 @@ static void qmp_cxl_process_dynamic_capacity_event(const char *path, } g_free(extents); + + /* Another choice is to do the set/clear after getting mailbox response*/ + list = records; + while (list) { + dpa = list->value->dpa * 1024 * 1024; + len = list->value->len * 1024 * 1024; + rid = list->value->region_id; + + switch (type) { + case DC_EVENT_ADD_CAPACITY: + set_region_block_backed(dcd, dpa, len); + break; + case DC_EVENT_RELEASE_CAPACITY: + clear_region_block_backed(dcd, dpa, len); + break; + default: + error_setg(errp, "DC event type not handled yet"); + break; + } + list = list->next; + } } void qmp_cxl_add_dynamic_capacity_event(const char *path, diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 01a5eaca48..1f85c88017 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -412,6 +412,7 @@ typedef struct CXLDCD_Region { uint64_t block_size; uint32_t dsmadhandle; uint8_t flags; + unsigned long *blk_bitmap; } CXLDCD_Region; struct CXLType3Dev {