From patchwork Fri Jul 21 13:57:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1810941 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=iRZA/5Ne; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R6rkD6v55z1yYC for ; Fri, 21 Jul 2023 23:58:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230306AbjGUN62 (ORCPT ); Fri, 21 Jul 2023 09:58:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229644AbjGUN61 (ORCPT ); Fri, 21 Jul 2023 09:58:27 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 809D130F4; Fri, 21 Jul 2023 06:58:02 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-51d95aed33aso2614083a12.3; Fri, 21 Jul 2023 06:58:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689947881; x=1690552681; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=QoSMNchEXwuX3x9QSSuoNR4qaNrXEAa88B7oBatCh9k=; b=iRZA/5Ne/3oru5JOq3496Ym3LZws8ffLUXRPdlg0DcwqM1jc8QzuScL2Dur/m9QAQI rE0yvxSCuuYgqE5kOAyomzzny6zbBa+6NrXJ+OMo27aOtmgFj8u4CeR4nDyepvSJci2+ M+FwO+R0DJvLFgocAMiN9/So9jFJqQg+L5zIfsnrQ1qxMrBSbN1jNIWo8o3jlGIjdzkS 7w1+PEafbgmgcjb+2DWAHzU/UDKlQYFsNyUylBeW2hCs0fFS6Rmwr79YltSHAFFi6s30 4Q8ncUzA/Is+sB8vKKG3JytEXlUqLgbTXffjMV+CMX1/dgMmU6y1oqpf4wq5ZflZHsw1 ZGhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689947881; x=1690552681; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=QoSMNchEXwuX3x9QSSuoNR4qaNrXEAa88B7oBatCh9k=; b=lgny7LbevnFIe16THKJSGNg9lfTlyui7r216LGuj1oW4HET7GwitIWSd58u76r6I+Y b3nIh/1lSLEm0vnVjrtXZ8/UH7nyx0D+rvFSuueUOoFQzOE2rYkvE3xcskO2IqVlRpcI Xd3NazRXGvlwJCZVbsLvSHTVeXFItG9JUehc6nATJUB1E6Hvd20rXsSRcllvJXDOZL78 ww7PWjiWmwsjlLAQSgS5c9mGaOo4o304LQM5LEHXKRfhR7PzJvPgFk9xOS+uYRZ72mh2 nNQWdtObxDVZ6ulNrUbJ6oFsKN4O+ihlVO1zu50/ZYFbklvnb1u6knFLZa345S8zE4JO +FkA== X-Gm-Message-State: ABy/qLaw03SVODzY4wrKbsJ1c2JlXLXUHP+/yBJhwZqBNYoCeIFY06tv AzDUp0/qVGyBMGnmq0DbfVo= X-Google-Smtp-Source: APBJJlHmttUgEOA8yerCrYZ3YpsTBZRkS659sRzG7iiET26bD9k0Lb9TaFyYTCHJdPm+Jcdy4SDrHg== X-Received: by 2002:aa7:c394:0:b0:521:a740:29b7 with SMTP id k20-20020aa7c394000000b00521a74029b7mr1630499edq.36.1689947880398; Fri, 21 Jul 2023 06:58:00 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id s11-20020aa7cb0b000000b0051def9be785sm2131434edt.85.2023.07.21.06.57.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 06:58:00 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v2 1/7] dt-bindings: arm: tegra: pmc: Improve property descriptions Date: Fri, 21 Jul 2023 15:57:53 +0200 Message-ID: <20230721135759.2994770-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Reformat the description of various properties to make them more consistent with existing ones. Make use of json-schema's ability to provide a description for individual list items to make improve the documentation further. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - instead of rewriting it, drop the reg property description in patch 2 - add Reviewed-by: from Rob .../arm/tegra/nvidia,tegra20-pmc.yaml | 212 +++++++++--------- 1 file changed, 103 insertions(+), 109 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 89191cfdf619..38fe66142547 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -26,12 +26,10 @@ properties: clock-names: items: + # Tegra clock of the same name - const: pclk + # 32 KHz clock input - const: clk32k_in - description: - Must includes entries pclk and clk32k_in. - pclk is the Tegra clock of that name and clk32k_in is 32KHz clock - input to Tegra. clocks: maxItems: 2 @@ -41,105 +39,103 @@ properties: '#clock-cells': const: 1 - description: - Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. - PMC also has blink control which allows 32Khz clock output to - Tegra blink pad. - Consumer of PMC clock should specify the desired clock by having - the clock ID in its "clocks" phandle cell with pmc clock provider. - See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC - clock IDs. + description: | + Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink + control which allows 32Khz clock output to Tegra blink pad. + + Consumer of PMC clock should specify the desired clock by having the + clock ID in its "clocks" phandle cell with PMC clock provider. See + include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs. '#interrupt-cells': const: 2 - description: - Specifies number of cells needed to encode an interrupt source. - The value must be 2. + description: Specifies number of cells needed to encode an interrupt + source. interrupt-controller: true nvidia,invert-interrupt: $ref: /schemas/types.yaml#/definitions/flag - description: Inverts the PMU interrupt signal. - The PMU is an external Power Management Unit, whose interrupt output - signal is fed into the PMC. This signal is optionally inverted, and - then fed into the ARM GIC. The PMC is not involved in the detection - or handling of this interrupt signal, merely its inversion. + description: Inverts the PMU interrupt signal. The PMU is an external Power + Management Unit, whose interrupt output signal is fed into the PMC. This + signal is optionally inverted, and then fed into the ARM GIC. The PMC is + not involved in the detection or handling of this interrupt signal, + merely its inversion. nvidia,core-power-req-active-high: $ref: /schemas/types.yaml#/definitions/flag - description: Core power request active-high. + description: core power request active-high nvidia,sys-clock-req-active-high: $ref: /schemas/types.yaml#/definitions/flag - description: System clock request active-high. + description: system clock request active-high nvidia,combined-power-req: $ref: /schemas/types.yaml#/definitions/flag - description: combined power request for CPU and Core. + description: combined power request for CPU and core nvidia,cpu-pwr-good-en: $ref: /schemas/types.yaml#/definitions/flag - description: - CPU power good signal from external PMIC to PMC is enabled. + description: CPU power good signal from external PMIC to PMC is enabled nvidia,suspend-mode: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2] - description: - The suspend mode that the platform should use. - Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh - Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh - Mode 2 is for LP2, CPU voltage off + description: the suspend mode that the platform should use + oneOf: + - description: LP0, CPU + Core voltage off and DRAM in self-refresh + const: 0 + - description: LP1, CPU voltage off and DRAM in self-refresh + const: 1 + - description: LP2, CPU voltage off + const: 2 nvidia,cpu-pwr-good-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: CPU power good time in uSec. + description: CPU power good time in microseconds nvidia,cpu-pwr-off-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: CPU power off time in uSec. + description: CPU power off time in microseconds nvidia,core-pwr-good-time: $ref: /schemas/types.yaml#/definitions/uint32-array - description: - - Core power good time in uSec. + description: core power good time in microseconds + items: + - description: oscillator stable time + - description: power stable time nvidia,core-pwr-off-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: Core power off time in uSec. + description: core power off time in microseconds nvidia,lp0-vec: $ref: /schemas/types.yaml#/definitions/uint32-array - description: - Starting address and length of LP0 vector. - The LP0 vector contains the warm boot code that is executed - by AVP when resuming from the LP0 state. - The AVP (Audio-Video Processor) is an ARM7 processor and - always being the first boot processor when chip is power on - or resume from deep sleep mode. When the system is resumed - from the deep sleep mode, the warm boot code will restore - some PLLs, clocks and then brings up CPU0 for resuming the - system. + description: | + Starting address and length of LP0 vector. The LP0 vector contains the + warm boot code that is executed by AVP when resuming from the LP0 state. + The AVP (Audio-Video Processor) is an ARM7 processor and always being + the first boot processor when chip is power on or resume from deep sleep + mode. When the system is resumed from the deep sleep mode, the warm boot + code will restore some PLLs, clocks and then brings up CPU0 for resuming + the system. + items: + - description: starting address of LP0 vector + - description: length of LP0 vector core-supply: - description: - Phandle to voltage regulator connected to the SoC Core power rail. + description: phandle to voltage regulator connected to the SoC core power + rail core-domain: type: object - description: | - The vast majority of hardware blocks of Tegra SoC belong to a - Core power domain, which has a dedicated voltage rail that powers - the blocks. - + description: The vast majority of hardware blocks of Tegra SoC belong to a + core power domain, which has a dedicated voltage rail that powers the + blocks. properties: operating-points-v2: - description: - Should contain level, voltages and opp-supported-hw property. - The supported-hw is a bitfield indicating SoC speedo or process - ID mask. + description: Should contain level, voltages and opp-supported-hw + property. The supported-hw is a bitfield indicating SoC speedo or + process ID mask. "#power-domain-cells": const: 0 @@ -152,37 +148,32 @@ properties: i2c-thermtrip: type: object - description: - On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, - hardware-triggered thermal reset will be enabled. - + description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode + exists, hardware-triggered thermal reset will be enabled. properties: nvidia,i2c-controller-id: $ref: /schemas/types.yaml#/definitions/uint32 - description: - ID of I2C controller to send poweroff command to PMU. - Valid values are described in section 9.2.148 - "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference - Manual. + description: ID of I2C controller to send poweroff command to PMU. + Valid values are described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" + of the Tegra K1 Technical Reference Manual. nvidia,bus-addr: $ref: /schemas/types.yaml#/definitions/uint32 - description: Bus address of the PMU on the I2C bus. + description: bus address of the PMU on the I2C bus nvidia,reg-addr: $ref: /schemas/types.yaml#/definitions/uint32 - description: PMU I2C register address to issue poweroff command. + description: PMU I2C register address to issue poweroff command nvidia,reg-data: $ref: /schemas/types.yaml#/definitions/uint32 - description: Poweroff command to write to PMU. + description: power-off command to write to PMU nvidia,pinmux-id: $ref: /schemas/types.yaml#/definitions/uint32 - description: - Pinmux used by the hardware when issuing Poweroff command. - Defaults to 0. Valid values are described in section 12.5.2 - "Pinmux Support" of the Tegra4 Technical Reference Manual. + description: Pinmux used by the hardware when issuing power-off command. + Defaults to 0. Valid values are described in section 12.5.2 "Pinmux + Support" of the Tegra4 Technical Reference Manual. required: - nvidia,i2c-controller-id @@ -195,41 +186,44 @@ properties: powergates: type: object description: | - This node contains a hierarchy of power domain nodes, which should - match the powergates on the Tegra SoC. Each powergate node - represents a power-domain on the Tegra SoC that can be power-gated - by the Tegra PMC. - Hardware blocks belonging to a power domain should contain - "power-domains" property that is a phandle pointing to corresponding - powergate node. - The name of the powergate node should be one of the below. Note that - not every powergate is applicable to all Tegra devices and the following - list shows which powergates are applicable to which devices. - Please refer to Tegra TRM for mode details on the powergate nodes to - use for each power-gate block inside Tegra. - Name Description Devices Applicable - 3d 3D Graphics Tegra20/114/124/210 - 3d0 3D Graphics 0 Tegra30 - 3d1 3D Graphics 1 Tegra30 - aud Audio Tegra210 - dfd Debug Tegra210 - dis Display A Tegra114/124/210 - disb Display B Tegra114/124/210 - heg 2D Graphics Tegra30/114/124/210 - iram Internal RAM Tegra124/210 - mpe MPEG Encode All - nvdec NVIDIA Video Decode Engine Tegra210 - nvjpg NVIDIA JPEG Engine Tegra210 - pcie PCIE Tegra20/30/124/210 - sata SATA Tegra30/124/210 - sor Display interfaces Tegra124/210 - ve2 Video Encode Engine 2 Tegra210 - venc Video Encode Engine All - vdec Video Decode Engine Tegra20/30/114/124 - vic Video Imaging Compositor Tegra124/210 - xusba USB Partition A Tegra114/124/210 - xusbb USB Partition B Tegra114/124/210 - xusbc USB Partition C Tegra114/124/210 + This node contains a hierarchy of power domain nodes, which should match + the powergates on the Tegra SoC. Each powergate node represents a power- + domain on the Tegra SoC that can be power-gated by the Tegra PMC. + + Hardware blocks belonging to a power domain should contain "power-domains" + property that is a phandle pointing to corresponding powergate node. + + The name of the powergate node should be one of the below. Note that not + every powergate is applicable to all Tegra devices and the following list + shows which powergates are applicable to which devices. + + Please refer to Tegra TRM for mode details on the powergate nodes to use + for each power-gate block inside Tegra. + + Name Description Devices Applicable + -------------------------------------------------------------- + 3d 3D Graphics Tegra20/114/124/210 + 3d0 3D Graphics 0 Tegra30 + 3d1 3D Graphics 1 Tegra30 + aud Audio Tegra210 + dfd Debug Tegra210 + dis Display A Tegra114/124/210 + disb Display B Tegra114/124/210 + heg 2D Graphics Tegra30/114/124/210 + iram Internal RAM Tegra124/210 + mpe MPEG Encode All + nvdec NVIDIA Video Decode Engine Tegra210 + nvjpg NVIDIA JPEG Engine Tegra210 + pcie PCIE Tegra20/30/124/210 + sata SATA Tegra30/124/210 + sor Display interfaces Tegra124/210 + ve2 Video Encode Engine 2 Tegra210 + venc Video Encode Engine All + vdec Video Decode Engine Tegra20/30/114/124 + vic Video Imaging Compositor Tegra124/210 + xusba USB Partition A Tegra114/124/210 + xusbb USB Partition B Tegra114/124/210 + xusbc USB Partition C Tegra114/124/210 patternProperties: "^[a-z0-9]+$": From patchwork Fri Jul 21 13:57:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1810943 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=GOyp6a7C; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R6rkK1kx1z1yYC for ; Fri, 21 Jul 2023 23:58:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229713AbjGUN6c (ORCPT ); Fri, 21 Jul 2023 09:58:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230343AbjGUN6a (ORCPT ); Fri, 21 Jul 2023 09:58:30 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A9C63AA8; Fri, 21 Jul 2023 06:58:04 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-991da766865so307497166b.0; Fri, 21 Jul 2023 06:58:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689947883; x=1690552683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sYtxsERINvfOgj4TjnONVaidkuvzw8sv8zecGnhSGTU=; b=GOyp6a7CNYyq6UbVYr7VmE8D+bXYRGraPwUeI19n4sLxVnheM07+DNEvz0nc9QFUr2 eovpJvbftUONq3cQcAMOMDcz0lJBl3FLsqpDw4ijThHqOFi6WcrlINXWyCcTP90Qm+Q5 OySY9C1ldFpHPLU+5AzSOu//YVfdJ0fnjeAGx86qo1DjZYdx8g31jnh9NpNE2UR5ShwQ bbt2zEWxLFN5Tetcw21Q0gSFUCA0u/0FVZWlTQHPBFDC5Mv/5PfHwQXBd4O0Ol+uakYR Nac0IJkvkpO4/qS1sx+QBVJ8uG+WOWrFuvmxyJ7dzNl+wYtpB6D+vZKlBtv/X1hoP7P8 7CLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689947883; x=1690552683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sYtxsERINvfOgj4TjnONVaidkuvzw8sv8zecGnhSGTU=; b=MXo+81xVjba+58d5evBuUe7Kh4X0cB2yltSnYF8A19MW4O6FwZamSCSynh3btheXLP flt/g/ykrioJNgtjo9d8asd8U2q5X2CExirtaZio1xkjyduAFjUwaMrywP1gjf5dhyS5 PAq1hh8Upzufh26KKXew3RS2QLADYpQe99sMako0815zsGQZkbWySyueViNeoECWx2tv LM77a2pGyHtCQKLeYWNWW2zwdQilnUT6CiFbopv3gxtTPthGCbpndOj88pEYSTRU/iFW xmXdq0p6NJLqLmkRPYfqqGkZXxnjrKIb5xpL7q/Cc2nQ2XfY5SIAnWy2/u4AjoExDUqD inRA== X-Gm-Message-State: ABy/qLbR9YKLBxV316hjp5uo1rTArEYfC1JghrvVbtZTU8x6Mr8e8jsK YvWYswC1uyja4nvT5ZRHrrA= X-Google-Smtp-Source: APBJJlGK5sNXwgeiMcH8XhtWrLWaHd4qRoqbwtzBqKGyIcOyamL7eg1DMuX41JgiwBfo5/S2VJy3WQ== X-Received: by 2002:a17:906:2086:b0:991:fef4:bb7 with SMTP id 6-20020a170906208600b00991fef40bb7mr1641707ejq.73.1689947882619; Fri, 21 Jul 2023 06:58:02 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id p2-20020a17090628c200b00997e99a662bsm2193899ejd.20.2023.07.21.06.58.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 06:58:01 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v2 2/7] dt-bindings: arm: tegra: pmc: Remove useless boilerplate descriptions Date: Fri, 21 Jul 2023 15:57:54 +0200 Message-ID: <20230721135759.2994770-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721135759.2994770-1-thierry.reding@gmail.com> References: <20230721135759.2994770-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The descriptions for the clocks and resets properties are no longer useful in the context of json-schema, so drop them. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - drop description of "reg" property - add Reviewed-by: from Rob .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 38fe66142547..0ac258bc7be0 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -21,8 +21,6 @@ properties: reg: maxItems: 1 - description: - Offset and length of the register set for the device. clock-names: items: @@ -33,9 +31,6 @@ properties: clocks: maxItems: 2 - description: - Must contain an entry for each entry in clock-names. - See ../clocks/clocks-bindings.txt for details. '#clock-cells': const: 1 @@ -234,18 +229,10 @@ properties: clocks: minItems: 1 maxItems: 8 - description: - Must contain an entry for each clock required by the PMC - for controlling a power-gate. - See ../clocks/clock-bindings.txt document for more details. resets: minItems: 1 maxItems: 8 - description: - Must contain an entry for each reset required by the PMC - for controlling a power-gate. - See ../reset/reset.txt for more details. power-domains: maxItems: 1 From patchwork Fri Jul 21 13:57:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1810946 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=Q4zYfoCF; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R6rkM4Hgcz20Fh for ; Fri, 21 Jul 2023 23:58:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231502AbjGUN6d (ORCPT ); Fri, 21 Jul 2023 09:58:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231556AbjGUN6b (ORCPT ); Fri, 21 Jul 2023 09:58:31 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5FF130FF; Fri, 21 Jul 2023 06:58:05 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-992b27e1c55so306475766b.2; Fri, 21 Jul 2023 06:58:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689947883; x=1690552683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FRDa+hXtdMdC6ZYOUEjHUlfDPteWrj1xebQwjE7g54o=; b=Q4zYfoCFspo6eRw6dSpFr4ss/iTcfDE61aduF8axDGPX1B7AM1e86J0/f9slVgfGhs I62z//MixkWJSLndiO11zDHMeStPjmb8oH08bsYjighwx1Y+shsP+x+qqzKge6V/KjYc Ed3oeYunr1S+SlqMoCiDyGe/StgYAGHN272cwJG3dIH/FJVBr+csnda6WgPAVvOWcRIO r8qPCcp+3cyL/mt2w8Nug9RNmGUSdowrXTtRs87EcnqWHttOoXjyiLZlslIfTi+cJLGB R4DXSEBbDP9WCvdd8B/rInXMMAZlVWFPsaPVDTY9XBpSny+2lHhRgayQ4vhwaNGTvZ0j 9gsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689947883; x=1690552683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FRDa+hXtdMdC6ZYOUEjHUlfDPteWrj1xebQwjE7g54o=; b=K4+YEunUKUqnqqZdFCg1tPbtj6Hi3Jwbjw4sXbKfZi2m4epXxa6EtXOaYXhnEFl9md qPttoQs48RdU/jeWQSj/giFB0dxFDXeMqxmDPBD3tAds6tGUDwQHxMLuJ7LDAfTlfLpP ftBOGjNo0BzYCwiBfk2H9SgqPyDuG7FZAhD5JuNXx3JzikGT44yhieStolt24hivN8jQ ifvMbOMTX+tRITrxIaYY4OgHHsJDEX/ws6cPNKAgAM1p//C6QFkbhGFsw/xZGrg47vpU B+iBdvSPyb3tGg1XT1G8NHbllJ9/3kAuRrgs4SuflP0UUw4L2GnQGmzxqI+KdZGMi3Jt VjQg== X-Gm-Message-State: ABy/qLa+ZbF5Xsr2BX1RqrW2UB9DaxSP0kCnXErfb42BG5SCuSNS8vbG rKKk5YWeQ0Km2q1L+92pONc= X-Google-Smtp-Source: APBJJlGXo6KJTtBvDxpzKoa0Ll06/93qqmYqGLS3iXNOGuxfLbZEIYNingZpfW6vsOFMLwngcnYOSA== X-Received: by 2002:a17:906:cc13:b0:99b:4bd4:df5d with SMTP id ml19-20020a170906cc1300b0099b4bd4df5dmr1652607ejb.42.1689947883591; Fri, 21 Jul 2023 06:58:03 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id qp7-20020a170907206700b00992b66e54e9sm2208013ejb.214.2023.07.21.06.58.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 06:58:03 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v2 3/7] dt-bindings: arm: tegra: pmc: Move additionalProperties Date: Fri, 21 Jul 2023 15:57:55 +0200 Message-ID: <20230721135759.2994770-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721135759.2994770-1-thierry.reding@gmail.com> References: <20230721135759.2994770-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding For indented subschemas it can be difficult to understand which block an additionalProperties property belongs to. Moving it closer to the beginning of a block is a good way to clarify this. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - add Reviewed-by: from Rob .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 0ac258bc7be0..d6f2c5862841 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -126,6 +126,7 @@ properties: description: The vast majority of hardware blocks of Tegra SoC belong to a core power domain, which has a dedicated voltage rail that powers the blocks. + additionalProperties: false properties: operating-points-v2: description: Should contain level, voltages and opp-supported-hw @@ -139,12 +140,11 @@ properties: - operating-points-v2 - "#power-domain-cells" - additionalProperties: false - i2c-thermtrip: type: object description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, hardware-triggered thermal reset will be enabled. + additionalProperties: false properties: nvidia,i2c-controller-id: $ref: /schemas/types.yaml#/definitions/uint32 @@ -176,10 +176,9 @@ properties: - nvidia,reg-addr - nvidia,reg-data - additionalProperties: false - powergates: type: object + additionalProperties: false description: | This node contains a hierarchy of power domain nodes, which should match the powergates on the Tegra SoC. Each powergate node represents a power- @@ -224,7 +223,6 @@ properties: "^[a-z0-9]+$": type: object additionalProperties: false - properties: clocks: minItems: 1 @@ -246,8 +244,6 @@ properties: - resets - '#power-domain-cells' - additionalProperties: false - patternProperties: "^[a-f0-9]+-[a-f0-9]+$": type: object From patchwork Fri Jul 21 13:57:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1810948 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=RWwj3xr5; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R6rkN3FSbz20Fh for ; Fri, 21 Jul 2023 23:58:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231591AbjGUN6e (ORCPT ); Fri, 21 Jul 2023 09:58:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229914AbjGUN6b (ORCPT ); Fri, 21 Jul 2023 09:58:31 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CD492D47; Fri, 21 Jul 2023 06:58:06 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-991c786369cso307560966b.1; Fri, 21 Jul 2023 06:58:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689947884; x=1690552684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lsEowniGr6Wk6wqHwLPaL+irpr9VN82cw7vXn+mEKas=; b=RWwj3xr5hRerGmcDGrcpuQd8WhB4Fb7tIlxcnscETLspdHaygKJYBqvYdeB5un2c1k NRH2/zAiYU+ctJjD++uUX2GoP2i19sp7rPwr91vOdI7iGND7zL3weN3900BtafUu1Vz+ Mg/f7oqcw1qEWE061XGGHNwxPIbDzLH8eLlMwc0hMZeURPVzG4Z499m6yVJ6zCzBIkz5 rjRKx2o8ccBCoILM2FdLUwJFvgngzp9/boNAUrOwKq7GiTMQvR2QQ0UG7URozObNSHOa C5nwQYv+K+u4viumbkyhGSgUyw7tDSy3U8lwh/AYA7jBmy405cstqSB+DGO5Wy0ZrZBB npAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689947884; x=1690552684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lsEowniGr6Wk6wqHwLPaL+irpr9VN82cw7vXn+mEKas=; b=CjKuUPCQNrCSrPFwHLeO0I4nYUwtzN2b60dGzDOUrRYCwi0UxqIdUg19wGsJvmaMcS AElSdD6VB0+vzCGCeAsK6XD+Y5lAlXxUx6tHggk0qJSUC++FnBCeewNliqMVKupEcCi3 NMGydlwsINfCHioewtgTmXFRFQrsDOU0EwfosnBT+j+JiXDJJN5b7zsWGNjx+FTe4mUs l87XD3mro5rvQ3+GROfnHfmel2W6XDXxSg3ss9hNHmx7f0Ic7yGrW4wgVjLKlI8Nki2A qSV3r6uAGkpP+/AS1xbbMEdOwWmgOZyncldYhAse51N//FY6/Bqf63AZD4lBIdS2rnU9 p5dw== X-Gm-Message-State: ABy/qLY+pFzcChSq6TMm2j59C/XdOAezzIaFaYLekEm4BOyjepnqRLs4 M5rHqUcKzxPy0M2Hn4XK14c= X-Google-Smtp-Source: APBJJlGqoMAC1BN/Ut087B4UlQOOkbEWOPF3etl3CDHqx5Y+6s+utsxojN1JrjXHCuXwZJ7KP7IaQQ== X-Received: by 2002:a17:907:2cd7:b0:99b:44aa:fae0 with SMTP id hg23-20020a1709072cd700b0099b44aafae0mr1617141ejc.21.1689947884440; Fri, 21 Jul 2023 06:58:04 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id l2-20020a170906230200b00997e52cb30bsm2172733eja.121.2023.07.21.06.58.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 06:58:04 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v2 4/7] dt-bindings: arm: tegra: pmc: Increase maximum number of clocks per powergate Date: Fri, 21 Jul 2023 15:57:56 +0200 Message-ID: <20230721135759.2994770-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721135759.2994770-1-thierry.reding@gmail.com> References: <20230721135759.2994770-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Some powergate definitions need more than 8 clocks, so bump the number up to 10, which is the current maximum in any known device tree file. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - add Acked-by: from Rob .../devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index d6f2c5862841..a336a75d8b82 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -226,7 +226,7 @@ properties: properties: clocks: minItems: 1 - maxItems: 8 + maxItems: 10 resets: minItems: 1 From patchwork Fri Jul 21 13:57:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1810952 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=Z9MyjWw/; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R6rkQ1bGXz20Fh for ; Fri, 21 Jul 2023 23:58:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231341AbjGUN6g (ORCPT ); Fri, 21 Jul 2023 09:58:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231472AbjGUN6d (ORCPT ); Fri, 21 Jul 2023 09:58:33 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32762CE; Fri, 21 Jul 2023 06:58:08 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-4fbf1f6c771so3175002e87.1; Fri, 21 Jul 2023 06:58:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689947886; x=1690552686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lqx9rZlOEWBvcbgCTsoEQr6GASQ7BEyeOZtqj7Jp/nw=; b=Z9MyjWw/G47mbUd2P3fUTwg7UrRfA56OnXv25E6cdqKbnVonqJnc6NTQNEFy8f+Kht A8F6Fkz8zvZXEGm9rL+nXth2XxcIVrs/XHjqFwaU9IMFcG6c2lU53WB4PXEti3ouwJB8 PA07fnGtpVDmYIyb1e6OxT9Ubl7bF8ZlEIrpO/tqyPWzCVmWD5Fo2PZN766SzaGLdf5L MElAjH/KiwlPOfsS9hR0V8LgL7JqG34vG+wiIQzbMb5kZKLV9L4YbxwpbTPxK8nmW7e8 FWDH8cRo0Xs+m8wJpRQbtz+tmY6onu0gytxLkwIMK4xcI7uB4Ja0mbM84KHDOFv3hGNQ Cwqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689947886; x=1690552686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lqx9rZlOEWBvcbgCTsoEQr6GASQ7BEyeOZtqj7Jp/nw=; b=XEYbiS9YTZSPCeVcOetbZ0lQmEep2Jmt4DEHOf/YAwugAmzSFrjFckvPJ9qOFV8Gsz YPTt/FLxWX96gR6WY5myK0/N/mcBBQ9TrgPX1UGFJB0brhhDE12sH0L6Fbxdp5lwJ0CI KwweXQYq9R0NevTynAFNkD/zzHAUWwMFaH25Kl3ptmgryR8RjyL2WWUCKqAI8XMNToXB tv9Sh2ndBEc9U9lLT0AUmpUQ4yY6ppHN7F0adlShFmyx5zdOdkGNYBJ8ltmk65emTkMl wPvv833oIarolQm7Dj9I5LHn3B8zrqV2k8Mx0gXDKiMKBa4qx6zbMPV4SB6obXpt0fqo f+xQ== X-Gm-Message-State: ABy/qLYR5uFUCumPaglCiGux7RyBBLYJj2MDJFexUa/9cz0XnQI7VZAJ jwDSgcqMZd1zxtjpCkoQJqAObbh1JFI= X-Google-Smtp-Source: APBJJlGPLpeNjzvrYUrO86grBKDrTHaFRE/zChFSYNlKHDhF2aAszqvj5g11JhhmLEa6SLC7l96Z0A== X-Received: by 2002:a05:6512:2208:b0:4fb:c028:d76f with SMTP id h8-20020a056512220800b004fbc028d76fmr1727547lfu.35.1689947885473; Fri, 21 Jul 2023 06:58:05 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id c12-20020aa7df0c000000b005217412e18dsm2165471edy.48.2023.07.21.06.58.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 06:58:05 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 5/7] dt-bindings: arm: tegra: pmc: Restructure pad configuration node schema Date: Fri, 21 Jul 2023 15:57:57 +0200 Message-ID: <20230721135759.2994770-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721135759.2994770-1-thierry.reding@gmail.com> References: <20230721135759.2994770-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The pad configuration node schema in its current form can accidentally match other properties as well. Restructure the schema to better match how the device trees are using these. Signed-off-by: Thierry Reding --- Changes in v2: - highlight quirks working around possible core schema - use phandle: true instead of fully redefining it - drop unneeded status property definition .../arm/tegra/nvidia,tegra20-pmc.yaml | 184 ++++++++++++------ 1 file changed, 122 insertions(+), 62 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index a336a75d8b82..0cbc16ec4267 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -244,69 +244,79 @@ properties: - resets - '#power-domain-cells' -patternProperties: - "^[a-f0-9]+-[a-f0-9]+$": + pinmux: type: object - description: - This is a Pad configuration node. On Tegra SOCs a pad is a set of - pins which are configured as a group. The pin grouping is a fixed - attribute of the hardware. The PMC can be used to set pad power state - and signaling voltage. A pad can be either in active or power down mode. - The support for power state and signaling voltage configuration varies - depending on the pad in question. 3.3V and 1.8V signaling voltages - are supported on pins where software controllable signaling voltage - switching is available. - - The pad configuration state nodes are placed under the pmc node and they - are referred to by the pinctrl client properties. For more information - see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. - The pad name should be used as the value of the pins property in pin - configuration nodes. - - The following pads are present on Tegra124 and Tegra132 - audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, - hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, - sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. - - The following pads are present on Tegra210 - audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, - debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, - hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, - sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. - - properties: - pins: - $ref: /schemas/types.yaml#/definitions/string - description: Must contain name of the pad(s) to be configured. - - low-power-enable: - $ref: /schemas/types.yaml#/definitions/flag - description: Configure the pad into power down mode. - - low-power-disable: - $ref: /schemas/types.yaml#/definitions/flag - description: Configure the pad into active mode. - - power-source: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or - TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - Power state can be configured on all Tegra124 and Tegra132 - pads. None of the Tegra124 or Tegra132 pads support signaling - voltage switching. - All of the listed Tegra210 pads except pex-cntrl support power - state configuration. Signaling voltage switching is supported - on below Tegra210 pads. - audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, - sdmmc3, spi, spi-hv, and uart. - - required: - - pins - - additionalProperties: false + additionalProperties: + type: object + description: | + This is a pad configuration node. On Tegra SoCs a pad is a set of pins + which are configured as a group. The pin grouping is a fixed attribute + of the hardware. The PMC can be used to set pad power state and + signaling voltage. A pad can be either in active or power down mode. + The support for power state and signaling voltage configuration varies + depending on the pad in question. 3.3V and 1.8V signaling voltages are + supported on pins where software controllable signaling voltage + switching is available. + + The pad configuration state nodes are placed under the pmc node and + they are referred to by the pinctrl client properties. For more + information see: + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + + The pad name should be used as the value of the pins property in pin + configuration nodes. + + The following pads are present on Tegra124 and Tegra132: + + audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, + hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, + pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, + usb_bias + + The following pads are present on Tegra210: + + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, + debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, + hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, + sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias + additionalProperties: false + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: Must contain name of the pad(s) to be configured. + + low-power-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into power down mode. + + low-power-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into active mode. + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The + values are defined in: + + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h + + Power state can be configured on all Tegra124 and Tegra132 pads. + None of the Tegra124 or Tegra132 pads support signaling voltage + switching. All of the listed Tegra210 pads except pex-cntrl support + power state configuration. Signaling voltage switching is supported + on the following Tegra210 pads: + + audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3, + spi, spi-hv, uart + + # XXX why is this needed? + phandle: true + + required: + - pins required: - compatible @@ -315,6 +325,56 @@ required: - clocks - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra124-pmc + then: + properties: + pinmux: + # XXX shouldn't be needed, but the DT validator complains about + # "additionalProperties" if "properties" doesn't exist + properties: + status: true + + additionalProperties: + type: object + properties: + pins: + items: + enum: [ audio, bb, cam, comp, csia, csb, cse, dsi, dsib, + dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand, + pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, + usb_bias ] + + - if: + properties: + compatible: + contains: + const: nvidia,tegra210-pmc + then: + properties: + pinmux: + # XXX shouldn't be needed, but the DT validator complains about + # "additionalProperties" if "properties" doesn't exist + properties: + status: true + + additionalProperties: + type: object + properties: + pins: + items: + enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie, + csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, + dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias, + pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, + usb-bias ] + additionalProperties: false dependencies: From patchwork Fri Jul 21 13:57:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1810950 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=WfQ3RemO; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4R6rkP2SRTz20Fh for ; Fri, 21 Jul 2023 23:58:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229644AbjGUN6f (ORCPT ); Fri, 21 Jul 2023 09:58:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231366AbjGUN6d (ORCPT ); Fri, 21 Jul 2023 09:58:33 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C5192D50; Fri, 21 Jul 2023 06:58:09 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-51de9c2bc77so2663072a12.3; Fri, 21 Jul 2023 06:58:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689947886; x=1690552686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CWqMB3Z6eA0gtm3C24bBTyUL2IADR5Mx3MSeqCPmjd8=; b=WfQ3RemO29FqWAZKKGNRk7GaDPE5o3FhQc5unyLgZVe8cDMiHXTJVFk3nb9w1/tBPy p8X/92W+xMBchdzhYzmJ3vgkEdRLA7tKztI5a5INO8Ua8ercNHxMpViw7bo88+py7Gu0 naax288ujQ6LJZem0NKTxot72Io4DHT6KA9MgfSv81vjExekEvzIAJm+w8LllJFWTpcR 4mGLjBGeI5tMHZoOaICuuHTaepFeS+YagnPTHjVzMa+zCrF2l+gTzxTmp6bsZau1YcRe 0pRlDcj3OHDuawNxw9//SEPvvry/sI7Ef2FCm+d+BiQ8G97IshENWw3slUgxkM4U8803 kzaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689947886; x=1690552686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CWqMB3Z6eA0gtm3C24bBTyUL2IADR5Mx3MSeqCPmjd8=; b=VR+A7WenyYlML9DOfe1gYy7PAmYt8VXTlQapO3zXBU8P3teOr7NqZAclGMh4Ejb5VY +anfb7IdDJRY3g76+PYy+5hFHYqUoZE/+6RiZFpv9GaAJE+ONC4t98hTmtWP7n83hZf3 iSpWxLjVqRcXv0HPnmaJuhnpPYTnT1lcOV3Xz7fN217nDLB6RTxgowBofwSI5HPTDjqC E3ANdi35rygiycqpyBudUoJhuaJbCQ6HWRs+ToydcqBlMqhVUzs6fl5ymPuNvH6Gt84J aVN2eJyUO074HSB3URIYpmj5yXpIVXlQ2xaee9HTPzbzTpaqT+7lkXjdVKwRki8JT0do eoPA== X-Gm-Message-State: ABy/qLYuZuslifKAdBD/OXZeBzePUpYvog6H0ohXgOx+e31AGhkyzYQN Y7CksnKx91npkSFEkDVwNIU= X-Google-Smtp-Source: APBJJlG3V/LyTD4HRDkIVhClpgD4iLCCqpfj3A36wMBfXN26KyKUABoqEGZbY3hYl6lsfRaRNacXEQ== X-Received: by 2002:a05:6402:1357:b0:51a:265a:8fca with SMTP id y23-20020a056402135700b0051a265a8fcamr1485489edw.27.1689947886314; Fri, 21 Jul 2023 06:58:06 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id u24-20020a05640207d800b0051a53d7b160sm2152212edy.80.2023.07.21.06.58.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 06:58:06 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v2 6/7] dt-bindings: arm: tegra: pmc: Reformat example Date: Fri, 21 Jul 2023 15:57:58 +0200 Message-ID: <20230721135759.2994770-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721135759.2994770-1-thierry.reding@gmail.com> References: <20230721135759.2994770-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Reformat the example using 4 spaces for indentation. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - add Acked-by: from Rob .../arm/tegra/nvidia,tegra20-pmc.yaml | 77 +++++++++---------- 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 0cbc16ec4267..67d69926f756 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -384,47 +384,46 @@ dependencies: examples: - | - #include #include #include - tegra_pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x7000e400 0x400>; - core-supply = <®ulator>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #clock-cells = <1>; - - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <4587 3876>; - nvidia,core-pwr-off-time = <39065>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - pd_core: core-domain { - operating-points-v2 = <&core_opp_table>; - #power-domain-cells = <0>; - }; - - powergates { - pd_audio: aud { - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - resets = <&tegra_car 198>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_xusbss: xusba { - clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; - resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - }; + pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x7000e400 0x400>; + core-supply = <®ulator>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + pd_core: core-domain { + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + + powergates { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; }; From patchwork Fri Jul 21 13:57:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1810954 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; 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[2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id lg23-20020a170906f89700b0098733a40bb7sm2221507ejb.155.2023.07.21.06.58.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 06:58:06 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v2 7/7] dt-bindings: arm: tegra: pmc: Relicense and move into soc/tegra directory Date: Fri, 21 Jul 2023 15:57:59 +0200 Message-ID: <20230721135759.2994770-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721135759.2994770-1-thierry.reding@gmail.com> References: <20230721135759.2994770-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Dual-license this binding for consistency with other Tegra bindings and move it into the soc/tegra directory. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - add Reviewed-by: from Rob .../bindings/{arm => soc}/tegra/nvidia,tegra20-pmc.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/{arm => soc}/tegra/nvidia,tegra20-pmc.yaml (99%) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml similarity index 99% rename from Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml rename to Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml index 67d69926f756..a2b8d59026ee 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml @@ -1,7 +1,7 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# +$id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Tegra Power Management Controller (PMC)