From patchwork Wed Mar 28 13:42:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aniruddha Banerjee X-Patchwork-Id: 892222 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CAO8T/0J"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40B8Fm636Xz9s0b for ; Thu, 29 Mar 2018 00:42:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753144AbeC1NmX (ORCPT ); Wed, 28 Mar 2018 09:42:23 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:38627 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751207AbeC1NmW (ORCPT ); Wed, 28 Mar 2018 09:42:22 -0400 Received: by mail-pg0-f68.google.com with SMTP id a15so941284pgn.5; Wed, 28 Mar 2018 06:42:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=lm70r1FMKC5DS32Db5lljDBLJLB0IqIjIIerTZFecZo=; b=CAO8T/0JsOpoFZNZ2fAkozuQDDTOE0d2aGCiQzMtyHnkV3fasS4GewpFhvem7emO2v C+D2tViCyyh5RW33hIBm9onDpszzg/o7wW6kLm8mmHlmujUopB3GjDBzVoECAgVnH8gw aFtZ+zbS1mfdEyry2F5LC8IxciWUyhhSoemB0SN/X7ZSYuE+Ok5bqzxuWKH/7K7LTZmF k/WlbZr1JxZjWPVWpmkyDCTavxzc6eol4aamBIyBevX3vchdHOOGTAOKV3bpaNoevtbR vwMGZf6rn0gn+132Ozid2vYiU8yF0SeMLsW8CENEWyd7IVemv1atCmc9wTRGsScEb0o9 yIxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=lm70r1FMKC5DS32Db5lljDBLJLB0IqIjIIerTZFecZo=; b=dMxaOf0Vnq+9tmdQ5Q/56gBI85Xx6SFFoVtWxI9i+KDHorg/iHVVuoIR7PQhuBXl5c rKBq8lsWJr9TgOSYFHTZxfIeG9+021ioBmglzU3F50jzMnGCeDrF/EnivRoR7HUatQR1 67VFyVIS0N2IGdH1I87l6kOD0/l1U1bjat57r9EUHJz/heBcVXmKFM1unCtVOJ6Ea65v Q9RSeg/9U8DBJ8dcHlmWSuBrnOiHFbmq8i22JsWoQy2ZTK0azpbIqe3fjmAGNFRbPTQ2 fo/G2LGJCbl5gZZixfxQs8Y4lEP1OS5FCP6excl7xBFtooxd4h/enkvzGIJBZLtuV69s Yusw== X-Gm-Message-State: AElRT7HBvTVTu6ebUHwP0jL9bYTag6tcBRDU4tKpvpAuKyfVxniXuMTm lEwe7IPFjmlplwo+ZY5bwamZqNYeD+o= X-Google-Smtp-Source: AIpwx49NFdN0zE1c1KkjMygZUPRvcfsOMRYIWIlUdOfyKbnU+Bjt4vqO6AAeQl926UUMac6fE//iqQ== X-Received: by 10.101.65.75 with SMTP id x11mr2648999pgp.203.1522244541252; Wed, 28 Mar 2018 06:42:21 -0700 (PDT) Received: from aniruddha-nvidia.nvidia.com ([121.244.166.165]) by smtp.gmail.com with ESMTPSA id l90sm9321363pfb.96.2018.03.28.06.42.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Mar 2018 06:42:20 -0700 (PDT) From: Aniruddha Banerjee To: marc.zyngier@arm.com, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Cc: aniruddhab@nvidia.com, stable@vger.kernel.org, vipink@nvidia.com, strasi@nvidia.com, swarren@nvidia.com, jonathanh@nvidia.com, talho@nvidia.com, treding@nvidia.com Subject: [PATCHv4] irqchip: arm-gic: take gic_lock when updating irq type Date: Wed, 28 Mar 2018 19:12:00 +0530 Message-Id: <20180328134200.7435-1-aniruddha.nitd@gmail.com> X-Mailer: git-send-email 2.16.2 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Aniruddha Banerjee The kernel documentation states that the locking of the irq-chip registers should be handled by the irq-chip driver. In the irq-gic, the accesses to the irqchip are seemingly not protected and multiple writes to SPIs from different irq descriptors do RMW requests without taking the irq-chip lock. When multiple irqs call the request_irq at the same time, there can be a simultaneous write at the gic distributor, leading to a race. Acquire the gic_lock when the irq_type is updated. Cc: stable@vger.kernel.org Signed-off-by: Aniruddha Banerjee --- Change from V1: * Moved the spinlock from irq-gic to irq-gic common, so that the fix is valid for GIC v1/v2/v3. Change from V2: * Fixup the Signed-off-by line. Change from V3: * Change raw_spin_lock to raw_spin_lock_irqsave and spin_unlock to raw_spin_unlock_irqrestore to protect against a potential deadlock when an interrupt handler changes the trigger type of any interrupt. drivers/irqchip/irq-gic-common.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c index 9ae71804b5dd..1c2ca8d51a70 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c @@ -21,6 +21,8 @@ #include "irq-gic-common.h" +static DEFINE_RAW_SPINLOCK(irq_controller_lock); + static const struct gic_kvm_info *gic_kvm_info; const struct gic_kvm_info *gic_get_kvm_info(void) @@ -52,11 +54,13 @@ int gic_configure_irq(unsigned int irq, unsigned int type, u32 confoff = (irq / 16) * 4; u32 val, oldval; int ret = 0; + unsigned long flags; /* * Read current configuration register, and insert the config * for "irq", depending on "type". */ + raw_spin_lock_irqsave(&irq_controller_lock, flags); val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff); if (type & IRQ_TYPE_LEVEL_MASK) val &= ~confmask; @@ -64,8 +68,10 @@ int gic_configure_irq(unsigned int irq, unsigned int type, val |= confmask; /* If the current configuration is the same, then we are done */ - if (val == oldval) + if (val == oldval) { + raw_spin_unlock_irqrestore(&irq_controller_lock, flags); return 0; + } /* * Write back the new configuration, and possibly re-enable @@ -83,6 +89,7 @@ int gic_configure_irq(unsigned int irq, unsigned int type, pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16); } + raw_spin_unlock_irqrestore(&irq_controller_lock, flags); if (sync_access) sync_access();