From patchwork Mon Jul 3 11:29:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Achal Verma X-Patchwork-Id: 1802683 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=klnc0xG8; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4QvkGs3KqLz20b1 for ; Mon, 3 Jul 2023 21:29:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230172AbjGCL3i (ORCPT ); Mon, 3 Jul 2023 07:29:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229917AbjGCL3i (ORCPT ); Mon, 3 Jul 2023 07:29:38 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2421EC; Mon, 3 Jul 2023 04:29:36 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 363BTG9b095606; Mon, 3 Jul 2023 06:29:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1688383756; bh=xDtP2HJQgfk6AN7TtOP/ryebO14+ERJGMm36HhtgU2Q=; h=From:To:CC:Subject:Date; b=klnc0xG8vrmpvDuVqdSlRNoClaR9Dz3fUQpMr+kcL1fTWNRJ0RBeESehAs6qKwC1h hau/3fOOAe/kAeT51HIRpJylQFRzIE1HfevMGUlqDZ3lVOUv5tU1pPesFuDJMKPlcW e8QnIkiz2UIkGMLep8PiaMEXigBmr1mweeQIuv90= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 363BTFx7048757 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 3 Jul 2023 06:29:15 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 3 Jul 2023 06:29:15 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 3 Jul 2023 06:29:15 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 363BTERL001690; Mon, 3 Jul 2023 06:29:15 -0500 From: Achal Verma To: Vignesh Raghavendra , Tom Joseph , Lorenzo Pieralisi , Krzysztof Wilczy_ski , Rob Herring , Bjorn Helgaas CC: , , , , Achal Verma Subject: [PATCH] PCI: j721e: Fix delay before PERST# deassert Date: Mon, 3 Jul 2023 16:59:14 +0530 Message-ID: <20230703112914.68806-1-a-verma1@ti.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org As per the PCIe Card Electromechanical specification REV. 3.0, PERST# signal should be de-asserted after minimum 100ms from the time power-rails become stable. Current delay of 100us is observed to be not enough on some custom platform implemented using TI's K3 SOCs. So, to ensure 100ms delay to give sufficient time for power-rails and refclk to become stable, change delay from 100us to 100ms. From PCIe Card Electromechanical specification REV. 3.0 section 2.6.2: TPVPERL: Power stable to PERST# inactive - 100ms T-PERST-CLK: REFCLK stable before PERST# inactive - 100 usec. Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver") Signed-off-by: Achal Verma --- drivers/pci/controller/cadence/pci-j721e.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index e70213c9060a..fa2b4c11d2c4 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -499,13 +499,12 @@ static int j721e_pcie_probe(struct platform_device *pdev) /* * "Power Sequencing and Reset Signal Timings" table in * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 - * indicates PERST# should be deasserted after minimum of 100us - * once REFCLK is stable. The REFCLK to the connector in RC - * mode is selected while enabling the PHY. So deassert PERST# - * after 100 us. + * indicates PERST# should be deasserted after minimum of 100ms + * after power rails achieve specified operating limits and + * within this period reference clock should also become stable. */ if (gpiod) { - usleep_range(100, 200); + msleep(100); gpiod_set_value_cansleep(gpiod, 1); }