From patchwork Wed Mar 28 08:54:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aniruddha Banerjee X-Patchwork-Id: 892026 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HsxEq2zX"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40B1sc5JMjz9s08 for ; Wed, 28 Mar 2018 19:54:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752568AbeC1Iyn (ORCPT ); Wed, 28 Mar 2018 04:54:43 -0400 Received: from mail-pl0-f68.google.com ([209.85.160.68]:39962 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752447AbeC1Iyl (ORCPT ); Wed, 28 Mar 2018 04:54:41 -0400 Received: by mail-pl0-f68.google.com with SMTP id x4-v6so1182866pln.7; Wed, 28 Mar 2018 01:54:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=ebAzNwrytD/Jm7ibYCp6FMNSY8kjl93ZhULkyuofghg=; b=HsxEq2zXnv/0aLyKtm9PlWCQC7HucLE5CAhGbNqGZMVWx2AGMXgWnKHNBK+QlnVQXw nl0hVc8bvbJSWSHRM09qfX2lJDCGV0rnK4JRbewRgsUFAHmLptS6KrB4svFmjPhYrG7w jwqSnYd3xFsYYWqJpuvVQ00RObk3XR5mxTlWhyMkEk3QQDncvzGJ49it/oAJCce4BJp/ DNe5oZ4Zgf1op1mU1eoMpzWX8sOzCVvtvuDyHvxOWt5WZhHd63RxWewiIQnEomwLzYqE dM3PxsbLnf1S7TbxO0o8zIOqal+kegURf2SEA09aTdpXywnwl7cg3rb1b+Wa3WsMljHW 0Ceg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ebAzNwrytD/Jm7ibYCp6FMNSY8kjl93ZhULkyuofghg=; b=hZRf74Z0CykvWe/+FYrGSsFzK82dBCkWG0nT0CrC1JWZLBQ87M5ad/3Tb0VbINqWwT O9rOtfilUjQvOMNrTQxliPiU3yVpD7JYGoYaCfMRZCe4avG4uKO+/+phkB22hBhD0bxp /ltcKSS4PrCztpLRZIu2uSjaTuGqOxLReKI4e0YSGlUAYY0gmcECWKO5xTK/fC8HJRvQ SshYmxQq0qaFxAcd6mThaCCpXpTURchTwtG9++i7QhvvXDqXV4DtrdjGyLEYOYcrAAWf Ve0C0yyhQoV2dEB5yiFHJAAz2qrJJ+meqD6GryBvVzQMmpafv/yF/y5TzxAgPUscNyB7 GGzQ== X-Gm-Message-State: AElRT7HcuWe1X1yokM8DqdRztYLKugNF/N/0gzaLD/iJwiPaHZKju+8I uF1dfc/r4tZvpWTjJ/g2nSM= X-Google-Smtp-Source: AIpwx4+tLKuSXSpb0BMm6POz4rNtTFvVYPWUcdXlVILuJGxzJtktzRwX+e+DU6yxSrdatgjfudR68w== X-Received: by 2002:a17:902:8c8e:: with SMTP id t14-v6mr2917059plo.206.1522227279998; Wed, 28 Mar 2018 01:54:39 -0700 (PDT) Received: from aniruddha-nvidia.nvidia.com ([121.244.166.165]) by smtp.gmail.com with ESMTPSA id i86sm7575613pfi.28.2018.03.28.01.54.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Mar 2018 01:54:39 -0700 (PDT) From: Aniruddha Banerjee To: marc.zyngier@arm.com, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Cc: aniruddhab@nvidia.com, stable@vger.kernel.org, vipink@nvidia.com, strasi@nvidia.com, swarren@nvidia.com, jonathanh@nvidia.com, talho@nvidia.com, treding@nvidia.com, Aniruddha Banerjee Subject: [PATCHv3] irqchip: arm-gic: take gic_lock when updating irq type Date: Wed, 28 Mar 2018 14:24:30 +0530 Message-Id: <20180328085430.3401-1-aniruddha.nitd@gmail.com> X-Mailer: git-send-email 2.16.2 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The kernel documentation states that the locking of the irq-chip registers should be handled by the irq-chip driver. In the irq-gic, the accesses to the irqchip are seemingly not protected and multiple writes to SPIs from different irq descriptors do RMW requests without taking the irq-chip lock. When multiple irqs call the request_irq at the same time, there can be a simultaneous write at the gic distributor, leading to a race. Acquire the gic_lock when the irq_type is updated. Signed-off-by: Aniruddha Banerjee --- Changes from V1: * Moved the spinlock from irq-gic to irq-gic common, so that the fix is valid for GIC v1/v2/v3. Change from V2: * Fixup the Signed-off-by line. drivers/irqchip/irq-gic-common.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c index 9ae71804b5dd..73dd39959e6e 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c @@ -21,6 +21,8 @@ #include "irq-gic-common.h" +static DEFINE_RAW_SPINLOCK(irq_controller_lock); + static const struct gic_kvm_info *gic_kvm_info; const struct gic_kvm_info *gic_get_kvm_info(void) @@ -57,6 +59,7 @@ int gic_configure_irq(unsigned int irq, unsigned int type, * Read current configuration register, and insert the config * for "irq", depending on "type". */ + raw_spin_lock(&irq_controller_lock); val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff); if (type & IRQ_TYPE_LEVEL_MASK) val &= ~confmask; @@ -64,8 +67,10 @@ int gic_configure_irq(unsigned int irq, unsigned int type, val |= confmask; /* If the current configuration is the same, then we are done */ - if (val == oldval) + if (val == oldval) { + raw_spin_unlock(&irq_controller_lock); return 0; + } /* * Write back the new configuration, and possibly re-enable @@ -83,6 +88,7 @@ int gic_configure_irq(unsigned int irq, unsigned int type, pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16); } + raw_spin_unlock(&irq_controller_lock); if (sync_access) sync_access();