From patchwork Mon Jun 19 11:59:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796534 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=J9RTdaqC; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7f24qVmz20XQ for ; Mon, 19 Jun 2023 22:01:30 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7219A8632E; Mon, 19 Jun 2023 14:01:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="J9RTdaqC"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id CBE9786324; Mon, 19 Jun 2023 14:01:19 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9A536862F5 for ; Mon, 19 Jun 2023 14:01:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-31114b46d62so3430248f8f.3 for ; Mon, 19 Jun 2023 05:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176070; x=1689768070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y9/mL7iJTD+lcn28FJElm9dXGWtf3Vxshy85tRJFUko=; b=J9RTdaqCWMIPx+9jiFUffP6MfY5ucmUw78JxWLuNH+Qthz463ecG3fxEnnWV1JlGue L0ort8vJkbm2dm0w4bFOUs9Eymog1dSQHMMmpkEpiwPdym9P6UL1EzqU2PCFf2AquHdA tY5TeJU827EkLLzy0DEG9vCmV9xWSA39j0gUU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176070; x=1689768070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y9/mL7iJTD+lcn28FJElm9dXGWtf3Vxshy85tRJFUko=; b=etCOevnBQDGpwQUrPGQU3pM4LTQrIQW5ySVsHq3nEoFJah7rdrh07+tRF0WBgxh09g m5tEjOjo+RBJOu8X4Bw4PTyLyMaKKbpU5q7Aj5zkItwo7pJ5AVLxqHi9ckHSMT/Tb/9x JzQyzKzXJqfNtbB/CDISgo5Dl05hIKXnytO/q0IFKa3CQoZi8YofoC22qvQ9+xiDEpQ7 nTh5AvwnuZIKRTPmmsC1VpAirmbS1mQIH3e7dokV05lb+4pQeOHkVwU1EqP4nZuTYrUw 7Ih3wNIkECRqARFqnEAENlz1FeKxbHa1dsK6y3LPuJ8TDg8u0b2MqsKboIf9TsFZWowe kkVw== X-Gm-Message-State: AC+VfDyr2V5mT4lKvoRjMbWRlsMCb3j47KaLV+i5l1eQMRtiW9vXvECq LSvltwVViKDHalhaafd8Ijixkuix17wcq31sAn0= X-Google-Smtp-Source: ACHHUZ43hWOsvZ7Npn1iP1yZvuJa+z6nqUKzkz60RcoW0VW/uv9Lc3+UzxxJWOQCPkYtHhil9VShXA== X-Received: by 2002:adf:f552:0:b0:311:1823:5a9f with SMTP id j18-20020adff552000000b0031118235a9fmr8970184wrp.50.1687176069672; Mon, 19 Jun 2023 05:01:09 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:08 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 01/45] x86: Return mtrr_add_request() to its old purpose Date: Mon, 19 Jun 2023 12:59:16 +0100 Message-ID: <20230619120011.1587499-2-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This function used to be for adding a list of requests to be actioned on relocation. Revert it back to this purpose, to avoid problems with boards which need control of their MTRRs (i.e. those which don't use FSP). The mtrr_set_next_var() function is available when the next free variable-MTRR must be set, so this can be used instead. Signed-off-by: Simon Glass Fixes: 3bcd6cf89ef ("x86: mtrr: Skip MSRs that were already programmed..") Fixes: 596bd0589ad ("x86: mtrr: Do not clear the unused ones..") --- Changes in v4: - Bring in dropped mtrr_add_request() request patch Changes in v3: - Fix invalid commit IDs obtained from another branch arch/x86/cpu/mtrr.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index e69dfb552b16..c174dd9b3ad2 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -156,8 +156,12 @@ int mtrr_commit(bool do_caches) debug("open done\n"); qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr); for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) - mtrr_set_next_var(req->type, req->start, req->size); + set_var_mtrr(i, req->type, req->start, req->size); + /* Clear the ones that are unused */ + debug("clear\n"); + for (; i < mtrr_get_var_count(); i++) + wrmsrl(MTRR_PHYS_MASK_MSR(i), 0); debug("close\n"); mtrr_close(&state, do_caches); debug("mtrr done\n"); From patchwork Mon Jun 19 11:59:17 2023 Content-Type: text/plain; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:11 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 02/45] x86: Allow listing MTRRs in SPL Date: Mon, 19 Jun 2023 12:59:17 +0100 Message-ID: <20230619120011.1587499-3-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Move MTRR-listing code into a common file so it can be used from SPL. Update the 'mtrr' command to call it. Use this in SPL just before adjusting the MTRRs, so we can see the state set up by the board. Only show it when debug is enabled. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) arch/x86/cpu/mtrr.c | 61 +++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/mtrr.h | 20 ++++++++++++ arch/x86/lib/spl.c | 7 +++++ cmd/x86/mtrr.c | 60 +++--------------------------------- 4 files changed, 92 insertions(+), 56 deletions(-) diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index c174dd9b3ad2..40d24e6fb9ba 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -30,6 +30,16 @@ DECLARE_GLOBAL_DATA_PTR; +const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { + "Uncacheable", + "Combine", + "2", + "3", + "Through", + "Protect", + "Back", +}; + /* Prepare to adjust MTRRs */ void mtrr_open(struct mtrr_state *state, bool do_caches) { @@ -324,3 +334,54 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask) return mtrr_start_op(cpu_select, &oper); } + +static void read_mtrrs_(void *arg) +{ + struct mtrr_info *info = arg; + + mtrr_read_all(info); +} + +int mtrr_list(int reg_count, int cpu_select) +{ + struct mtrr_info info; + int ret; + int i; + + printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", + "Mask ||", "Size ||"); + memset(&info, '\0', sizeof(info)); + ret = mp_run_on_cpus(cpu_select, read_mtrrs_, &info); + if (ret) + return log_msg_ret("run", ret); + for (i = 0; i < reg_count; i++) { + const char *type = "Invalid"; + u64 base, mask, size; + bool valid; + + base = info.mtrr[i].base; + mask = info.mtrr[i].mask; + size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); + size |= (1 << 12) - 1; + size += 1; + valid = mask & MTRR_PHYS_MASK_VALID; + type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; + printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, + valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK, + mask & ~MTRR_PHYS_MASK_VALID, size); + } + + return 0; +} + +int mtrr_get_type_by_name(const char *typename) +{ + int i; + + for (i = 0; i < MTRR_TYPE_COUNT; i++) { + if (*typename == *mtrr_type_name[i]) + return i; + } + + return -EINVAL; +}; diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index ca2edc7878f7..2e995f540616 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -190,6 +190,26 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask); */ int mtrr_get_var_count(void); +/** + * mtrr_list() - List the MTRRs + * + * Shows a list of all the MTRRs including their values + * + * @reg_count: Number of registers to show. You can use mtrr_get_var_count() for + * this + * @cpu_select: CPU to use. Use MP_SELECT_BSP for the boot CPU + * Returns: 0 if OK, -ve if the CPU was not found + */ +int mtrr_list(int reg_count, int cpu_select); + +/** + * mtrr_get_type_by_name() - Get the type of an MTRR given its type name + * + * @typename: Name to check + * Returns: MTRR type (MTRR_TYPE_...) or -EINVAL if invalid + */ +int mtrr_get_type_by_name(const char *typename); + #endif #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index ca1645f9d687..b9d23e6bfe18 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -139,6 +140,12 @@ static int x86_spl_init(void) arch_setup_gd(gd->new_gd); gd->start_addr_sp = (ulong)ptr; + if (_LOG_DEBUG) { + ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP); + if (ret) + printf("mtrr_list failed\n"); + } + /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */ ret = mtrr_add_request(MTRR_TYPE_WRBACK, (1ULL << 32) - CONFIG_XIP_ROM_SIZE, diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c index b1691d8b65ab..6ad7a123a447 100644 --- a/cmd/x86/mtrr.c +++ b/cmd/x86/mtrr.c @@ -10,71 +10,19 @@ #include #include -static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { - "Uncacheable", - "Combine", - "2", - "3", - "Through", - "Protect", - "Back", -}; - -static void read_mtrrs(void *arg) -{ - struct mtrr_info *info = arg; - - mtrr_read_all(info); -} - -static int do_mtrr_list(int reg_count, int cpu_select) -{ - struct mtrr_info info; - int ret; - int i; - - printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", - "Mask ||", "Size ||"); - memset(&info, '\0', sizeof(info)); - ret = mp_run_on_cpus(cpu_select, read_mtrrs, &info); - if (ret) - return log_msg_ret("run", ret); - for (i = 0; i < reg_count; i++) { - const char *type = "Invalid"; - uint64_t base, mask, size; - bool valid; - - base = info.mtrr[i].base; - mask = info.mtrr[i].mask; - size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); - size |= (1 << 12) - 1; - size += 1; - valid = mask & MTRR_PHYS_MASK_VALID; - type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; - printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, - valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK, - mask & ~MTRR_PHYS_MASK_VALID, size); - } - - return 0; -} - static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[]) { const char *typename = argv[0]; uint32_t start, size; uint64_t base, mask; - int i, type = -1; + int type = -1; bool valid; int ret; if (argc < 3) return CMD_RET_USAGE; - for (i = 0; i < MTRR_TYPE_COUNT; i++) { - if (*typename == *mtrr_type_name[i]) - type = i; - } - if (type == -1) { + type = mtrr_get_type_by_name(typename); + if (type < 0) { printf("Invalid type name %s\n", typename); return CMD_RET_USAGE; } @@ -146,7 +94,7 @@ static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc, if (!first) printf("\n"); printf("CPU %d:\n", i); - ret = do_mtrr_list(reg_count, i); + ret = mtrr_list(reg_count, i); if (ret) { printf("Failed to read CPU %s (err=%d)\n", i < MP_SELECT_ALL ? simple_itoa(i) : "", From patchwork Mon Jun 19 11:59:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796535 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:13 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 03/45] x86: mtrr: Add documentation Date: Mon, 19 Jun 2023 12:59:18 +0100 Message-ID: <20230619120011.1587499-4-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add documention for the x86 'mtrr' command. Signed-off-by: Simon Glass Suggested-by: Heinrich Schuchardt Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Add new patch with docs for mtrr command doc/usage/cmd/mtrr.rst | 151 +++++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + 2 files changed, 152 insertions(+) create mode 100644 doc/usage/cmd/mtrr.rst diff --git a/doc/usage/cmd/mtrr.rst b/doc/usage/cmd/mtrr.rst new file mode 100644 index 000000000000..1b79424112d7 --- /dev/null +++ b/doc/usage/cmd/mtrr.rst @@ -0,0 +1,151 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +mtrr command +============ + +Synopis +------- + + mtrr [list] + mtrr set + mtrr disable + mtrr enable + + +Description +----------- + +The *mtrr* command is used to dump the Memory Type Range Registers (MTRRs) on +an x86 machine. These register control cache behaviour in selected memory +ranges. + +Note that the number of registers can vary between CPUs. + + +mtrr [list] +~~~~~~~~~~~ + +List the MTRRs. The table shows the following information: + +Reg + Register number (the first is register 0) + +Valid + Shows Y if the register is valid (has bit 11 set), N if not + +Write-type + Shows the behaviour when writing to the memory region. The types are + abrievated to fit a reasonable line length. Valid types shown below. + + ====== ============== ==================================================== + Value Type Meaning + ====== ============== ==================================================== + 0 Uncacheable Skip cache and write directly to memory + 1 Combine Multiple writes can be combined into one transaction + 4 Through Update cache and also write to memory + 5 Protect Writes are prohibited + 6 Back Update cache but don't write to memory + ====== ============== ==================================================== + +Base + Base memory address from which the register controls behaviour + +Mask + Mask value, which also indicates the size + +Size + Length of memory region within which the register controls behaviour + + +mtrr set +~~~~~~~~ + +This sets the value of a particular MTRR. Parameters are: + +reg + Register number to set, with 0 being the first + +type + Access type to set. See Write-type above for valid types. This uses the name + rather than its numeric value. + +start + Base memory address from which the register should control behaviour + +size + Length of memory region within which the register controls behaviour + + +mtrr disable +~~~~~~~~~~~~ + +This disables a particular register, by clearing its `valid` bit (11). + + +mtrr enable +~~~~~~~~~~~ + +This enables a particular register, by setting its `valid` bit (11). + + +Example +------- + +This shows disabling and enabling an MTRR, as well as setting its type:: + + => mtrr + CPU 0: + Reg Valid Write-type Base || Mask || Size || + 0 Y Back 0000000000000000 0000000f80000000 0000000080000000 + 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000 + 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000 + 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000 + 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000 + 5 Y Combine 00000000d0000000 0000000ff0000000 0000000010000000 + 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + => mtrr d 5 + => mtrr + CPU 0: + Reg Valid Write-type Base || Mask || Size || + 0 Y Back 0000000000000000 0000000f80000000 0000000080000000 + 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000 + 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000 + 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000 + 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000 + 5 N Combine 00000000d0000000 0000000ff0000000 0000000010000000 + 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + => mtrr e 5 + => mtrr + CPU 0: + Reg Valid Write-type Base || Mask || Size || + 0 Y Back 0000000000000000 0000000f80000000 0000000080000000 + 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000 + 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000 + 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000 + 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000 + 5 Y Combine 00000000d0000000 0000000ff0000000 0000000010000000 + 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + => mtrr set 5 Uncacheable d0000000 10000000 + => mtrr + CPU 0: + Reg Valid Write-type Base || Mask || Size || + 0 Y Back 0000000000000000 0000000f80000000 0000000080000000 + 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000 + 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000 + 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000 + 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000 + 5 Y Uncacheable 00000000d0000000 0000000ff0000000 0000000010000000 + 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + => diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 84ef8a9a427d..f45b3d2bb6ed 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -71,6 +71,7 @@ Shell commands cmd/md cmd/mmc cmd/mtest + cmd/mtrr cmd/panic cmd/part cmd/pause From patchwork Mon Jun 19 11:59:19 2023 Content-Type: text/plain; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:14 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 04/45] bios_emulator: Add Kconfig and adjust Makefile for SPL Date: Mon, 19 Jun 2023 12:59:19 +0100 Message-ID: <20230619125956.v4.4.Ibd4b367f1dea522102a3a0c89b4264c41f1627eb@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The Kconfig for this is currently inside a particular board. Move it into the correct place and allow use in SPL, so that video can be used there if needed. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) board/google/Kconfig | 7 ------- drivers/Kconfig | 2 ++ drivers/Makefile | 2 +- drivers/bios_emulator/Kconfig | 10 ++++++++++ 4 files changed, 13 insertions(+), 8 deletions(-) create mode 100644 drivers/bios_emulator/Kconfig diff --git a/board/google/Kconfig b/board/google/Kconfig index a0f1a6097641..e4f9b5b68aab 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -4,13 +4,6 @@ if VENDOR_GOOGLE -config BIOSEMU - bool - select X86EMU_RAW_IO - -config X86EMU_RAW_IO - bool - choice prompt "Mainboard model" optional diff --git a/drivers/Kconfig b/drivers/Kconfig index 75937fbb6d9b..a25f6ae02fdf 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -10,6 +10,8 @@ source "drivers/ata/Kconfig" source "drivers/axi/Kconfig" +source "drivers/bios_emulator/Kconfig" + source "drivers/bus/Kconfig" source "drivers/block/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 29be78a3f282..c70466dbcbe1 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/ obj-$(CONFIG_$(SPL_TPL_)BLK) += block/ obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ @@ -79,7 +80,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-y += adc/ obj-y += ata/ obj-$(CONFIG_DM_DEMO) += demo/ -obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ obj-y += cache/ obj-$(CONFIG_CPU) += cpu/ diff --git a/drivers/bios_emulator/Kconfig b/drivers/bios_emulator/Kconfig new file mode 100644 index 000000000000..3660576772d1 --- /dev/null +++ b/drivers/bios_emulator/Kconfig @@ -0,0 +1,10 @@ +config BIOSEMU + bool + select X86EMU_RAW_IO + +config SPL_BIOSEMU + bool + select X86EMU_RAW_IO + +config X86EMU_RAW_IO + bool From patchwork Mon Jun 19 11:59:20 2023 Content-Type: text/plain; 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While we are here, add a comment to _X86EMU_env since it the symbol is actually defined twice, which can cause confusion when building. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) drivers/bios_emulator/biosemui.h | 18 +++++++++--------- drivers/bios_emulator/x86emu/sys.c | 1 + include/configs/conga-qeval20-qa3-e3845.h | 2 -- include/configs/dfi-bt700.h | 2 -- include/configs/minnowmax.h | 2 -- include/configs/som-db5800-som-6867.h | 2 -- include/configs/theadorable-x86-common.h | 2 -- include/configs/x86-chromebook.h | 2 -- 8 files changed, 10 insertions(+), 21 deletions(-) diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h index 7853015c1e2e..954cd883158c 100644 --- a/drivers/bios_emulator/biosemui.h +++ b/drivers/bios_emulator/biosemui.h @@ -128,19 +128,19 @@ typedef struct { u32 finalVal; } BE_portInfo; -#define PM_inpb(port) inb(port+VIDEO_IO_OFFSET) -#define PM_inpw(port) inw(port+VIDEO_IO_OFFSET) -#define PM_inpd(port) inl(port+VIDEO_IO_OFFSET) -#define PM_outpb(port,val) outb(val,port+VIDEO_IO_OFFSET) -#define PM_outpw(port,val) outw(val,port+VIDEO_IO_OFFSET) -#define PM_outpd(port,val) outl(val,port+VIDEO_IO_OFFSET) +#define PM_inpb(port) inb(port) +#define PM_inpw(port) inw(port) +#define PM_inpd(port) inl(port) +#define PM_outpb(port, val) outb(val, port) +#define PM_outpw(port, val) outw(val, port) +#define PM_outpd(port, val) outl(val, port) #define LOG_inpb(port) PM_inpb(port) #define LOG_inpw(port) PM_inpw(port) #define LOG_inpd(port) PM_inpd(port) -#define LOG_outpb(port,val) PM_outpb(port,val) -#define LOG_outpw(port,val) PM_outpw(port,val) -#define LOG_outpd(port,val) PM_outpd(port,val) +#define LOG_outpb(port, val) PM_outpb(port, val) +#define LOG_outpw(port, val) PM_outpw(port, val) +#define LOG_outpd(port, val) PM_outpd(port, val) /*-------------------------- Function Prototypes --------------------------*/ diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index c2db1213fe66..882a8a34cc3e 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -44,6 +44,7 @@ /*------------------------- Global Variables ------------------------------*/ +/* Note: bios.c defines this if the emulator is not enabled */ X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ X86EMU_intrFuncs _X86EMU_intrTab[256]; diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index 60617e6fec25..03c364f29fb3 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -16,8 +16,6 @@ "stdout=serial\0" \ "stderr=serial\0" -#define VIDEO_IO_OFFSET 0 - #undef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ "kernel-ver=4.4.0-22\0" \ diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 05389a435bee..be095e28a1b4 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -20,8 +20,6 @@ "stdout=serial\0" \ "stderr=serial\0" -#define VIDEO_IO_OFFSET 0 - #undef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ "kernel-ver=4.4.0-24\0" \ diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 4a12c2f72c62..842672d55751 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -17,6 +17,4 @@ "stderr=vidconsole,serial\0" \ "usb_pgood_delay=40\0" -#define VIDEO_IO_OFFSET 0 - #endif /* __CONFIG_H */ diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h index b2e7aa1514c0..5f7eabd3fc64 100644 --- a/include/configs/som-db5800-som-6867.h +++ b/include/configs/som-db5800-som-6867.h @@ -16,6 +16,4 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#define VIDEO_IO_OFFSET 0 - #endif /* __CONFIG_H */ diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index b23b8783076b..46aef238213a 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -15,8 +15,6 @@ "stdout=serial\0" \ "stderr=serial\0" -#define VIDEO_IO_OFFSET 0 - /* Environment settings */ #undef CFG_EXTRA_ENV_SETTINGS diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 98abb00927ad..6bf90c7de432 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -10,8 +10,6 @@ #define CFG_X86_REFCODE_ADDR 0xffea0000 #define CFG_X86_REFCODE_RUN_ADDR 0 -#define VIDEO_IO_OFFSET 0 - #define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" From patchwork Mon Jun 19 11:59:21 2023 Content-Type: text/plain; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:17 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 06/45] x86: Tidy up EFI code in interrupt_init() Date: Mon, 19 Jun 2023 12:59:21 +0100 Message-ID: <20230619125956.v4.6.Ic4ac1278141c324f8f88c120dc06047f0a1c20fa@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The ll_boot_init() check handles the EFI case so we don't need the rest of the code. Drop it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) arch/x86/cpu/i386/interrupt.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index fae2544c456f..f3f3527237f2 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -266,6 +266,10 @@ int interrupt_init(void) struct udevice *dev; int ret; + /* + * When running as an EFI application we are not in control of + * interrupts and should leave them alone. + */ if (!ll_boot_init()) return 0; @@ -274,11 +278,6 @@ int interrupt_init(void) if (ret && ret != -ENODEV) return ret; - /* - * When running as an EFI application we are not in control of - * interrupts and should leave them alone. - */ -#ifndef CONFIG_EFI_APP /* Just in case... */ disable_interrupts(); @@ -294,14 +293,8 @@ int interrupt_init(void) /* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts(); - /* - * It is now safe to enable interrupts. - * - * TODO(sjg@chromium.org): But we don't handle these correctly when - * booted from EFI. - */ + /* It is now safe to enable interrupts */ enable_interrupts(); -#endif return 0; } From patchwork Mon Jun 19 11:59:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796537 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=Ex1ZAMpK; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7gN14wMz20XQ for ; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:19 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 07/45] x86: Add a comment for board_init_f_r_trampoline() Date: Mon, 19 Jun 2023 12:59:22 +0100 Message-ID: <20230619125956.v4.7.Ib334710a2abe24e384e2f9f01feac0aa1fadd045@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add a comment for this function in the header. Change the function (and the one after) to use __noreturn to keep checkpatch happy. Add docs to board_init_f_r() while we are here. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Add docs to board_init_f_r() too arch/x86/include/asm/u-boot-x86.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 8f38c2d1c601..1d8aa320f535 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -102,8 +102,20 @@ int video_bios_init(void); */ int fsp_save_s3_stack(void); -void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); -void board_init_f_r(void) __attribute__ ((noreturn)); +/** + * board_init_f_r_trampoline() - jump to relocated address with new stack + * + * @sp: New stack pointer to use + */ +void __noreturn board_init_f_r_trampoline(ulong sp); + +/** + * board_init_f_r() - jump to relocated U-Boot + * + * This is used to jump from pre-relocation to post-relocation U-Boot. It + * enables the cache and jump to the new location. + */ +void __noreturn board_init_f_r(void); int arch_misc_init(void); From patchwork Mon Jun 19 11:59:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796541 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=IgSAcHXy; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7hh3tHHz20XQ for ; Mon, 19 Jun 2023 22:03:48 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C37BA86373; Mon, 19 Jun 2023 14:03:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="IgSAcHXy"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BBBD786346; Mon, 19 Jun 2023 14:01:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B30578607D for ; Mon, 19 Jun 2023 14:01:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-311367a3e12so2091489f8f.2 for ; Mon, 19 Jun 2023 05:01:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176081; x=1689768081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LANiLbc0T6ux03TbgrNmO4BQibVM9FUH5IBMTeov4QM=; b=IgSAcHXydPfaCRzz2kmfO/YYY2GZj1six9d+k+jM1ZXdiy4FBVuJAujLN85Y2QrjGO z2dTbKoQcEHvKCyciCoXA5hkQq3J2X1aku679ciuTx6HlXZmZPQBBTkeqLMHC2yb3+LB qxAEr/MfIuHOvIPe3g5E08TphBZVFQY59w7B0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176081; x=1689768081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LANiLbc0T6ux03TbgrNmO4BQibVM9FUH5IBMTeov4QM=; b=fECB9fnY8o1PByvEDYBBqPyrM7Qz4A++LWq5dY4g+cPFrOjWb0O0o2AFGKkfc5E7Ar Nr7shypwJ4w5MgHGvCQYfeT8Us79iMpsyAg9IAOwRC/3n8DNj8dnOP24OBwW0qNjCs6n igmJSobh72T9MhR/kMjwauclZMoFUwszal3FU45w5b6nvPVhOcChTB45IsKKwyW22k0h IRnvayhqAKczH0pjbdI2xLuRDfn1TFevXiTHvtkyjWKEstgPxu60p7U4aQNCeL36H/aB bikNUPNHP+6mp0jj2tiyCUduEftQI12E1PdCDto6Xl51+9rD24uM9h6k3yMnvUbRUM8+ eFjw== X-Gm-Message-State: AC+VfDxuSrpwtePVYLs00WTayY5rXnT9NVH0RbJFV7AWsbh/y0yEBQtX MlvcCN6d7L4A03Dlf2wJdDSbW1WijpPPWg1pGQU= X-Google-Smtp-Source: ACHHUZ4l1JnRbunThbRjssJLS4GBg8vLJ83oZqcvbi6Mm8LVD7orovANqwoQtZEfBHn0Orh4uCyjrg== X-Received: by 2002:a5d:6ad1:0:b0:30a:e69d:7219 with SMTP id u17-20020a5d6ad1000000b0030ae69d7219mr7469676wrw.65.1687176081023; Mon, 19 Jun 2023 05:01:21 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:20 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 08/45] x86: Show the CPU physical address size with bdinfo Date: Mon, 19 Jun 2023 12:59:23 +0100 Message-ID: <20230619125956.v4.8.I39ec1342da17dcd7f20d49cce2e1245672c921b9@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This is useful information so show it with the bdinfo command. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/lib/bdinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c index 15390070fe85..0970efa4726f 100644 --- a/arch/x86/lib/bdinfo.c +++ b/arch/x86/lib/bdinfo.c @@ -22,6 +22,7 @@ void arch_print_bdinfo(void) bdinfo_print_num_l("vendor", gd->arch.x86_vendor); bdinfo_print_str(" name", cpu_vendor_name(gd->arch.x86_vendor)); bdinfo_print_num_l("model", gd->arch.x86_model); + bdinfo_print_num_l("phys_addr", cpu_phys_address_size()); if (IS_ENABLED(CONFIG_EFI_STUB)) efi_show_bdinfo(); From patchwork Mon Jun 19 11:59:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796542 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=NWSljdCq; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7hz6hGnz20XQ for ; Mon, 19 Jun 2023 22:04:03 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 05E328601B; Mon, 19 Jun 2023 14:03:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="NWSljdCq"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BAC8D8628C; Mon, 19 Jun 2023 14:01:50 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EAE1F8545F for ; Mon, 19 Jun 2023 14:01:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-30e3caa6aa7so3348161f8f.1 for ; Mon, 19 Jun 2023 05:01:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176082; x=1689768082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YyspPJDt/PXi2Arx9K65Q9Dq+jk+60VmjW+qAkgIEp4=; b=NWSljdCqpTpyjUILD5PMmfX9QGtTm5sNWl28qG6xGjjc504P4oIBsLid1rFUEWVuAW fT/VXvuz3rFIN6TfixZ+ogD3OmyiG7dpSOuCPVIm7Pt3PHFsY6NkFwIv1mrZPO2jGVy8 LDnPRcGLTqq7H700EVyxfKv2Vl4mDrXuA1tec= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176082; x=1689768082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YyspPJDt/PXi2Arx9K65Q9Dq+jk+60VmjW+qAkgIEp4=; b=i6p+sRKwicuB5z7G8uPyyMm+wc3B2hSgmtzUcsVG1mAyVCDxA4fIfvS84XbJhmf4Js iDIadsF8sLJCS3tFaIr3KtRpwE28QJjxPAHh5nNW+WJF/Tj0noNcq9JLWrNwh9dsiqDb 83Z8Y0ule7YiuKyVUshfSpcIMHDr1WV8p8R7Z/neZrhweIpc4PPZn6XJSJq1GsDxv025 1LTrp9xMnYO1+7oH9UcrBucICATqxJeNFxx4cpy3sQ+/uZLkfny5JKMNXah6/t/dXpW4 XubB+pBslRYgp9yD2QSDLu6qzKo5oSd8ySu2u8QaqW3squIXTHQ4qS8fzYhJv3jDdq5g 4EaQ== X-Gm-Message-State: AC+VfDwazez8FQC6RLHtmHvyu8XChBPW7imXR1luc6Kv3XNuPeZxYzIU kQZoz9cEJLTUEzcVRomDJXPcpgj+ACcLTRQY2fo= X-Google-Smtp-Source: ACHHUZ7u41+nc+zA5CIkOnnxH58MrCEiYiR072OFOdhv8ON/WAUn7uZYRv0JYkm+mY6YZMGML+c4Mg== X-Received: by 2002:a5d:590c:0:b0:30a:8995:1dbc with SMTP id v12-20020a5d590c000000b0030a89951dbcmr6837983wrd.26.1687176082377; Mon, 19 Jun 2023 05:01:22 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:21 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 09/45] x86: Correct get_sp() implementation for 64-bit Date: Mon, 19 Jun 2023 12:59:24 +0100 Message-ID: <20230619125956.v4.9.Idbf1f668608bd458b8a1f17632a61de2ef506702@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Use an assembler implementation as is done for i386, so that the results are equivalent. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 61cb7bc61168..3196f9ddc2c8 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -258,7 +258,7 @@ static ulong get_sp(void) ulong ret; #if CONFIG_IS_ENABLED(X86_64) - ret = gd->start_addr_sp; + asm("mov %%rsp, %0" : "=r"(ret) : ); #else asm("mov %%esp, %0" : "=r"(ret) : ); #endif From patchwork Mon Jun 19 11:59:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796543 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=Do6oUvfg; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7jG4Jtkz20XQ for ; Mon, 19 Jun 2023 22:04:18 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CAEE686366; Mon, 19 Jun 2023 14:03:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Do6oUvfg"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 2819F86343; Mon, 19 Jun 2023 14:01:55 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3757C86306 for ; Mon, 19 Jun 2023 14:01:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f900cd3f69so18534445e9.0 for ; Mon, 19 Jun 2023 05:01:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176083; x=1689768083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xRitOuURQx8bkI7Y83ZUg2M00bLbY6czwK00dg6M9jw=; b=Do6oUvfgdiviZyj89GwnTJXd7u1IV/mJOVaze2LR9aX8pu582azD7U4nbYY7UftJBP tB4oXLhRpOBPea71/cUg1qYIcJ210GvFql5n4peQPkm5r/0lYz3hLXf38qOc5SmiQUHW IBLJnKJrzLTyMuOCBcHv4SgbJrqKaU7KmwzOc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176083; x=1689768083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xRitOuURQx8bkI7Y83ZUg2M00bLbY6czwK00dg6M9jw=; b=K/a+v4P7CnrjXw4JPzGnYPSvQsxoAPucTtfkrFeki3VsCOSGwRta9ZDTAv5kbuVEty 6IHLRu0d+OJ7wU9uC763vfGibPK3XRMBDQSr3D7+sjtg4Ve7T8v4iDjC22C+MW9DuSgG /GBl/OkrNpq5USnsPljWQBxZ9jVtCGKOTBZGKmsnIpFLGX818iCPFD0zmr4FeSxjNu4O GMKqj8eNavpQZNhcxaQbnSzshhAV48bG79MLH8M6Scxdef1FJEln/DmGCf094YTPe/YB 3bUyuUXaFQbajeN8mCYk0upRFq/8UpBthDcj0DgX+DSiJi5wr+LN9SA17KpK2dDmDzzo L51g== X-Gm-Message-State: AC+VfDztJZ8LU/DSIuaqHHSHTILX78JVqHSsVpBwz+MQ4XMDMa93nGil NTBd9NqQG+OGVfnzmqlqOpOxHNag730mM5ZyMms= X-Google-Smtp-Source: ACHHUZ7iKlo9RT/5Bu/vLTmxrVn3H599fSjDemln+uSpXDV5C4jrZe+eZZwwEYyZN5c+9tsrjWsN4g== X-Received: by 2002:a5d:570b:0:b0:309:53f3:6e3e with SMTP id a11-20020a5d570b000000b0030953f36e3emr5330765wrv.69.1687176083498; Mon, 19 Jun 2023 05:01:23 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:22 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 10/45] x86: Show an error when a BIOS exception occurs Date: Mon, 19 Jun 2023 12:59:25 +0100 Message-ID: <20230619125956.v4.10.I76dffbd644a8af409f3be94419ace7ef642d9ee4@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Rather than silently hanging, show an error first. This can happen when there is something wrong with the video BIOS. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Fix BINS typo - Drop the Ooops string arch/x86/lib/bios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 94349ba8073d..8cc686fd146b 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -78,7 +78,7 @@ static int int_exception_handler(void) }; struct eregs *regs = ®_info; - debug("Oops, exception %d while executing option rom\n", regs->vector); + log_err("Exception %d while executing option rom\n", regs->vector); cpu_hlt(); return 0; From patchwork Mon Jun 19 11:59:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796548 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=WbQ/kJZv; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7l64TJrz20XZ for ; Mon, 19 Jun 2023 22:05:54 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 669D0863BA; Mon, 19 Jun 2023 14:04:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="WbQ/kJZv"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D89F78636B; Mon, 19 Jun 2023 14:02:11 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2D27386307 for ; Mon, 19 Jun 2023 14:01:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3113da5260dso877212f8f.2 for ; Mon, 19 Jun 2023 05:01:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176085; x=1689768085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aSyJ9w6YpWNyY0NKAIZ6KKSnbrCa0tkuLwGM1tQoxL4=; b=WbQ/kJZvaWwGK+MLH3/G+QXwUxu1AVeOUf0GorbjjJJuL3g1AppGdrXkZUW3qyAqYk mGCOeqW0WlBfkU5/Byg4AfO+kB1Tv/gMPbwu92FYoMO6YCHA8my4c4dFZz85gjIQI74R rbnEn7EtsrLv2lBUCtGk429LyGLEDRIi3VH6o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176085; x=1689768085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aSyJ9w6YpWNyY0NKAIZ6KKSnbrCa0tkuLwGM1tQoxL4=; b=Q/87nKuWJ+ORuX5ozehliBd+YYLyncitPdnFIUOfan0MOaGwC3d/mMHPTXenD2r59/ GnQxWmgpu0wJYNqExs9Y5PHkQ35BST25WOydiBMSvO+ADgvfh60sOk+Uewlsq7sPgZ3a XzoJwfiCbcc3a3CKgFaErZ52YajI38xDJzVfTST6ZzhoOAo9jugU/Mr9v+HO/7xjDLpn 112hI6Fz5+TOvb4SM7E/VHdr6FPLsbUxr6W8XwT8SmVU2pO8UGyk+byaUKzMctecG4io wvdsjLYS3g85ULsC+01EOzN9p5vu8WeGGowX3To6dEX76B5GkCTpspayc3abDYRU1jV9 F2UA== X-Gm-Message-State: AC+VfDyoRplTnvZo8vh6eA3UjbPMQ5zGZkQsC19KTVg6XtKrniOKUeoG Mr4LcCskoynyFVpA35WhxNMbpK50nVju8zAEtKE= X-Google-Smtp-Source: ACHHUZ7mEp6YeoL14CZGY+ehyWtADzrGJJKzaYFBEFdK/565W69Nh7cvmYMZWkQrRWZKYYqQOZ0DiA== X-Received: by 2002:a5d:534a:0:b0:307:904b:29e1 with SMTP id t10-20020a5d534a000000b00307904b29e1mr6286817wrv.20.1687176085347; Mon, 19 Jun 2023 05:01:25 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:24 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 11/45] acpi: Add a comment to set the acpi tables Date: Mon, 19 Jun 2023 12:59:26 +0100 Message-ID: <20230619125956.v4.11.I5c3b0506bc7def0d7bbae87f7841a7e0107bee35@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Sometimes a previous bootloader has written ACPI tables. It is useful to be able to find and list these. Add an 'acpi set' command to set the address for these tables. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) cmd/acpi.c | 24 +++++++++++++++++++++--- doc/usage/cmd/acpi.rst | 29 +++++++++++++++++++++++++++-- test/dm/acpi.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+), 5 deletions(-) diff --git a/cmd/acpi.c b/cmd/acpi.c index e70913e40bfe..ede9c8c7dcb4 100644 --- a/cmd/acpi.c +++ b/cmd/acpi.c @@ -118,6 +118,22 @@ static int do_acpi_list(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } +static int do_acpi_set(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong val; + + if (argc < 2) { + printf("ACPI pointer: %lx\n", gd_acpi_start()); + } else { + val = hextoul(argv[1], NULL); + printf("Setting ACPI pointer to %lx\n", val); + gd_set_acpi_start(val); + } + + return 0; +} + static int do_acpi_items(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -157,12 +173,14 @@ static int do_acpi_dump(struct cmd_tbl *cmdtp, int flag, int argc, #ifdef CONFIG_SYS_LONGHELP static char acpi_help_text[] = - "list - list ACPI tables\n" - "acpi items [-d] - List/dump each piece of ACPI data from devices\n" - "acpi dump - Dump ACPI table"; + "list - list ACPI tables\n" + "acpi items [-d] - List/dump each piece of ACPI data from devices\n" + "acpi set [] - Set or show address of ACPI tables\n" + "acpi dump - Dump ACPI table"; #endif U_BOOT_CMD_WITH_SUBCMDS(acpi, "ACPI tables", acpi_help_text, U_BOOT_SUBCMD_MKENT(list, 1, 1, do_acpi_list), U_BOOT_SUBCMD_MKENT(items, 2, 1, do_acpi_items), + U_BOOT_SUBCMD_MKENT(set, 2, 1, do_acpi_set), U_BOOT_SUBCMD_MKENT(dump, 2, 1, do_acpi_dump)); diff --git a/doc/usage/cmd/acpi.rst b/doc/usage/cmd/acpi.rst index 14bafc8e3524..5aeb4f4b77bf 100644 --- a/doc/usage/cmd/acpi.rst +++ b/doc/usage/cmd/acpi.rst @@ -11,12 +11,14 @@ Synopis acpi list acpi items [-d] acpi dump + acpi set
Description ----------- -The *acpi* command is used to dump the ACPI tables generated by U-Boot for passing -to the operating systems. +The *acpi* command is used to dump the ACPI tables generated by U-Boot for +passing to the operating systems. It allow allows manually setting the address +to take a look at existing ACPI tables. ACPI tables can be generated by various output functions and even devices can output material to include in the Differentiated System Description Table (DSDT) @@ -231,5 +233,28 @@ Example 00000000: 44 53 44 54 ea 32 00 00 02 eb 55 2d 42 4f 4f 54 DSDT.2....U-BOOT 00000010: 55 2d 42 4f 4f 54 42 4c 25 07 11 20 49 4e 54 4c U-BOOTBL%.. INTL +This shows searching for tables in a known area of memory, then setting the +pointer:: + + => acpi list + No ACPI tables present + => ms.s bff00000 80000 "RSD PTR" + bff75000: 52 53 44 20 50 54 52 20 cf 42 4f 43 48 53 20 00 RSD PTR .BOCHS . + 1 match + => acpi set bff75000 + Setting ACPI pointer to bff75000 + => acpi list + Name Base Size Detail + ---- -------- ----- ------ + RSDP bff75000 0 v00 BOCHS + RSDT bff76a63 38 v01 BOCHS BXPC 1 BXPC 1 + FACP bff768ff 74 v01 BOCHS BXPC 1 BXPC 1 + DSDT bff75080 187f v01 BOCHS BXPC 1 BXPC 1 + FACS bff75040 40 + APIC bff76973 90 v01 BOCHS BXPC 1 BXPC 1 + HPET bff76a03 38 v01 BOCHS BXPC 1 BXPC 1 + WAET bff76a3b 28 v01 BOCHS BXPC 1 BXPC 1 + SSDT bff95040 c5 v02 COREv4 COREBOOT 2a CORE 20221020 + .. _`ACPI specification`: https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 818f71572c7c..77eb524b59f8 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -609,3 +609,41 @@ static int dm_test_acpi_cmd_items(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_cmd_items, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +/* Test 'acpi set' command */ +static int dm_test_acpi_cmd_set(struct unit_test_state *uts) +{ + struct acpi_ctx ctx; + ulong addr; + void *buf; + + gd_set_acpi_start(0); + + console_record_reset(); + ut_asserteq(0, gd_acpi_start()); + ut_assertok(run_command("acpi set", 0)); + ut_assert_nextline("ACPI pointer: 0"); + + buf = memalign(16, BUF_SIZE); + ut_assertnonnull(buf); + addr = map_to_sysmem(buf); + ut_assertok(setup_ctx_and_base_tables(uts, &ctx, addr)); + + ut_assertok(acpi_write_dev_tables(&ctx)); + + ut_assertok(run_command("acpi set", 0)); + ut_assert_nextline("ACPI pointer: %lx", addr); + + ut_assertok(run_command("acpi set 0", 0)); + ut_assert_nextline("Setting ACPI pointer to 0"); + ut_asserteq(0, gd_acpi_start()); + + ut_assertok(run_commandf("acpi set %lx", addr)); + ut_assert_nextline("Setting ACPI pointer to %lx", addr); + ut_asserteq(addr, gd_acpi_start()); + + ut_assert_console_end(); + + return 0; +} +DM_TEST(dm_test_acpi_cmd_set, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); From patchwork Mon Jun 19 11:59:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796544 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=ShoRWy1A; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7jZ5ZdGz20Z9 for ; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:26 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 12/45] bdinfo: Show the RAM top and approximate stack pointer Date: Mon, 19 Jun 2023 12:59:27 +0100 Message-ID: <20230619125956.v4.12.Ib35b8f5950b2eceb28aaf39b527c3463cc5c394f@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean These are useful pieces of information when debugging. The RAM top shows where U-Boot started allocating memory from, before it relocated. The stack pointer can be checked to ensure it is in the correct region. Signed-off-by: Simon Glass Reviewed-by: Nikhil M Jain Tested-by: Nikhil M Jain Reviewed-by: Bin Meng --- (no changes since v1) cmd/Kconfig | 8 ++++++++ cmd/bdinfo.c | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 365371fb511a..a449593c2064 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -135,6 +135,14 @@ config CMD_BDI help Print board info +config CMD_BDINFO_EXTRA + bool "bdinfo extra features" + default y if SANDBOX || X86 + help + Show additional information about the board. This uses a little more + code space but provides more options, particularly those useful for + bringup, development and debugging. + config CMD_CONFIG bool "config" default SANDBOX diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 365357ca545f..4bd21c9ea4b4 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -152,6 +152,11 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) printf("devicetree = %s\n", fdtdec_get_srcname()); } + if (IS_ENABLED(CONFIG_CMD_BDINFO_EXTRA)) { + bdinfo_print_num_ll("stack ptr", (ulong)&bd); + bdinfo_print_num_ll("ram_top ptr", (ulong)gd->ram_top); + } + arch_print_bdinfo(); return 0; From patchwork Mon Jun 19 11:59:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796546 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=fO4ovemY; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7kV0FBRz20XZ for ; Mon, 19 Jun 2023 22:05:22 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2CD6E863AE; Mon, 19 Jun 2023 14:04:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="fO4ovemY"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 35DD98637D; Mon, 19 Jun 2023 14:02:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 655F686337 for ; Mon, 19 Jun 2023 14:01:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f90a1aa204so24214555e9.0 for ; Mon, 19 Jun 2023 05:01:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176089; x=1689768089; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wDheEPzdRxp5nvimkwFGI/mQMtKM01oO4Qt3W4B5OxU=; b=fO4ovemYr89ADBmJHzcOWFwXHZJltlnttaxFOZB6N+WSoNWqDkhWBUjBtNAi1W261B j0RxXz2OukG86LKHrczt3ADAvtJMj9MW+A0C0wN1z9nqbiFgsSaALAmOssVwI+v18y9U nS87KXEwQ/ZgRv4gMbsE+mChNtF/wh5jb4IiU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176089; x=1689768089; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wDheEPzdRxp5nvimkwFGI/mQMtKM01oO4Qt3W4B5OxU=; b=gEsAUnCLg3JyUZ/1ms7A1kak6DYfFgxMA/IajHs5Q0YYAj2WoDRGBd/EY5TTI1LeoE F61Pq4M/c141jNiNi8EN37xN4YwV2yPsg3lepTNbQhf8EO0KouA55VcsRa3ydQSAzZCY ziuJu2/F+Xj3we8znRfNI4jLPhkwgLUmnHY3MjoIKgN1ORaRoxMzI1qL2uKJWOu5TdbW ShTKDBRVnHlmC/kA3qQSzeOJ2pEnJdjgIuAijRf1oZya9/LsV7lceLf8b7BzpthlNOn8 J/MdEWNFOYILOk5YYM7Do4/bfNobZbAaIKHFm5kxF5Wg7TSladDldbHseY8Kyo2+2RnR 1+eA== X-Gm-Message-State: AC+VfDyw+PrLp2JbXMnFoaQHyFOVsIUR8ccaoAXIu4UAfGWWEJSbsjZ0 GNQs69HRl9rVmGbjv0bMlw2eVwlG5ShiP8r+G70= X-Google-Smtp-Source: ACHHUZ7cYfP2l7SNm+IdNWRwgWXnNPK4D09+KHTHtSpkFCwBfxyx3PcUYg26H6J9TN5s832pDF6Jeg== X-Received: by 2002:a5d:65c9:0:b0:311:1120:f2a1 with SMTP id e9-20020a5d65c9000000b003111120f2a1mr8731084wrw.46.1687176089572; Mon, 19 Jun 2023 05:01:29 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:28 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 13/45] part: Allow setting the partition-table type Date: Mon, 19 Jun 2023 12:59:28 +0100 Message-ID: <20230619125956.v4.13.I6e17ea4b4d63a646093f13ef1ff52385b0078bec@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some devices have multiple partition types available on the same media. It is sometimes useful to see these to check that everything is working correctly. Provide a way to manually set the partition-table type, avoiding the auto-detection process. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) cmd/part.c | 34 +++++++++++++++++++ disk/part.c | 16 +++++++++ doc/usage/cmd/part.rst | 74 ++++++++++++++++++++++++++++++++++++++++++ include/part.h | 9 +++++ 4 files changed, 133 insertions(+) diff --git a/cmd/part.c b/cmd/part.c index 28f2b7ff9bbe..0ce190005d32 100644 --- a/cmd/part.c +++ b/cmd/part.c @@ -182,6 +182,36 @@ static int do_part_number(int argc, char *const argv[]) return do_part_info(argc, argv, CMD_PART_INFO_NUMBER); } +static int do_part_set(int argc, char *const argv[]) +{ + const char *devname, *partstr, *typestr; + struct blk_desc *desc; + int dev; + + if (argc < 3) + return CMD_RET_USAGE; + + /* Look up the device */ + devname = argv[0]; + partstr = argv[1]; + typestr = argv[2]; + dev = blk_get_device_by_str(devname, partstr, &desc); + if (dev < 0) { + printf("** Bad device specification %s %s **\n", devname, + partstr); + return CMD_RET_FAILURE; + } + + desc->part_type = part_get_type_by_name(typestr); + if (!desc->part_type) { + printf("Unknown partition type '%s'\n", typestr); + return CMD_RET_FAILURE; + } + part_print(desc); + + return 0; +} + #ifdef CONFIG_PARTITION_TYPE_GUID static int do_part_type(int argc, char *const argv[]) { @@ -245,6 +275,8 @@ static int do_part(struct cmd_tbl *cmdtp, int flag, int argc, return do_part_number(argc - 2, argv + 2); else if (!strcmp(argv[1], "types")) return do_part_types(argc - 2, argv + 2); + else if (!strcmp(argv[1], "set")) + return do_part_set(argc - 2, argv + 2); #ifdef CONFIG_PARTITION_TYPE_GUID else if (!strcmp(argv[1], "type")) return do_part_type(argc - 2, argv + 2); @@ -279,6 +311,8 @@ U_BOOT_CMD( #endif "part type : \n" " - set environment variable to partition type\n" + "part set type\n" + " - set partition type for a device\n" "part types\n" " - list supported partition table types" ); diff --git a/disk/part.c b/disk/part.c index 35300df59039..1d2117ab71ee 100644 --- a/disk/part.c +++ b/disk/part.c @@ -54,6 +54,22 @@ static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc) return NULL; } +int part_get_type_by_name(const char *name) +{ + struct part_driver *drv = + ll_entry_start(struct part_driver, part_driver); + const int n_ents = ll_entry_count(struct part_driver, part_driver); + struct part_driver *entry; + + for (entry = drv; entry != drv + n_ents; entry++) { + if (!strcasecmp(name, entry->name)) + return entry->part_type; + } + + /* Not found */ + return PART_TYPE_UNKNOWN; +} + static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart) { struct blk_desc *dev_desc; diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst index 8d2a2803912d..8a594aaff27e 100644 --- a/doc/usage/cmd/part.rst +++ b/doc/usage/cmd/part.rst @@ -13,6 +13,7 @@ Synopis part start part size part number + part set part type : [varname] part types @@ -82,6 +83,18 @@ part must be specified as partition name. varname a variable to store the current partition number value into +The 'part set' command sets the type of a partition. This is useful when +autodetection fails or does not do the correct thing: + + interface + interface for accessing the block device (mmc, sata, scsi, usb, ....) + dev + device number + part + partition number + type + partition type to use (see 'part types') to check available types + The 'part type' command prints or sets an environment variable to the partition type UUID. interface @@ -147,6 +160,67 @@ Examples => part types Supported partition tables: EFI, AMIGA, DOS, ISO, MAC +This shows looking at a device with multiple partition tables:: + + => virtio scan + => part list virtio 0 + + Partition Map for VirtIO device 0 -- Partition Type: EFI + + Part Start LBA End LBA Name + Attributes + Type GUID + Partition GUID + 1 0x00000040 0x0092b093 "ISO9660" + attrs: 0x1000000000000001 + type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 + guid: a0891d7e-b930-4513-94d8-f629dbd637b2 + 2 0x0092b094 0x0092d7e7 "Appended2" + attrs: 0x0000000000000000 + type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b + guid: a0891d7e-b930-4513-94db-f629dbd637b2 + 3 0x0092d7e8 0x0092da3f "Gap1" + attrs: 0x1000000000000001 + type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 + guid: a0891d7e-b930-4513-94da-f629dbd637b2 + => ls virtio 0:3 + => part types + Supported partition tables: EFI, DOS, ISO + => part set virtio 0 dos + + Partition Map for VirtIO device 0 -- Partition Type: DOS + + Part Start Sector Num Sectors UUID Type + 1 1 9624191 00000000-01 ee + => part set virtio 0 iso + + Partition Map for VirtIO device 0 -- Partition Type: ISO + + Part Start Sect x Size Type + 1 3020 4 512 U-Boot + 2 9613460 10068 512 U-Boot + => part set virtio 0 efi + + Partition Map for VirtIO device 0 -- Partition Type: EFI + + Part Start LBA End LBA Name + Attributes + Type GUID + Partition GUID + 1 0x00000040 0x0092b093 "ISO9660" + attrs: 0x1000000000000001 + type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 + guid: a0891d7e-b930-4513-94d8-f629dbd637b2 + 2 0x0092b094 0x0092d7e7 "Appended2" + attrs: 0x0000000000000000 + type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b + guid: a0891d7e-b930-4513-94db-f629dbd637b2 + 3 0x0092d7e8 0x0092da3f "Gap1" + attrs: 0x1000000000000001 + type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 + guid: a0891d7e-b930-4513-94da-f629dbd637b2 + => + Return value ------------ diff --git a/include/part.h b/include/part.h index be75c7354955..3b1b5398699c 100644 --- a/include/part.h +++ b/include/part.h @@ -598,6 +598,15 @@ static inline struct part_driver *part_driver_get_first(void) return ll_entry_start(struct part_driver, part_driver); } +/** + * part_get_type_by_name() - Get partition type by name + * + * @name: Name of partition type to look up (not case-sensitive) + * Returns: Corresponding partition type (PART_TYPE_...) or PART_TYPE_UNKNOWN if + * not known + */ +int part_get_type_by_name(const char *name); + #else static inline int part_driver_get_count(void) { return 0; } From patchwork Mon Jun 19 11:59:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796545 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=Elf0u0XQ; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:30 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 14/45] qfw: Show the file address if available Date: Mon, 19 Jun 2023 12:59:29 +0100 Message-ID: <20230619125956.v4.14.I32eae3bc14e6961dd375dc4b993c62fa22bd5bf7@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some files have an associated address. Show this with the 'qfw list' command so that it is possible to dump the data. Signed-off-by: Simon Glass --- (no changes since v1) cmd/qfw.c | 2 +- doc/usage/cmd/qfw.rst | 28 ++++++++++++++++------------ 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/cmd/qfw.c b/cmd/qfw.c index ae3c6a7a84e9..d6ecfa60d5a7 100644 --- a/cmd/qfw.c +++ b/cmd/qfw.c @@ -26,7 +26,7 @@ static int qemu_fwcfg_cmd_list_firmware(void) for (file = qfw_file_iter_init(qfw_dev, &iter); !qfw_file_iter_end(&iter); file = qfw_file_iter_next(&iter)) { - printf("%-56s\n", file->cfg.name); + printf("%08lx %-56s\n", file->addr, file->cfg.name); } return 0; diff --git a/doc/usage/cmd/qfw.rst b/doc/usage/cmd/qfw.rst index cc0e27c27790..76d74278a213 100644 --- a/doc/usage/cmd/qfw.rst +++ b/doc/usage/cmd/qfw.rst @@ -11,6 +11,7 @@ Synopsis qfw list qfw cpus qfw load [kernel_addr [initrd_addr]] + qfw list Description ----------- @@ -41,18 +42,21 @@ QEMU firmware files are listed via the *qfw list* command: :: => qfw list - etc/boot-fail-wait - etc/smbios/smbios-tables - etc/smbios/smbios-anchor - etc/e820 - genroms/kvmvapic.bin - genroms/linuxboot.bin - etc/system-states - etc/acpi/tables - etc/table-loader - etc/tpm/log - etc/acpi/rsdp - bootorder + 00000000 bios-geometry + 00000000 bootorder + 000f0060 etc/acpi/rsdp + bed14040 etc/acpi/tables + 00000000 etc/boot-fail-wait + 00000000 etc/e820 + 00000000 etc/smbios/smbios-anchor + 00000000 etc/smbios/smbios-tables + 00000000 etc/system-states + 00000000 etc/table-loader + 00000000 etc/tpm/log + 00000000 genroms/kvmvapic.bin + +Where an address is shown, it indicates where the data is available for +inspection, e.g. using the :doc:`md`. The available CPUs can be shown via the *qfw cpus* command: From patchwork Mon Jun 19 11:59:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796549 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=f/jQjITg; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7lb0W87z20XZ for ; Mon, 19 Jun 2023 22:06:19 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3BF60865AE; Mon, 19 Jun 2023 14:04:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="f/jQjITg"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BFCF686337; Mon, 19 Jun 2023 14:02:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6FB48862ED for ; Mon, 19 Jun 2023 14:01:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3112c11fdc9so1542188f8f.3 for ; Mon, 19 Jun 2023 05:01:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176092; x=1689768092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IJjR5qSa28VvVM5NPFNWU66vPXXE4Wd4PwZZRnW9Nw0=; b=f/jQjITghsquQp0BLvg2VKfNQTsbrSHdbOF71n51RbiJRdhGhyj3lr/xn7ROGE3Brw SbbjIOoRRO+GRnYTYXiXjENoeJocu8am+9cq+78D1PFcsCyJXJq6TNytVGVAPRavc/2X B+D+cKPQX/6YOgYmvs4P8OaqWuI2SKkix66/s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176092; x=1689768092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IJjR5qSa28VvVM5NPFNWU66vPXXE4Wd4PwZZRnW9Nw0=; b=BvS5Z0Sw/ffLCHgTa2xNI3CIy4kuYDVte1RhWFDZXc/eCO499+tnXgG9628W8Rg5WL lLvAW2kcfl/qDBl4tCLMzSPqP0uLK9cRmnnqxuF1I8D42MgREdQJPznl46WLOHRIyIkh sLHkYFcqqcKHYMDkOKPm5ypw5frAgbawznsT+X8iZmXZ+i9UcaO9+VEmf9V3VWae3gki bc9oTrx5iqqBMb4nvHCj3ujuGsxQc4Kc1GPokoDAANRXU0MGHyymVvulm7QL6Yzo6cLm NpJl8l3xiWmVkHhr2qqgyyZoD37cQmYX5RGDzZasL2LxJs/vrn0jeJO0RKzQbZ5vObD/ LBKA== X-Gm-Message-State: AC+VfDzWko8X5iEQZbbeHKKNXi0beppjRL8avQYz/7NO5umMT1diZqHr XwY5n7dCXmjPlE6EeAo4QELTSme3WObnamI6ZKM= X-Google-Smtp-Source: ACHHUZ609r2O/0+qqET4G6Ons/Mg6BfqWx6lPLAlu1JpweiYSPtyoceCXzd84HSNsylJlaLR7NOyNQ== X-Received: by 2002:a5d:470e:0:b0:30a:e8e8:c172 with SMTP id y14-20020a5d470e000000b0030ae8e8c172mr5453968wrq.26.1687176092568; Mon, 19 Jun 2023 05:01:32 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:31 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 15/45] log: Tidy up an ambiguous comment. Date: Mon, 19 Jun 2023 12:59:30 +0100 Message-ID: <20230619125956.v4.15.I85d34b53b3d0b7357458e0a6f85eff95e4b1b26b@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add a a bit more detail so it is clear that multiple devices are supported, but only one per driver. Signed-off-by: Simon Glass --- (no changes since v1) common/log.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/log.c b/common/log.c index 7cfc49bc28a5..ec33b62e8a6f 100644 --- a/common/log.c +++ b/common/log.c @@ -436,7 +436,7 @@ int log_init(void) /* * We cannot add runtime data to the driver since it is likely stored * in rodata. Instead, set up a 'device' corresponding to each driver. - * We only support having a single device. + * We only support having a single device for each driver. */ INIT_LIST_HEAD((struct list_head *)&gd->log_head); while (drv < end) { From patchwork Mon Jun 19 11:59:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796571 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=OqPquwMT; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7wG59Qnz20Wk for ; Mon, 19 Jun 2023 22:13:50 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1A70080F53; Mon, 19 Jun 2023 14:13:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="OqPquwMT"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 828B986093; Mon, 19 Jun 2023 14:02:17 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BC8AA84796 for ; Mon, 19 Jun 2023 14:01:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f906d8fca3so18256515e9.1 for ; Mon, 19 Jun 2023 05:01:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176094; x=1689768094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CicgY1wfRW/NI/OVsiuHRq/kWLObclXp21CRMSPUu3U=; b=OqPquwMTHBK2ccLfBVg06S+cPvHuwlCHP2mb99KGLshLxiF66+DXCul1XS3cxhqfbs vJC9XvSNdavTGmZISTOlbyRRBykhVXLaxpShq+hENlxfGQzKcHIoOetI1RiBxL7IlsV+ hDHz4cNd3/Xk4ZZoQNtrqr4PaZrX9iEyqOOIE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176094; x=1689768094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CicgY1wfRW/NI/OVsiuHRq/kWLObclXp21CRMSPUu3U=; b=NKIELYd2iiJZpRsa98aERXKUjdWQ8X/E1o+Qk/ukQW2gVGrHQF6u3vwcgEHmiEwhkj vJYHiCuKD/L6cUCny5wOjTaPwm3Vf5IWRPsImLqI4Jf0AtfqhincZCUa9+QG/Lk5hB/l Rc2lyGCHwACks+5gRmuSXQ1yZjCEyCNIkoBaqFWY9wCXzxLpZ5xKsbvnyLJld1RwQAI/ VL/lN2+C03e2w67Kr/Bv81+zjmsHKnHx/8SqHP/UtICv2O3ncNXjn9fVFQ8sS4hoTtrM 5YmOyubJcfNZAIWhWj3ve3TcCKauM/vAZVTTX0aXwXAKClWE+fIwdWYQJZD4s6fKfgyz HnIQ== X-Gm-Message-State: AC+VfDytLZutwxD8J1ZHiMRVdagOAi90uL0qNKv5/eh8uvoXM2FuW/9f ZzXCqzj8p5IXe2DN5LhXJZ/u1TK4xiVIyBx0x6Y= X-Google-Smtp-Source: ACHHUZ5qtlDwmHXbJ+0SLyqp9fwRLcJm/VmeENZckZMHbTkDyimDiENRzLT+0F8esCz4QzoHrKtE/A== X-Received: by 2002:a5d:5272:0:b0:30f:c1c3:274a with SMTP id l18-20020a5d5272000000b0030fc1c3274amr6169679wrc.26.1687176094645; Mon, 19 Jun 2023 05:01:34 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:33 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 16/45] qfw: Set the address of the ACPI tables Date: Mon, 19 Jun 2023 12:59:31 +0100 Message-ID: <20230619125956.v4.16.Iaa779cbac7951e7c45f111b8d8324d659104639a@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Once the ACPI tables have been set up, record their address so that it is possible to list them with 'acpi list'. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) drivers/misc/qfw.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index 9ef95caa8956..0a93feeb4b2e 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -18,6 +18,7 @@ #include #include #include +#include #if defined(CONFIG_GENERATE_ACPI_TABLE) && !defined(CONFIG_SANDBOX) /* @@ -227,6 +228,9 @@ out: } free(table_loader); + + gd_set_acpi_start(acpi_get_rsdp_addr()); + return addr; } From patchwork Mon Jun 19 11:59:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796550 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=O7PIfY/0; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7m01dmHz20XZ for ; Mon, 19 Jun 2023 22:06:40 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 150AB8640D; Mon, 19 Jun 2023 14:05:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="O7PIfY/0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5793286342; Mon, 19 Jun 2023 14:02:21 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 14B4786339 for ; Mon, 19 Jun 2023 14:01:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3112f256941so1473279f8f.1 for ; Mon, 19 Jun 2023 05:01:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176096; x=1689768096; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c0FNfF6BmajQwNyQ54QlzMXvnhgfcMqK20wnbR2hh1s=; b=O7PIfY/0SXp0LNN6+gl9FLi32+TYTiAKKTXTyft7OUW2V4dkdo/vctun8etdEEfozy k+HDXhyNFw89rVQ58aXPb9784yWyeGU5djm4haUikdhWAmprH8KbMNu1wMnZBcxCFd9w uQiY6EuGB6XFCskcUQ/AHVeSveXzqtMchr11c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176096; x=1689768096; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c0FNfF6BmajQwNyQ54QlzMXvnhgfcMqK20wnbR2hh1s=; b=dY164ALk9/gKMXbnkAnKJerCWqqsDVff+j8rK5+sHH7FlbflPBszuWj2+ILIGfvVy0 ZZMan15BrLNrHf6NaZ0Ytph23cMcPD7tezldbRyOmB//EgLWpb8x91HDVZFxgaqAquJL IAas6tGxVncK0DCb39kfYlWo0FUXCJdWSnE8cZuopuMzqX5goTcfwfAGRWoiD82cVP0a YieNRjW1UpM9Zhr2LPmE7cO/TCtD0htmd48C/aSFUKdAC2pMmXZOZwSsiMzYJbBgAI9o IicAgr3Gjgex+W4nhBOz4Z1rjtbGLZHMIha/P8YYVtPiMPvQrTPff2jtmY3unXZ+O34A dfeQ== X-Gm-Message-State: AC+VfDzUycwv1OlL0Jyh3zuRJ6Fsz/PBfpelwn/TW8RAT4P7fXz+NO0r GOIIBSWhXdyo4bXdn4mUoXk3v/+Rsv4Zb+X9w9o= X-Google-Smtp-Source: ACHHUZ4P9lTZRANm6lQlu6IHRhYzZ4QusfLlpzAAAEsKizvZR0W69486Zmv/rTBihJomBKhU9yWQsw== X-Received: by 2002:a5d:514c:0:b0:311:3fdc:109d with SMTP id u12-20020a5d514c000000b003113fdc109dmr1280023wrt.1.1687176096505; Mon, 19 Jun 2023 05:01:36 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:35 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 17/45] efi: Show all known UUIDs with CONFIG_CMD_EFIDEBUG Date: Mon, 19 Jun 2023 12:59:32 +0100 Message-ID: <20230619125956.v4.17.I8b1d3f1a3ffca2880596902c87d794f4ea59a53a@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The CMD_EFIDEBUG option enables debugging so it is reasonable to assume that all effects should be made to decode the dreaded UUIDs favoured by UEFI. Update the table to show them all when CONFIG_CMD_EFIDEBUG is enabled. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) lib/uuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/uuid.c b/lib/uuid.c index 96e1af3c8b00..ab30fbf9152f 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -255,7 +255,7 @@ static const struct { EFI_CERT_TYPE_PKCS7_GUID, }, #endif -#ifdef CONFIG_EFI +#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI) { "EFI_LZMA_COMPRESSED", EFI_LZMA_COMPRESSED }, { "EFI_DXE_SERVICES", EFI_DXE_SERVICES }, { "EFI_HOB_LIST", EFI_HOB_LIST }, From patchwork Mon Jun 19 11:59:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796547 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=MaFAt2Db; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7kn5kbVz20XZ for ; Mon, 19 Jun 2023 22:05:37 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E7B1286437; Mon, 19 Jun 2023 14:04:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="MaFAt2Db"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BCD6A86337; Mon, 19 Jun 2023 14:02:25 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EE2698632B for ; Mon, 19 Jun 2023 14:01:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f90b8acefeso13822835e9.0 for ; Mon, 19 Jun 2023 05:01:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176099; x=1689768099; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2+finF1JdN+cd4QAOC93PKsJ7SyBLzPCGLJTOWUTZ6g=; b=MaFAt2DbLYllMLGK5nBxtj9dMpXQsTXSDzL4c8AbtXn6QeV1zfWQcwtc+vDhe1j8EF krZkoCTYEJzi6rQzlyuNlUcncTG5oNQ997EZouDLTQY8pVClQ/EMwp/KVzBObCVZMN1o 6ytxJrsTySp2sFtOMLIg4/kBD94BsJgrxdMb8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176099; x=1689768099; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2+finF1JdN+cd4QAOC93PKsJ7SyBLzPCGLJTOWUTZ6g=; b=gGl9x6cAirGseuv+Q8jPKkUywG5ifW/ilEMz1/nv1adFGA5+5phM0I66VsNgRA1GEE tWSRfgJxZSPCk2mL4ngflEK7Z5QmSh9buVDweEiPcY/sQUmMwQCUuWUxHfxiNCCTgzq4 Qr+BD4V2KedYEGyzQ7y8xIJ8ej90f8voNxT0hKZXoLjZ8szsnGfw00t9RlnewCrCaX5x slOQ3ZSI0LAHFuIFgibCD18b5/1WssUlPZxXRXWWU1Zi7KAqXWWdD+NNQHFK/3eMSkOJ n/WkSZabEQGsw3pWbLFJHeXdZzWFKs+jvJgQgm9NWrdA0NAOPMpa/7AoQcSm3zM/Qtun um1g== X-Gm-Message-State: AC+VfDwTNetH96XQgWOKeMiVV2QyVjx7rcPNr/FpwpPvtSXX2mA6vshR 4yxmLziWJMIdXn8KCn86Yo79XG4hQjmv6qqqVTQ= X-Google-Smtp-Source: ACHHUZ5cUvUYvIVNw4SCi1C+fsX+OptxtnxkbiAohScqxULXbMkO75n39ssr5Amic9b9y/un8pkIng== X-Received: by 2002:a5d:58e5:0:b0:30a:d7a7:3db4 with SMTP id f5-20020a5d58e5000000b0030ad7a73db4mr6405175wrd.12.1687176099161; Mon, 19 Jun 2023 05:01:39 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:37 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 18/45] x86: Improve the trampoline in 64-bit mode Date: Mon, 19 Jun 2023 12:59:33 +0100 Message-ID: <20230619125956.v4.18.Id9b0fb3198dfc1b7aa6ed0380f4b8f77edc473d6@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean At present this leaves the stack at the pre-relocation value. This is not ideal since we want to have U-Boot running entirely from the top of memory. In addition, the new global_data pointer is not actually used, since the global_data pointer itself is relocated, then the pre-relocation value is changed, so the effective value (after relocation) does not update. Adjust the implementation to follow the 32-bit code more closely, with a trampoline function which is passed the new stack and global_data pointer. This ensures that the correct values come through even when relocating. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) arch/x86/cpu/start64.S | 19 +++++++++++++++++++ arch/x86/include/asm/u-boot-x86.h | 11 +++++++++++ common/board_f.c | 12 +++++++----- 3 files changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S index 7be834788b9f..78e894d2a21a 100644 --- a/arch/x86/cpu/start64.S +++ b/arch/x86/cpu/start64.S @@ -26,3 +26,22 @@ _start: /* Should not return here */ jmp . + +.globl board_init_f_r_trampoline64 +.type board_init_f_r_trampoline64, @function +board_init_f_r_trampoline64: + /* + * SDRAM has been initialised, U-Boot code has been copied into + * RAM, BSS has been cleared and relocation adjustments have been + * made. It is now time to jump into the in-RAM copy of U-Boot + * + * %eax = Address of top of new stack + */ + + /* Stack grows down from top of SDRAM */ + movq %rsi, %rsp + + /* New gd is in rdi */ + + /* Re-enter U-Boot by calling board_init_f_r() */ + call board_init_f_r diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 1d8aa320f535..02a8b0f15270 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -117,6 +117,17 @@ void __noreturn board_init_f_r_trampoline(ulong sp); */ void __noreturn board_init_f_r(void); +/* + * board_init_f_r_trampoline64() - jump to relocated address with new stack + * + * This is the 64-bit version + * + * @new_gd: New global_data pointer to use + * @sp: New stack pointer to pass on to board_init_r() + */ +void __noreturn board_init_f_r_trampoline64(struct global_data *new_gd, + ulong sp); + int arch_misc_init(void); /* Read the time stamp counter */ diff --git a/common/board_f.c b/common/board_f.c index 1688e27071fc..abd589c9c996 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -731,8 +731,7 @@ static int fix_fdt(void) #endif /* ARM calls relocate_code from its crt0.S */ -#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ - !CONFIG_IS_ENABLED(X86_64) +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) static int jump_to_copy(void) { @@ -754,7 +753,11 @@ static int jump_to_copy(void) * (CPU cache) */ arch_setup_gd(gd->new_gd); - board_init_f_r_trampoline(gd->start_addr_sp); +# if CONFIG_IS_ENABLED(X86_64) + board_init_f_r_trampoline64(gd->new_gd, gd->start_addr_sp); +# else + board_init_f_r_trampoline(gd->start_addr_sp); +# endif #else relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); #endif @@ -969,8 +972,7 @@ static const init_fnc_t init_sequence_f[] = { * watchdog device is not serviced is as small as possible. */ cyclic_unregister_all, -#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ - !CONFIG_IS_ENABLED(X86_64) +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) jump_to_copy, #endif NULL, From patchwork Mon Jun 19 11:59:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796552 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:39 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 19/45] Show the malloc base with the bdinfo command Date: Mon, 19 Jun 2023 12:59:34 +0100 Message-ID: <20230619125956.v4.19.Ifeceb389ca067768037fa89ba27000a62fe8c64d@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean It is useful to see the base of the malloc region. This is visible when debugging but not in normal usage. Add it to the global data so that it can be shown. Signed-off-by: Simon Glass Reviewed-by: Nikhil M Jain Tested-by: Nikhil M Jain Reviewed-by: Bin Meng --- (no changes since v1) cmd/bdinfo.c | 1 + common/board_r.c | 7 ++++--- include/asm-generic/global_data.h | 13 +++++++++++++ 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 4bd21c9ea4b4..a864f01525fe 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -155,6 +155,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (IS_ENABLED(CONFIG_CMD_BDINFO_EXTRA)) { bdinfo_print_num_ll("stack ptr", (ulong)&bd); bdinfo_print_num_ll("ram_top ptr", (ulong)gd->ram_top); + bdinfo_print_num_l("malloc base", gd_malloc_start()); } arch_print_bdinfo(); diff --git a/common/board_r.c b/common/board_r.c index d798c00a80a5..4aaa89403117 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -196,7 +196,7 @@ static int initr_barrier(void) static int initr_malloc(void) { - ulong malloc_start; + ulong start; #if CONFIG_VAL(SYS_MALLOC_F_LEN) debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr, @@ -207,8 +207,9 @@ static int initr_malloc(void) * This value MUST match the value of gd->start_addr_sp in board_f.c: * reserve_noncached(). */ - malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN; - mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN), + start = gd->relocaddr - TOTAL_MALLOC_LEN; + gd_set_malloc_start(start); + mem_malloc_init((ulong)map_sysmem(start, TOTAL_MALLOC_LEN), TOTAL_MALLOC_LEN); return 0; } diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index a1e1b9d64005..8fc205ded1a3 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -301,6 +301,12 @@ struct global_data { * @timebase_l: low 32 bits of timer */ unsigned int timebase_l; + /** + * @malloc_start: start of malloc() region + */ +#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA) + unsigned long malloc_start; +#endif #if CONFIG_VAL(SYS_MALLOC_F_LEN) /** * @malloc_base: base address of early malloc() @@ -560,6 +566,13 @@ static_assert(sizeof(struct global_data) == GD_SIZE); #define gd_event_state() NULL #endif +#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA) +#define gd_malloc_start() gd->malloc_start +#define gd_set_malloc_start(_val) gd->malloc_start = (_val) +#else +#define gd_malloc_start() 0 +#define gd_set_malloc_start(val) +#endif /** * enum gd_flags - global data flags * From patchwork Mon Jun 19 11:59:35 2023 Content-Type: text/plain; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:41 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 20/45] nvme: Provide more useful debugging messages Date: Mon, 19 Jun 2023 12:59:35 +0100 Message-ID: <20230619125956.v4.20.I60cf14612aa3596f3c00761d66055794f9208995@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When scanning fails it is useful to be able to decode what went wrong. Add some debugging for this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) drivers/nvme/nvme.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 74e7a5b01109..a7add66ab4d1 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -578,17 +578,22 @@ static int nvme_set_queue_count(struct nvme_dev *dev, int count) return min(result & 0xffff, result >> 16) + 1; } -static void nvme_create_io_queues(struct nvme_dev *dev) +static int nvme_create_io_queues(struct nvme_dev *dev) { unsigned int i; + int ret; for (i = dev->queue_count; i <= dev->max_qid; i++) if (!nvme_alloc_queue(dev, i, dev->q_depth)) - break; + return log_msg_ret("all", -ENOMEM); - for (i = dev->online_queues; i <= dev->queue_count - 1; i++) - if (nvme_create_queue(dev->queues[i], i)) - break; + for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { + ret = nvme_create_queue(dev->queues[i], i); + if (ret) + return log_msg_ret("cre", ret); + } + + return 0; } static int nvme_setup_io_queues(struct nvme_dev *dev) @@ -598,14 +603,18 @@ static int nvme_setup_io_queues(struct nvme_dev *dev) nr_io_queues = 1; result = nvme_set_queue_count(dev, nr_io_queues); - if (result <= 0) + if (result <= 0) { + log_debug("Cannot set queue count (err=%dE)\n", result); return result; + } dev->max_qid = nr_io_queues; /* Free previously allocated queues */ nvme_free_queues(dev, nr_io_queues + 1); - nvme_create_io_queues(dev); + result = nvme_create_io_queues(dev); + if (result) + return result; return 0; } @@ -683,8 +692,11 @@ int nvme_scan_namespace(void) uclass_foreach_dev(dev, uc) { ret = device_probe(dev); - if (ret) + if (ret) { + log_err("Failed to probe '%s': err=%dE\n", dev->name, + ret); return ret; + } } return 0; @@ -842,8 +854,10 @@ int nvme_init(struct udevice *udev) ndev->dbs = ((void __iomem *)ndev->bar) + 4096; ret = nvme_configure_admin_queue(ndev); - if (ret) + if (ret) { + log_debug("Unable to configure admin queue (err=%dE)\n", ret); goto free_queue; + } /* Allocate after the page size is known */ ndev->prp_pool = memalign(ndev->page_size, MAX_PRP_POOL); @@ -855,8 +869,10 @@ int nvme_init(struct udevice *udev) ndev->prp_entry_num = MAX_PRP_POOL >> 3; ret = nvme_setup_io_queues(ndev); - if (ret) + if (ret) { + log_debug("Unable to setup I/O queues(err=%dE)\n", ret); goto free_queue; + } nvme_get_info_from_identify(ndev); From patchwork Mon Jun 19 11:59:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796551 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:43 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 21/45] pci: Support autoconfig in SPL Date: Mon, 19 Jun 2023 12:59:36 +0100 Message-ID: <20230619125956.v4.21.If68f4c70b5f796494bcaf317d71cf3a322a412f0@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Allow PCI autoconfig to be handled in SPL, so that we can set it up correctly for boards which need to do this before U-Boot proper. This includes qemu-x64_64 which needs to set up the video device while in 32-bit mode. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) drivers/pci/Kconfig | 8 ++++++++ drivers/pci/pci-uclass.c | 10 +++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 60d98d14640d..56c8362c90ba 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -40,6 +40,14 @@ config PCI_PNP help Enable PCI memory and I/O space resource allocation and assignment. +config SPL_PCI_PNP + bool "Enable Plug & Play support for PCI" + help + Enable PCI memory and I/O space resource allocation and assignment. + This is normally not done in SPL, but can be enabled if devices must + be set up in the SPL phase. Often it is enough to manually configure + one device, so this option can be disabled. + config PCI_REGION_MULTI_ENTRY bool "Enable Multiple entries of region type MEMORY in ranges for PCI" help diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 8d27e40338cf..632c1a63cfce 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -722,6 +723,9 @@ static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor, u32 vendev; int index; + if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(PCI_PNP)) + return true; + for (index = 0; !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index, &vendev); @@ -793,7 +797,9 @@ static int pci_find_and_bind_driver(struct udevice *parent, * space is pretty limited (ie: using Cache As RAM). */ if (!(gd->flags & GD_FLG_RELOC) && - !(drv->flags & DM_FLAG_PRE_RELOC)) + !(drv->flags & DM_FLAG_PRE_RELOC) && + (!CONFIG_IS_ENABLED(PCI_PNP) || + spl_phase() != PHASE_SPL)) return log_msg_ret("pre", -EPERM); /* @@ -918,6 +924,8 @@ int pci_bind_bus_devices(struct udevice *bus) } ret = pci_find_and_bind_driver(bus, &find_id, bdf, &dev); + } else { + debug("device: %s\n", dev->name); } if (ret == -EPERM) continue; From patchwork Mon Jun 19 11:59:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796556 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=khjmQzOW; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7pZ5jsVz20XZ for ; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:45 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 22/45] pci: Allow the video BIOS to work in SPL with QEMU Date: Mon, 19 Jun 2023 12:59:37 +0100 Message-ID: <20230619125956.v4.22.Ia7bae40a2926dca93050f6c11d753d8f219be1ca@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean QEMU emulates two common machines (Q35 and i440fx) which use mapping to determine whether RAM is present below 1MB. In order to copy the video BIOS to c0000 we need to flip this mapping over to RAM. This does not happen automatically until SPL has finished running. Switch in RAM at these address so that the video BIOS can be loaded and run. This fix was found in the seabios code base. Signed-off-by: Simon Glass --- (no changes since v1) drivers/pci/pci_rom.c | 46 +++++++++++++++++++++++++++++++++++++++++++ include/pci_ids.h | 1 + 2 files changed, 47 insertions(+) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index f0dfe6314907..0f44238bbbc8 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -141,6 +141,49 @@ static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp) return 0; } +#define Q35_HOST_BRIDGE_PAM0 0x90 +#define I440FX_PAM0 0x59 + +/** + * intel_set_writable_ram() - Set RAM to be writable + * + * This is needed for QEMU when using Q35 or I440FX emulation, since otherwise + * there is no RAM available at c0000 + * + * See Intel 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet for + * information about the PAM0-PAM6 registers + */ +static void intel_set_writable_ram(void) +{ + struct udevice *dev; + int pam0 = -1; + int i; + + for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) { + const struct pci_child_plat *pdata = dev_get_parent_plat(dev); + + if (pdata->vendor == PCI_VENDOR_ID_INTEL) { + if (pdata->device == PCI_DEVICE_ID_INTEL_Q35_MCH) { + pam0 = Q35_HOST_BRIDGE_PAM0; + break; + } else if (pdata->device == PCI_DEVICE_ID_INTEL_82441) { + pam0 = I440FX_PAM0; + break; + } + } + } + + if (!dev) + return; + + // Adjust RAM to be writable from c0000 to f0000 + for (i = 1; i <= 6; i++) + dm_pci_write_config8(dev, pam0 + i, 0x33); + + // Also f0000-100000 + dm_pci_write_config8(dev, pam0, 0x30); +} + /** * pci_rom_load() - Load a ROM image and return a pointer to it * @@ -185,6 +228,9 @@ static int pci_rom_load(struct pci_rom_header *rom_header, return -ENOMEM; *allocedp = true; #endif + /* QEMU hacks */ + intel_set_writable_ram(); + if (target != rom_header) { ulong start = get_timer(0); diff --git a/include/pci_ids.h b/include/pci_ids.h index 88b0a6404585..856d53264114 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2870,6 +2870,7 @@ #define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916 #define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918 #define PCI_DEVICE_ID_INTEL_ICH9_AHCI 0x2922 +#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 #define PCI_DEVICE_ID_INTEL_I7_MCR 0x2c18 #define PCI_DEVICE_ID_INTEL_I7_MC_TAD 0x2c19 #define PCI_DEVICE_ID_INTEL_I7_MC_RAS 0x2c1a From patchwork Mon Jun 19 11:59:38 2023 Content-Type: text/plain; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:47 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 23/45] pci: Tidy up logging and reporting for video BIOS Date: Mon, 19 Jun 2023 12:59:38 +0100 Message-ID: <20230619125956.v4.23.I45cd86dea07a1d0289d67fd81a4ca9ebd4666220@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When running the ROM the code is not very helpful when something goes wrong. Add a little more debugging and some logging of return values to improve this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) drivers/pci/pci_rom.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 0f44238bbbc8..dab0f1979068 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -300,14 +300,16 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), ret = pci_rom_probe(dev, &rom); if (ret) - return ret; + return log_msg_ret("pro", ret); ret = pci_rom_load(rom, &ram, &alloced); - if (ret) + if (ret) { + ret = log_msg_ret("ld", ret); goto err; + } if (!board_should_run_oprom(dev)) { - ret = -ENXIO; + ret = log_msg_ret("run", -ENXIO); goto err; } @@ -345,21 +347,25 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), #ifdef CONFIG_BIOSEMU BE_VGAInfo *info; + log_debug("Running video BIOS with emulator..."); ret = biosemu_setup(dev, &info); if (ret) goto err; biosemu_set_interrupt_handler(0x15, int15_handler); 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:48 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 24/45] x86: Allow video-BIOS code to be built for SPL Date: Mon, 19 Jun 2023 12:59:39 +0100 Message-ID: <20230619125956.v4.24.I5d7962e5f9d12c176625cd77882e45ababdb590a@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean With qemu-x86_64 we need to run the video BIOS while in 32-bit mode, i.e. SPL. Add a Kconfig option for this, adjust the Makefile rules and use CONFIG_IS_ENABLED() where needed. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) arch/x86/lib/Makefile | 7 ++++--- arch/x86/lib/bios.c | 2 +- drivers/pci/pci_rom.c | 28 ++++++++++++++-------------- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index b0612ae6dd5f..90a7618ecfde 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -4,16 +4,17 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += bdinfo.o -ifndef CONFIG_X86_64 -ifndef CONFIG_TPL_BUILD + +ifndef CONFIG_$(SPL_TPL_)X86_64 obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o endif -endif + ifndef CONFIG_SPL_BUILD obj-$(CONFIG_X86_32BIT_INIT) += string.o endif + ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_BOOTM) += bootm.o endif diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 8cc686fd146b..e29cae78e509 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -23,7 +23,7 @@ static int (*int_handler[256])(void); /* to have a common register file for interrupt handlers */ -#ifndef CONFIG_BIOSEMU +#if !CONFIG_IS_ENABLED(BIOSEMU) X86EMU_sysEnv _X86EMU_env; #endif diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index dab0f1979068..2d9a2a899ef7 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -344,20 +344,20 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), } if (emulate) { -#ifdef CONFIG_BIOSEMU - BE_VGAInfo *info; - - log_debug("Running video BIOS with emulator..."); - ret = biosemu_setup(dev, &info); - if (ret) - goto err; - biosemu_set_interrupt_handler(0x15, int15_handler); - ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, - true, vesa_mode, &mode_info); - log_debug("done\n"); - if (ret) - goto err; -#endif + if (CONFIG_IS_ENABLED(BIOSEMU)) { + BE_VGAInfo *info; + + log_debug("Running video BIOS with emulator..."); + ret = biosemu_setup(dev, &info); + if (ret) + goto err; + biosemu_set_interrupt_handler(0x15, int15_handler); + ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, + true, vesa_mode, &mode_info); + log_debug("done\n"); + if (ret) + goto err; + } } else { #if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL) log_debug("Running video BIOS..."); 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:51 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 25/45] x86: Pass video settings from SPL to U-Boot proper Date: Mon, 19 Jun 2023 12:59:40 +0100 Message-ID: <20230619125956.v4.25.Ieb0824a81d8ad4109fa501c9497b01b8749f913a@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When video is set up in SPL, U-Boot proper needs to use the correct parameters so it can write to the display. Put these in a bloblist so they are available to U-Boot proper. Signed-off-by: Simon Glass Reviewed-by: Nikhil M Jain Reviewed-by: Bin Meng --- (no changes since v3) Changes in v3: - Add a tag name for the blob common/bloblist.c | 1 + drivers/pci/pci_rom.c | 78 +++++++++++++++++++++++++++++++------------ include/bloblist.h | 1 + include/video.h | 24 +++++++++++++ 4 files changed, 83 insertions(+), 21 deletions(-) diff --git a/common/bloblist.c b/common/bloblist.c index 0d63b6e88177..2144b10e1d04 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -51,6 +51,7 @@ static struct tag_name { /* BLOBLISTT_PROJECT_AREA */ { BLOBLISTT_U_BOOT_SPL_HANDOFF, "SPL hand-off" }, + { BLOBLISTT_U_BOOT_VIDEO, "SPL video handoff" }, /* BLOBLISTT_VENDOR_AREA */ }; diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 2d9a2a899ef7..ecb6da64c5c9 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include @@ -34,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -420,34 +422,68 @@ int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void)) printf("Not available (previous bootloader prevents it)\n"); return -EPERM; } - bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); - ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE | - PCI_ROM_ALLOW_FALLBACK); - bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD); - if (ret) { - debug("failed to run video BIOS: %d\n", ret); - return ret; - } - ret = vesa_setup_video_priv(&mode_info.vesa, - mode_info.vesa.phys_base_ptr, uc_priv, - plat); - if (ret) { - if (ret == -ENFILE) { - /* - * See video-uclass.c for how to set up reserved memory - * in your video driver - */ - log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set up no reserved memory\n", - dev->driver->name); + /* In U-Boot proper, collect the information added by SPL (see below) */ + if (IS_ENABLED(CONFIG_SPL_VIDEO) && spl_phase() > PHASE_SPL && + CONFIG_IS_ENABLED(BLOBLIST)) { + struct video_handoff *ho; + + ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho)); + if (!ho) + return log_msg_ret("blf", -ENOENT); + plat->base = ho->fb; + plat->size = ho->size; + uc_priv->xsize = ho->xsize; + uc_priv->ysize = ho->ysize; + uc_priv->line_length = ho->line_length; + uc_priv->bpix = ho->bpix; + } else { + bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); + ret = dm_pci_run_vga_bios(dev, int15_handler, + PCI_ROM_USE_NATIVE | + PCI_ROM_ALLOW_FALLBACK); + bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD); + if (ret) { + debug("failed to run video BIOS: %d\n", ret); + return ret; } - debug("No video mode configured\n"); - return ret; + ret = vesa_setup_video_priv(&mode_info.vesa, + mode_info.vesa.phys_base_ptr, + uc_priv, plat); + if (ret) { + if (ret == -ENFILE) { + /* + * See video-uclass.c for how to set up reserved + * memory in your video driver + */ + log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set up no reserved memory\n", + dev->driver->name); + } + + debug("No video mode configured\n"); + return ret; + } } printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, mode_info.vesa.bits_per_pixel); + /* In SPL, store the information for use by U-Boot proper */ + if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) { + struct video_handoff *ho; + + ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0); + if (!ho) + return log_msg_ret("blc", -ENOMEM); + + ho->fb = plat->base; + ho->size = plat->size; + ho->xsize = uc_priv->xsize; + ho->ysize = uc_priv->ysize; + ho->line_length = uc_priv->line_length; + ho->bpix = uc_priv->bpix; + } + return 0; } diff --git a/include/bloblist.h b/include/bloblist.h index 2a2f1700eb09..7ea72c6bd46d 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -113,6 +113,7 @@ enum bloblist_tag_t { BLOBLISTT_PROJECT_AREA = 0x8000, BLOBLISTT_U_BOOT_SPL_HANDOFF = 0x8000, /* Hand-off info from SPL */ BLOBLISTT_VBE = 0x8001, /* VBE per-phase state */ + BLOBLISTT_U_BOOT_VIDEO = 0x8002, /* Video information from SPL */ /* * Vendor-specific tags are permitted here. Projects can be open source diff --git a/include/video.h b/include/video.h index 03434a81234f..fffaae84e585 100644 --- a/include/video.h +++ b/include/video.h @@ -134,6 +134,30 @@ struct video_ops { #define video_get_ops(dev) ((struct video_ops *)(dev)->driver->ops) +/** + * struct video_handoff - video information passed from SPL + * + * This is used when video is set up by SPL, to provide the details to U-Boot + * proper. + * + * @fb: Base address of frame buffer, 0 if not yet known + * @size: Frame-buffer size, in bytes + * @xsize: Number of pixel columns (e.g. 1366) + * @ysize: Number of pixels rows (e.g.. 768) + * @line_length: Length of each frame buffer line, in bytes. This can be + * set by the driver, but if not, the uclass will set it after + * probing + * @bpix: Encoded bits per pixel (enum video_log2_bpp) + */ +struct video_handoff { + u64 fb; + u32 size; + ushort xsize; + ushort ysize; + u32 line_length; + u8 bpix; +}; + /** enum colour_idx - the 16 colors supported by consoles */ enum colour_idx { VID_BLACK = 0, From patchwork Mon Jun 19 11:59:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796559 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=hPZ41HoM; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7rQ6cdhz20Wk for ; Mon, 19 Jun 2023 22:10:30 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BA490846D9; Mon, 19 Jun 2023 14:07:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="hPZ41HoM"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 47FDC86259; Mon, 19 Jun 2023 14:02:50 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2810486359 for ; Mon, 19 Jun 2023 14:01:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3094910b150so3349976f8f.0 for ; Mon, 19 Jun 2023 05:01:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176114; x=1689768114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1nkGvUab4Rz+yrBUc1k1VSO8jmugOfLL3HZ+i6wNKxM=; b=hPZ41HoMKNwzLt0xGa2STw9cEmKvw0jFiZQO+qD+2b4BxNDkbLeb8koFycXO76vpO8 Cu9PpzmDC7HpefQqUiQ8ycqlsi2S5qmiXRCCLVIBZjRMvFV/w1OHWh+DHgMwkJkCZcc0 r1ikLYIoDnBI0kxGBpc0o6hKsRbndoSDQvG0M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176114; x=1689768114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1nkGvUab4Rz+yrBUc1k1VSO8jmugOfLL3HZ+i6wNKxM=; b=SYLBDoV4ZJgffuBMYXjWNxXWFWfSHUeaJI7P8ks8NeOlYF1c7QLCPua0oryJYghOCf bzv/Zwx0+4gaTnGU1/oIcEy7yCDAZMmr51mps9p+QzCVOw4J+ZWYVYEA8QYkedeofUjg rf9w/q+qPD1qTYvyEw4nPrCkb9ApMNfZLagbQOYlxgpfFAwT8Jz/ev0deLJS4XvZxHni pfi4DmWEQdquDksra7+PaE7V1oJLqGXFpRvxW9dM4EPKlwtXvcmWpER6wHTw86mvZnVc 1uNo/LkUA9/Z7ad6lw8R70NFjlqJ54zufMH/r/+tBPWiWyTRbGEp3iFtontAiKY0aa5Q vV8g== X-Gm-Message-State: AC+VfDxqpFPPk3TEfLCGU9GZzRqyhTwWQjdkoBbzFW1uX1BkbKXGwa8S QbT38HNGIvL4m1sML9rx6o4LMtq3FNoZvjjHrgc= X-Google-Smtp-Source: ACHHUZ5jA7XZ6uFhJquetCiogoQECz4jqQZ3pul3wkiuYnCLuDJ9C0BaQqPelLFFQAoxVmRlcY14aA== X-Received: by 2002:adf:f3d0:0:b0:311:1bd2:de6f with SMTP id g16-20020adff3d0000000b003111bd2de6fmr8240194wrp.12.1687176114460; Mon, 19 Jun 2023 05:01:54 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:01:53 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 26/45] x86: Init video in SPL if enabled Date: Mon, 19 Jun 2023 12:59:41 +0100 Message-ID: <20230619125956.v4.26.I51e48cfd19ef0c0ff56d7d51c52d789b41112378@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When video is required in SPL, set this up ready for use. Ignore any problems since it may be that video is not actually available and we still want to continue on to U-Boot proper in that case. Make sure that the SPL banner is only shown once. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/lib/spl.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index b9d23e6bfe18..8d57f98f6c1f 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -97,7 +98,8 @@ static int x86_spl_init(void) return ret; } #endif - preloader_console_init(); + if (!IS_ENABLED(CONFIG_SPL_BOARD_INIT)) + preloader_console_init(); #if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU) ret = print_cpuinfo(); if (ret) { @@ -257,4 +259,12 @@ void spl_board_init(void) #ifndef CONFIG_TPL preloader_console_init(); #endif + + if (CONFIG_IS_ENABLED(VIDEO)) { + struct udevice *dev; + + /* Set up PCI video in SPL if required */ + uclass_first_device_err(UCLASS_PCI, &dev); + uclass_first_device_err(UCLASS_VIDEO, &dev); + } } From patchwork Mon Jun 19 11:59:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796555 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Drop the 0x prefix, which is not supported in SPL. Signed-off-by: Simon Glass --- (no changes since v1) drivers/pci/pci_rom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index ecb6da64c5c9..62cfe60c0fb2 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -319,7 +319,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), defined(CONFIG_FRAMEBUFFER_VESA_MODE) vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE; #endif - debug("Selected vesa mode %#x\n", vesa_mode); + debug("Selected vesa mode %x\n", vesa_mode); if (exec_method & PCI_ROM_USE_NATIVE) { #ifdef CONFIG_X86 @@ -370,7 +370,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), log_debug("done\n"); #endif } - debug("Final vesa mode %#x\n", mode_info.video_mode); + debug("Final vesa mode %x\n", mode_info.video_mode); ret = 0; err: From patchwork Mon Jun 19 11:59:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796560 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Use the correct address in that case. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) drivers/pci/pci_rom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 62cfe60c0fb2..ba2cf18d53eb 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -93,6 +93,7 @@ static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp) debug("%s: rom_address=%x\n", __func__, rom_address); return -ENOENT; } + rom_address &= PCI_ROM_ADDRESS_MASK; /* Enable expansion ROM address decoding. */ dm_pci_write_config32(dev, PCI_ROM_ADDRESS, From patchwork Mon Jun 19 11:59:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796565 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=KNCdQ1HF; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7t32qtXz20Wk for ; Mon, 19 Jun 2023 22:11:55 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D427E865FF; Mon, 19 Jun 2023 14:08:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="KNCdQ1HF"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7037886330; Mon, 19 Jun 2023 14:03:07 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7764986373 for ; Mon, 19 Jun 2023 14:02:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f9083d8849so26027515e9.0 for ; Mon, 19 Jun 2023 05:02:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176122; x=1689768122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=esUaTEcep/HbF/UVoJtOT3CBAV0JqX/xrSjWy7dmpfU=; b=KNCdQ1HFCdLNUJXc5mE/tjJXk36dKkwB8IirDLYpepTHQ7JWu7J7LuzvqF7Q35M4u0 dcHUM2KQyhBC6wBWkzrcDzxcQ7D2IDQ2z2VyElq+4Qvw4IaLodmtSmTqWLA7oxA25ZPv RoIJxULCLKI1IgqiozsHwUMPyxhN2xNe4AV/8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176122; x=1689768122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=esUaTEcep/HbF/UVoJtOT3CBAV0JqX/xrSjWy7dmpfU=; b=SssaVQivarmgMXE1L6aKmQ9bBamYzzAlma2vkxtnlIROjfleTvVvJCMg35PcXVlnzs 5zHd5SNBwxUnSuk+OPg3eVSdSTS/vyDeN5lfJYAMYzbKGgyzE3U5fXB/R4RDig0ARVa0 G9XPEBUrrC84ZwUrJMnHsVtxxQQMJZ99FvcrQVv24ToijfixtHR6TFQIhenbNNZ8TOY9 nDdeARLRtgDg05VHBSmYm8/TSnEd0J4WKwtU8UCN5tpBHXPiDoS7TdT+mA+kNSsk7g93 fFc/okgf9E/3rCk5h0YxC9lpFOOyXNCHInRSrFUzFdZ6zLSOhAnrI0Wz8kg9Mlo7eNJK dVKQ== X-Gm-Message-State: AC+VfDzOBw6oOnLP14b2LyiKwHfgHcUsJQtupzGsVdan9OP7rUAhf7j9 3JzYJNSy8Y5S2qxY6ctUHWiNjhL78iz19LYefwI= X-Google-Smtp-Source: ACHHUZ6NrkR2YFKJaAErHx2yecv9t7+T2rOJhO3HF6gt9oWogDXUgKE5Js7Looz076Ig66LmIdY88A== X-Received: by 2002:a1c:7c0d:0:b0:3f9:b0cf:be2d with SMTP id x13-20020a1c7c0d000000b003f9b0cfbe2dmr2081944wmc.22.1687176122468; Mon, 19 Jun 2023 05:02:02 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:00 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 29/45] x86: Enable display for QEMU 64-bit Date: Mon, 19 Jun 2023 12:59:44 +0100 Message-ID: <20230619125956.v4.29.I28405fcd995a3bf63b2ad6f650d6fc5210953925@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Enable the various options needed for display to work on the qemu-x86_64 board. This includes expanding the available malloc() memory in SPL, since the PCI bus must be enumerated in order to find the video device. It also includes enabling a bloblist, so that the video parameters can be passed. This is placed at address 10000 but is not needed after U-Boot proper reads the information there. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) configs/qemu-x86_64_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index f29a5aa0f813..371ca9de8429 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -7,6 +7,7 @@ CONFIG_MAX_CPUS=2 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" CONFIG_SPL_TEXT_BASE=0xfffd0000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_X86_RUN_64BIT=y @@ -29,7 +30,10 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_ADDR=0x10000 CONFIG_SPL_NO_BSS_LIMIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_CPU=y CONFIG_SPL_ENV_SUPPORT=y @@ -69,10 +73,12 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y +CONFIG_SPL_PCI_PNP=y CONFIG_SPL_DM_RTC=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y +CONFIG_SPL_VIDEO=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_USER=y CONFIG_FRAMEBUFFER_VESA_MODE=0x144 From patchwork Mon Jun 19 11:59:45 2023 Content-Type: text/plain; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:04 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 30/45] x86: Allow logging to be used in SPL reliably Date: Mon, 19 Jun 2023 12:59:45 +0100 Message-ID: <20230619125956.v4.30.I3ff4f57cec46d4068d7790792b6373bae7c28c0e@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When global_data is relocated, log_head moves in memory, meaning that the items in that list point to the wrong place. Disable logging when making the change, then reenable it afterwards, so that logging works normally. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) arch/x86/lib/spl.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 8d57f98f6c1f..090fa718dbf9 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -139,9 +139,22 @@ static int x86_spl_init(void) */ gd->new_gd = (struct global_data *)ptr; memcpy(gd->new_gd, gd, sizeof(*gd)); + + /* + * Make sure logging is disabled when we switch, since the log system + * list head will move + */ + gd->new_gd->flags &= ~GD_FLG_LOG_READY; arch_setup_gd(gd->new_gd); gd->start_addr_sp = (ulong)ptr; + /* start up logging again, with the new list-head location */ + ret = log_init(); + if (ret) { + log_debug("Log setup failed (err=%d)\n", ret); + return ret; + } + if (_LOG_DEBUG) { ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP); if (ret) From patchwork Mon Jun 19 11:59:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796568 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:06 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass , =?utf-8?q?B?= =?utf-8?q?eno=C3=AEt_Th=C3=A9baudeau?= Subject: [PATCH v4 31/45] fs: fat: Shrink the size of a few strings Date: Mon, 19 Jun 2023 12:59:46 +0100 Message-ID: <20230619125956.v4.31.If2eea014ebc68815d68f373640c80a761a082f83@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean To save a few bytes, replace Error with ** and try to use the same string for multiple messages where possible. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Drop ** in strings and use log_err() for messages fs/fat/fat.c | 20 +++++++++++--------- fs/fat/fat_write.c | 14 ++++---------- 2 files changed, 15 insertions(+), 19 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 2da93dae3cf3..d1476aa433d6 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -8,6 +8,8 @@ * 2003-03-10 - kharris@nexus-tech.net - ported to uboot */ +#define LOG_CATEGORY LOGC_FS + #include #include #include @@ -97,8 +99,8 @@ int fat_register_device(struct blk_desc *dev_desc, int part_no) /* Read the partition table, if present */ if (part_get_info(dev_desc, part_no, &info)) { if (part_no != 0) { - printf("** Partition %d not valid on device %d **\n", - part_no, dev_desc->devnum); + log_err("Partition %d invalid on device %d\n", part_no, + dev_desc->devnum); return -1; } @@ -168,7 +170,7 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry) __u32 ret = 0x00; if (CHECK_CLUST(entry, mydata->fatsize)) { - printf("Error: Invalid FAT entry: 0x%08x\n", entry); + log_err("Invalid FAT entry: %#08x\n", entry); return ret; } @@ -586,19 +588,19 @@ static int get_fs_info(fsdata *mydata) mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0]; mydata->clust_size = bs.cluster_size; if (mydata->sect_size != cur_part_info.blksz) { - printf("Error: FAT sector size mismatch (fs=%hu, dev=%lu)\n", - mydata->sect_size, cur_part_info.blksz); + log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n", + mydata->sect_size, cur_part_info.blksz); return -1; } if (mydata->clust_size == 0) { - printf("Error: FAT cluster size not set\n"); + log_err("FAT cluster size not set\n"); return -1; } if ((unsigned int)mydata->clust_size * mydata->sect_size > MAX_CLUSTSIZE) { - printf("Error: FAT cluster size too big (cs=%u, max=%u)\n", - (unsigned int)mydata->clust_size * mydata->sect_size, - MAX_CLUSTSIZE); + log_err("FAT cluster size too big (cs=%u, max=%u)\n", + (uint)mydata->clust_size * mydata->sect_size, + MAX_CLUSTSIZE); return -1; } diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 413fc432ebed..e2a9913f807a 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -1571,8 +1571,9 @@ int fat_unlink(const char *filename) char *filename_copy, *dirname, *basename; filename_copy = strdup(filename); - if (!filename_copy) { - printf("Error: allocating memory\n"); + itr = malloc_cache_aligned(sizeof(fat_itr)); + if (!itr || !filename_copy) { + printf("Error: out of memory\n"); ret = -ENOMEM; goto exit; } @@ -1584,13 +1585,6 @@ int fat_unlink(const char *filename) goto exit; } - itr = malloc_cache_aligned(sizeof(fat_itr)); - if (!itr) { - printf("Error: allocating memory\n"); - ret = -ENOMEM; - goto exit; - } - ret = fat_itr_root(itr, &fsdata); if (ret) goto exit; @@ -1605,7 +1599,7 @@ int fat_unlink(const char *filename) } if (!find_directory_entry(itr, basename)) { - printf("%s: doesn't exist\n", basename); + log_err("%s: doesn't exist (%d)\n", basename, -ENOENT); ret = -ENOENT; goto exit; } From patchwork Mon Jun 19 11:59:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796569 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:10 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass , =?utf-8?q?B?= =?utf-8?q?eno=C3=AEt_Th=C3=A9baudeau?= Subject: [PATCH v4 32/45] fs: fat: Support reading from a larger block size Date: Mon, 19 Jun 2023 12:59:47 +0100 Message-ID: <20230619125956.v4.32.Ia13846500fab3d5a1d5573db11a040d233994fa6@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean At present it is not possible to read from some CDROM drives since the FAT sector size does not match the media's block size. Add a conversion option for this, so that reading is possible. This does increase SPL size for read-only FAT support by 25 bytes but all but 6 are covered by the previous patch. We could reduce the overhead of this feature to 0 bytes by making the code uglier (using a static variable). Signed-off-by: Simon Glass --- (no changes since v2) Changes in v2: - Use log_warning() for the warning fs/fat/Kconfig | 13 ++++++ fs/fat/fat.c | 107 ++++++++++++++++++++++++++++++++++++++++----- fs/fat/fat_write.c | 8 ++-- 3 files changed, 114 insertions(+), 14 deletions(-) diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig index 9bb11eac9f7a..b0aa888c6cc4 100644 --- a/fs/fat/Kconfig +++ b/fs/fat/Kconfig @@ -22,3 +22,16 @@ config FS_FAT_MAX_CLUSTSIZE is the smallest amount of disk space that can be used to hold a file. Unless you have an extremely tight memory memory constraints, leave the default. + +config FAT_BLK_XLATE + bool "Enable FAT filesystem on a device with a larger block size" + depends on FS_FAT + help + This provides a simple translation mechanism for reading FAT + filesystems which don't use the same sector size as the underlying + media. For example, the FAT filesystem may use 512 bytes but the + media uses 2048, e.g. on a CDROM drive. + + This only supports the case where the FAT filesystem's sector size is + smaller than the media's block size. It does not support creating or + writing files. diff --git a/fs/fat/fat.c b/fs/fat/fat.c index d1476aa433d6..686b321163fb 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -45,13 +45,93 @@ static struct disk_partition cur_part_info; #define DOS_FS_TYPE_OFFSET 0x36 #define DOS_FS32_TYPE_OFFSET 0x52 -static int disk_read(__u32 block, __u32 nr_blocks, void *buf) +/** + * disk_read_conv() - Read blocks and break them into smaller ones + * + * This is used when the FAT filesystem is hosted on a block device with a + * block size greated than 512 bytes, e.g. the 2048 bytes of a CDROM drive. It + * reads the blocks into a buffer and pulls out what is requested by the calling + * function. + * + * It uses an internal 2KB buffer on the stack. + * + * @mydata: Filesystem information + * @block: Block number to read, in terms of mydata->sect_size + * @nr_blocks: Number of blocks to read, in terms of mydata->sect_size + * @buf: Buffer for data + */ +static int disk_read_conv(fsdata *mydata, __u32 block, __u32 nr_blocks, + void *buf) +{ + uint factor, whole, remain, upto; + ulong base, index; + uint to_copy; + u8 tbuf[2048]; + int ret; + + log_debug("mydata %x, cur_dev %lx, block %x, nr_block %x\n", + mydata->sect_size, cur_dev->blksz, block, nr_blocks); + if (mydata->sect_size > cur_dev->blksz || + cur_dev->blksz > sizeof(tbuf)) { + log_err("Block size %lx not supported\n", cur_dev->blksz); + return -EIO; + } + factor = cur_dev->blksz / mydata->sect_size; + + /* get the first partial block */ + base = cur_part_info.start + block / factor; + index = block % factor; + log_debug("cur_part_info.start %llx, block %x, base %lx, index %lx\n", + (unsigned long long)cur_part_info.start, block, base, index); + ret = blk_dread(cur_dev, base, 1, tbuf); + if (ret != 1) + return -EIO; + + to_copy = min((ulong)nr_blocks, factor - index); + log_debug("to_copy %x\n", to_copy); + memcpy(buf, tbuf + index * mydata->sect_size, + to_copy * mydata->sect_size); + upto = to_copy; + + /* load any whole blocks */ + remain = nr_blocks - upto; + whole = remain / factor; + log_debug("factor %x, whole %x, remain %x\n", factor, whole, remain); + if (whole) { + ret = blk_dread(cur_dev, base + 1, whole, + buf + upto * mydata->sect_size); + if (ret != whole) + return -EIO; + upto += whole * factor; + remain = nr_blocks - upto; + } + + /* load any blocks at the end */ + log_debug("end: remain %x\n", remain); + if (remain) { + ret = blk_dread(cur_dev, base + 1 + whole, 1, tbuf); + if (ret != 1) + return -EIO; + memcpy(buf + upto * mydata->sect_size, tbuf, + remain * mydata->sect_size); + upto += remain; + } + + return upto; +} + +static int disk_read(fsdata *mydata, __u32 block, __u32 nr_blocks, void *buf) { ulong ret; if (!cur_dev) return -1; + /* support converting from a larger block size */ + if (IS_ENABLED(CONFIG_FAT_BLK_XLATE) && mydata && + mydata->sect_size != cur_dev->blksz) + return disk_read_conv(mydata, block, nr_blocks, buf); + ret = blk_dread(cur_dev, cur_part_info.start + block, nr_blocks, buf); if (ret != nr_blocks) @@ -68,7 +148,7 @@ int fat_set_blk_dev(struct blk_desc *dev_desc, struct disk_partition *info) cur_part_info = *info; /* Make sure it has a valid FAT header */ - if (disk_read(0, 1, buffer) != 1) { + if (disk_read(NULL, 0, 1, buffer) != 1) { cur_dev = NULL; return -1; } @@ -213,7 +293,7 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry) if (flush_dirty_fat_buffer(mydata) < 0) return -1; - if (disk_read(startblock, getsize, bufptr) < 0) { + if (disk_read(mydata, startblock, getsize, bufptr) < 0) { debug("Error reading FAT blocks\n"); return ret; } @@ -267,7 +347,7 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) debug("FAT: Misaligned buffer address (%p)\n", buffer); while (size >= mydata->sect_size) { - ret = disk_read(startsect++, 1, tmpbuf); + ret = disk_read(mydata, startsect++, 1, tmpbuf); if (ret != 1) { debug("Error reading data (got %d)\n", ret); return -1; @@ -281,7 +361,7 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) __u32 bytes_read; __u32 sect_count = size / mydata->sect_size; - ret = disk_read(startsect, sect_count, buffer); + ret = disk_read(mydata, startsect, sect_count, buffer); if (ret != sect_count) { debug("Error reading data (got %d)\n", ret); return -1; @@ -294,7 +374,7 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) if (size) { ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size); - ret = disk_read(startsect, 1, tmpbuf); + ret = disk_read(mydata, startsect, 1, tmpbuf); if (ret != 1) { debug("Error reading data (got %d)\n", ret); return -1; @@ -506,7 +586,7 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) return -1; } - if (disk_read(0, 1, block) < 0) { + if (disk_read(NULL, 0, 1, block) < 0) { debug("Error: reading block\n"); goto fail; } @@ -588,9 +668,14 @@ static int get_fs_info(fsdata *mydata) mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0]; mydata->clust_size = bs.cluster_size; if (mydata->sect_size != cur_part_info.blksz) { - log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n", - mydata->sect_size, cur_part_info.blksz); - return -1; + if (IS_ENABLED(CONFIG_FAT_BLK_XLATE)) { + log_warning("FAT sector size mismatch (fs=%u, dev=%lu): translating for read-only\n", + mydata->sect_size, cur_part_info.blksz); + } else { + log_err("FAT sector size mismatch (fs=%u, dev=%lu), see CONFIG_FAT_BLK_XLATE\n", + mydata->sect_size, cur_part_info.blksz); + return -1; + } } if (mydata->clust_size == 0) { log_err("FAT cluster size not set\n"); @@ -848,7 +933,7 @@ void *fat_next_cluster(fat_itr *itr, unsigned int *nbytes) * dent at a time and iteratively constructing the vfat long * name. */ - ret = disk_read(sect, read_size, itr->block); + ret = disk_read(itr->fsdata, sect, read_size, itr->block); if (ret < 0) { debug("Error: reading block\n"); return NULL; diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index e2a9913f807a..95f7a60caa2b 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -477,7 +477,7 @@ static int set_fatent_value(fsdata *mydata, __u32 entry, __u32 entry_value) startblock += mydata->fat_sect; - if (disk_read(startblock, getsize, bufptr) < 0) { + if (disk_read(NULL, startblock, getsize, bufptr) < 0) { debug("Error reading FAT blocks\n"); return -1; } @@ -712,7 +712,8 @@ get_set_cluster(fsdata *mydata, __u32 clustnum, loff_t pos, __u8 *buffer, /* partial write at beginning */ if (pos) { wsize = min(bytesperclust - pos, size); - ret = disk_read(startsect, mydata->clust_size, tmpbuf_cluster); + ret = disk_read(NULL, startsect, mydata->clust_size, + tmpbuf_cluster); if (ret != mydata->clust_size) { debug("Error reading data (got %d)\n", ret); return -1; @@ -778,7 +779,8 @@ get_set_cluster(fsdata *mydata, __u32 clustnum, loff_t pos, __u8 *buffer, /* partial write at end */ if (size) { wsize = size; - ret = disk_read(startsect, mydata->clust_size, tmpbuf_cluster); + ret = disk_read(NULL, startsect, mydata->clust_size, + tmpbuf_cluster); if (ret != mydata->clust_size) { debug("Error reading data (got %d)\n", ret); return -1; From patchwork Mon Jun 19 11:59:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796578 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=cxU1wr11; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7yC757Fz20XQ for ; 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Enable some more options, so that all possible EFI UUIDs are decoded, we get a proper printf() in SPL, can search memory for tables, support the full set of standard-boot features, have full logging and can boot from CDROM media. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) configs/qemu-x86_64_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 371ca9de8429..79ea35918575 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -19,6 +19,7 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_X86_OFFSET_U_BOOT=0xfff00000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y CONFIG_SYS_MONITOR_BASE=0x01110000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y @@ -27,6 +28,9 @@ CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_LOG=y +CONFIG_LOGF_FUNC=y +CONFIG_SPL_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y @@ -46,12 +50,14 @@ CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEM_SEARCH=y CONFIG_CMD_IDE=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_QFW=y CONFIG_CMD_BOOTSTAGE=y @@ -83,5 +89,7 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_USER=y CONFIG_FRAMEBUFFER_VESA_MODE=0x144 CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_FAT_BLK_XLATE=y +# CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_GENERATE_ACPI_TABLE=y # CONFIG_GZIP is not set From patchwork Mon Jun 19 11:59:49 2023 Content-Type: text/plain; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:16 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 34/45] x86: Refactor table-writing code a litlle Date: Mon, 19 Jun 2023 12:59:49 +0100 Message-ID: <20230619120011.1587499-5-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The implementation of write_tables() is confusing because it uses the rom_table_start variable as the address pointer as it progresses. Rename it to rom_addr to make the code clearer. Move the rom_table_end variable into the block where it is used. Also update logging to use the ACPI category, now that it is available. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v3) Changes in v3: - Add new patch to refactor table-writing code a ltitle arch/x86/lib/tables.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index ea834a5035f5..132c02ee80f4 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -3,7 +3,7 @@ * Copyright (C) 2015, Bin Meng */ -#define LOG_CATEGORY LOGC_BOARD +#define LOG_CATEGORY LOGC_ACPI #include #include @@ -78,33 +78,33 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad) int write_tables(void) { - u32 rom_table_start; - u32 rom_table_end; u32 high_table, table_size; struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1]; + u32 rom_addr; int i; - rom_table_start = ROM_TABLE_ADDR; + rom_addr = ROM_TABLE_ADDR; - debug("Writing tables to %x:\n", rom_table_start); + debug("Writing tables to %x:\n", rom_addr); for (i = 0; i < ARRAY_SIZE(table_list); i++) { const struct table_info *table = &table_list[i]; int size = table->size ? : CONFIG_ROM_TABLE_SIZE; + u32 rom_table_end; if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) && table->tag) { - rom_table_start = (ulong)bloblist_add(table->tag, size, + rom_addr = (ulong)bloblist_add(table->tag, size, table->align); - if (!rom_table_start) + if (!rom_addr) return log_msg_ret("bloblist", -ENOBUFS); } - rom_table_end = table->write(rom_table_start); + rom_table_end = table->write(rom_addr); if (!rom_table_end) { log_err("Can't create configuration table %d\n", i); return -EINTR; } if (IS_ENABLED(CONFIG_SEABIOS)) { - table_size = rom_table_end - rom_table_start; + table_size = rom_table_end - rom_addr; high_table = (u32)(ulong)high_table_malloc(table_size); if (high_table) { if (!table->write(high_table)) { @@ -123,13 +123,13 @@ int write_tables(void) } debug("- wrote '%s' to %x, end %x\n", table->name, - rom_table_start, rom_table_end); - if (rom_table_end - rom_table_start > size) { + rom_addr, rom_table_end); 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:18 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 35/45] x86: Record the start and end of the tables Date: Mon, 19 Jun 2023 12:59:50 +0100 Message-ID: <20230619125956.v4.35.Ide1869a9d0ecb96f573e5a1a8667450437a3143e@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The ACPI tables are special in that they are passed to EFI as a separate piece, independent of other tables. Also they can be spread over two areas of memory, e.g. with QEMU we end up with tables kept in high memory as well. Add new global_data fields to hold this information and update the bdinfo command to show the table areas. Move the rom_table_end variable into the loop that uses it. Signed-off-by: Simon Glass --- (no changes since v3) Changes in v3: - Adjust the code to handle qemu writing a pointer to tables in memory Changes in v2: - Handle the case where the tables are in the bloblist arch/sandbox/include/asm/global_data.h | 4 ++++ arch/x86/include/asm/global_data.h | 4 ++++ arch/x86/lib/bdinfo.c | 4 ++++ arch/x86/lib/tables.c | 18 +++++++++++++++++- drivers/misc/qfw.c | 8 ++++++++ 5 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index f4ce72d56602..f0ab3ba5c146 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -13,6 +13,10 @@ struct arch_global_data { uint8_t *ram_buf; /* emulated RAM buffer */ void *text_base; /* pointer to base of text region */ + ulong table_start; /* Start address of x86 tables */ + ulong table_end; /* End address of x86 tables */ + ulong table_start_high; /* Start address of high x86 tables */ + ulong table_end_high; /* End address of high x86 tables */ }; #include diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 22d103df4ee8..ea58259ad774 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -123,6 +123,10 @@ struct arch_global_data { #endif void *itss_priv; /* Private ITSS data pointer */ ulong coreboot_table; /* Address of coreboot table */ + ulong table_start; /* Start address of x86 tables */ + ulong table_end; /* End address of x86 tables */ + ulong table_start_high; /* Start address of high x86 tables */ + ulong table_end_high; /* End address of high x86 tables */ }; #endif diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c index 0970efa4726f..9504e7fc293e 100644 --- a/arch/x86/lib/bdinfo.c +++ b/arch/x86/lib/bdinfo.c @@ -23,6 +23,10 @@ void arch_print_bdinfo(void) bdinfo_print_str(" name", cpu_vendor_name(gd->arch.x86_vendor)); bdinfo_print_num_l("model", gd->arch.x86_model); bdinfo_print_num_l("phys_addr", cpu_phys_address_size()); + bdinfo_print_num_l("table start", gd->arch.table_start); + bdinfo_print_num_l("table end", gd->arch.table_end); + bdinfo_print_num_l(" high start", gd->arch.table_start_high); + bdinfo_print_num_l(" high end", gd->arch.table_end_high); if (IS_ENABLED(CONFIG_EFI_STUB)) efi_show_bdinfo(); diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 132c02ee80f4..d95fdb205000 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -54,6 +54,10 @@ static struct table_info table_list[] = { #ifdef CONFIG_GENERATE_MP_TABLE { "mp", write_mp_table, }, #endif + /* + * tables which can go in the bloblist must be last in this list, so + * that the calculation of gd->table_end works properly + */ #ifdef CONFIG_GENERATE_ACPI_TABLE { "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, 0x10000, 0x1000}, #endif @@ -80,10 +84,12 @@ int write_tables(void) { u32 high_table, table_size; struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1]; + bool use_high = false; u32 rom_addr; int i; - rom_addr = ROM_TABLE_ADDR; + gd->arch.table_start = ROM_TABLE_ADDR; + rom_addr = gd->arch.table_start; debug("Writing tables to %x:\n", rom_addr); for (i = 0; i < ARRAY_SIZE(table_list); i++) { @@ -92,10 +98,15 @@ int write_tables(void) u32 rom_table_end; if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) && table->tag) { + if (!gd->arch.table_end) + gd->arch.table_end = rom_addr; rom_addr = (ulong)bloblist_add(table->tag, size, table->align); if (!rom_addr) return log_msg_ret("bloblist", -ENOBUFS); + use_high = true; + if (!gd->arch.table_start_high) + gd->arch.table_start_high = rom_addr; } rom_table_end = table->write(rom_addr); if (!rom_table_end) { @@ -132,6 +143,11 @@ int write_tables(void) rom_addr = rom_table_end; } + if (use_high) + gd->arch.table_end_high = rom_addr; + else + gd->arch.table_end = rom_addr; + if (IS_ENABLED(CONFIG_SEABIOS)) { /* make sure the last item is zero */ cfg_tables[i].size = 0; diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index 0a93feeb4b2e..c0da4bd7359e 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -65,6 +65,11 @@ static int bios_linker_allocate(struct udevice *dev, printf("error: allocating resource\n"); return -ENOMEM; } + if (aligned_addr < gd->arch.table_start_high) + gd->arch.table_start_high = aligned_addr; + if (aligned_addr + size > gd->arch.table_end_high) + gd->arch.table_end_high = aligned_addr + size; + } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) { aligned_addr = ALIGN(*addr, align); } else { @@ -189,6 +194,9 @@ ulong write_acpi_tables(ulong addr) return addr; } + gd->arch.table_start_high = (ulong)table_loader; + gd->arch.table_end_high = (ulong)table_loader; + qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size, table_loader); for (i = 0; i < (size / sizeof(*entry)); i++) { From patchwork Mon Jun 19 11:59:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796562 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:20 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 36/45] x86: Show the number of physical address bits Date: Mon, 19 Jun 2023 12:59:51 +0100 Message-ID: <20230619120011.1587499-6-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add this information to global_data and show it with the 'bdinfo' command. For now we use CONFIG_CPU_ADDR_BITS to control the number of bits, but this could change if needed. Signed-off-by: Simon Glass --- (no changes since v2) Changes in v2: - Add new patch to show the number of physical address bits arch/x86/cpu/i386/cpu.c | 2 ++ arch/x86/include/asm/global_data.h | 1 + arch/x86/lib/bdinfo.c | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 91cd5d7c9e40..5c17d279092e 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -468,6 +468,7 @@ int x86_cpu_init_f(void) if (ll_boot_init()) setup_cpu_features(); setup_identity(); + gd->arch.phys_bits = cpu_phys_address_size(); setup_mtrr(); setup_pci_ram_top(); @@ -483,6 +484,7 @@ int x86_cpu_reinit_f(void) long addr; setup_identity(); + gd->arch.phys_bits = cpu_phys_address_size(); setup_pci_ram_top(); addr = locate_coreboot_table(); if (addr >= 0) { diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index ea58259ad774..5b802f79d502 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -127,6 +127,7 @@ struct arch_global_data { ulong table_end; /* End address of x86 tables */ ulong table_start_high; /* Start address of high x86 tables */ ulong table_end_high; /* End address of high x86 tables */ + uint phys_bits; /* Number of physical address bits */ }; #endif diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c index 9504e7fc293e..c5fda22679ad 100644 --- a/arch/x86/lib/bdinfo.c +++ b/arch/x86/lib/bdinfo.c @@ -27,6 +27,7 @@ void arch_print_bdinfo(void) bdinfo_print_num_l("table end", gd->arch.table_end); bdinfo_print_num_l(" high start", gd->arch.table_start_high); bdinfo_print_num_l(" high end", gd->arch.table_end_high); + bdinfo_print_num_l("phys bits", gd->arch.phys_bits); if (IS_ENABLED(CONFIG_EFI_STUB)) efi_show_bdinfo(); From patchwork Mon Jun 19 11:59:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796564 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:22 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 37/45] x86: Convert some debug statements to use logging Date: Mon, 19 Jun 2023 12:59:52 +0100 Message-ID: <20230619120011.1587499-7-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Move from using debug() to log_debug() so that we don't have to use the __func__ parameter and can access other logging features. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Add new patch to convert some debug statements to use logging arch/x86/cpu/intel_common/mrc.c | 10 +++++----- arch/x86/cpu/ivybridge/sdram.c | 4 +++- arch/x86/lib/mrccache.c | 6 ++++-- arch/x86/lib/spl.c | 22 ++++++++++++++-------- drivers/gpio/intel_ich6_gpio.c | 5 +++-- drivers/pch/pch9.c | 6 ++++-- 6 files changed, 33 insertions(+), 20 deletions(-) diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index 69405d740b47..2819bae02e3c 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -3,6 +3,8 @@ * Copyright (c) 2016 Google, Inc */ +#define LOG_CATEGORY UCLASS_RAM + #include #include #include @@ -144,12 +146,10 @@ int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap) ret = gpio_request_list_by_name(dev, "board-id-gpios", desc, ARRAY_SIZE(desc), GPIOD_IS_IN); - if (ret < 0) { - debug("%s: gpio ret=%d\n", __func__, ret); - return ret; - } + if (ret < 0) + return log_msg_ret("gp", ret); spd_index = dm_gpio_get_values_as_int(desc, ret); - debug("spd index %d\n", spd_index); + log_debug("spd index %d\n", spd_index); node = fdt_first_subnode(blob, dev_of_offset(dev)); if (node < 0) diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 1a0ec433e654..0718aefbb1fe 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -9,6 +9,8 @@ * Copyright (C) 2011 Google Inc. */ +#define LOG_CATEGORY UCLASS_RAM + #include #include #include @@ -213,7 +215,7 @@ static int copy_spd(struct udevice *dev, struct pei_data *peid) ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data); if (ret) { - debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret); + log_debug("Could not locate SPD (err=%d)\n", ret); return ret; } diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 2f6f6880003e..6494b8d26341 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -6,6 +6,8 @@ * Copyright (C) 2015 Bin Meng */ +#define LOG_CATEGORY UCLASS_RAM + #include #include #include @@ -197,8 +199,8 @@ static void mrccache_setup(struct mrc_output *mrc, void *data) cache->signature = MRC_DATA_SIGNATURE; cache->data_size = mrc->len; checksum = compute_ip_checksum(mrc->buf, cache->data_size); - debug("Saving %d bytes for MRC output data, checksum %04x\n", - cache->data_size, checksum); + log_debug("Saving %d bytes for MRC output data, checksum %04x\n", + cache->data_size, checksum); cache->checksum = checksum; cache->reserved = 0; memcpy(cache->data, mrc->buf, cache->data_size); diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 090fa718dbf9..6886587f647f 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -3,6 +3,8 @@ * Copyright (c) 2016 Google, Inc */ +#define LOG_CATEGORY LOGC_BOOT + #include #include #include @@ -76,25 +78,25 @@ static int x86_spl_init(void) #endif int ret; - debug("%s starting\n", __func__); + log_debug("x86 spl starting\n"); if (IS_ENABLED(TPL)) ret = x86_cpu_reinit_f(); else ret = x86_cpu_init_f(); ret = spl_init(); if (ret) { - debug("%s: spl_init() failed\n", __func__); + log_debug("spl_init() failed (err=%d)\n", ret); return ret; } ret = arch_cpu_init(); if (ret) { - debug("%s: arch_cpu_init() failed\n", __func__); + log_debug("arch_cpu_init() failed (err=%d)\n", ret); return ret; } #ifndef CONFIG_TPL ret = fsp_setup_pinctrl(NULL, NULL); if (ret) { - debug("%s: fsp_setup_pinctrl() failed\n", __func__); + log_debug("fsp_setup_pinctrl() failed (err=%d)\n", ret); return ret; } #endif @@ -103,23 +105,25 @@ static int x86_spl_init(void) #if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU) ret = print_cpuinfo(); if (ret) { - debug("%s: print_cpuinfo() failed\n", __func__); + log_debug("print_cpuinfo() failed (err=%d)\n", ret); return ret; } #endif ret = dram_init(); if (ret) { - debug("%s: dram_init() failed\n", __func__); + log_debug("dram_init() failed (err=%d)\n", ret); return ret; } + log_debug("mrc\n"); if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { ret = mrccache_spl_save(); if (ret) - debug("%s: Failed to write to mrccache (err=%d)\n", - __func__, ret); + log_debug("Failed to write to mrccache (err=%d)\n", + ret); } #ifndef CONFIG_SYS_COREBOOT + log_debug("bss\n"); debug("BSS clear from %lx to %lx len %lx\n", (ulong)&__bss_start, (ulong)&__bss_end, (ulong)&__bss_end - (ulong)&__bss_start); memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start); @@ -140,6 +144,7 @@ static int x86_spl_init(void) gd->new_gd = (struct global_data *)ptr; memcpy(gd->new_gd, gd, sizeof(*gd)); + log_debug("logging\n"); /* * Make sure logging is disabled when we switch, since the log system * list head will move @@ -179,6 +184,7 @@ static int x86_spl_init(void) debug("Failed to set CPU frequency (err=%d)\n", ret); # endif #endif + log_debug("done\n"); return 0; } diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 63a07b9592a0..2ed0d0bea9a5 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -26,6 +26,8 @@ * reserved or subject to arcane restrictions. */ +#define LOG_CATEGORY UCLASS_GPIO + #include #include #include @@ -155,8 +157,7 @@ static int ich6_gpio_request(struct udevice *dev, unsigned offset, */ tmplong = inl(bank->use_sel); if (!(tmplong & (1UL << offset))) { - debug("%s: gpio %d is reserved for internal use\n", __func__, - offset); + log_debug("gpio %d is reserved for internal use\n", offset); return -EPERM; } diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c index 3bd011518b3a..3137eb2c28f5 100644 --- a/drivers/pch/pch9.c +++ b/drivers/pch/pch9.c @@ -3,6 +3,8 @@ * Copyright (C) 2014 Google, Inc */ +#define LOG_CATEGORY UCLASS_PCH + #include #include #include @@ -38,7 +40,7 @@ static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep) */ dm_pci_read_config32(dev, GPIO_BASE, &base); if (base == 0x00000000 || base == 0xffffffff) { - debug("%s: unexpected BASE value\n", __func__); + log_debug("unexpected BASE value\n"); return -ENODEV; } @@ -59,7 +61,7 @@ static int pch9_get_io_base(struct udevice *dev, u32 *iobasep) dm_pci_read_config32(dev, IO_BASE, &base); if (base == 0x00000000 || base == 0xffffffff) { - debug("%s: unexpected BASE value\n", __func__); + log_debug("unexpected BASE value\n"); return -ENODEV; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:24 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 38/45] x86: link: Support Micron memory Date: Mon, 19 Jun 2023 12:59:53 +0100 Message-ID: <20230619120011.1587499-8-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add the required tag so that micron memory can be set up correctly. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Add new patch to support Micron memory arch/x86/dts/chromebook_link.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 36956f40bd70..c904b7d0b69d 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -314,6 +314,7 @@ 00 00 00 00 00 00 00 00]; }; micron_4Gb_1600_1.35v_x16 { + bootph-all; reg = <2>; data = [92 11 0b 03 04 19 02 02 03 11 01 08 0a 00 fe 00 From patchwork Mon Jun 19 11:59:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796561 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=FGwxG9bN; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7rx26kTz20Wk for ; Mon, 19 Jun 2023 22:10:57 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5C587865EA; Mon, 19 Jun 2023 14:08:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="FGwxG9bN"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 34A3D86093; Mon, 19 Jun 2023 14:03:50 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9CF6D86342 for ; Mon, 19 Jun 2023 14:02:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3111547c8f9so3970871f8f.1 for ; Mon, 19 Jun 2023 05:02:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176146; x=1689768146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bte5sNmJ8S+Rfq0Zv0eLJwu7pOkAHf4JfigaEaJPWr8=; b=FGwxG9bNRvxLPkMdw/l4p1VDhsJns2IGg4gb24zhcEcTx0N85ij9rVWL9VYlH7EctP ZQxg/l6aqxz/XM0O47bmlycFnT6nVOaX14PhZB3HzhEL+UmBPTo4Rjzze6/42DzmP3ni T3o08u2AWEB3cMhp6wRntSdRCWbCZriI5znG0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176146; x=1689768146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bte5sNmJ8S+Rfq0Zv0eLJwu7pOkAHf4JfigaEaJPWr8=; b=draMWwcBT1n92RVYI+lAvVnEnksLMvPK1E/d74a2bH88TPwPpHiE2kV56cSIC+NU3+ Jer5p/xO2YNsY4EOXiytYWVACF7kCMoBGlJ/iZ3XVnMepgdPz0lKjg90SXCql8pQ8KBt +GcNCS2aISRMUM5lIKjE57x9YwhZ9dO+Z5FakmISzl/sqxCPgQCZtAaecZt53NLUIcxo H405ABTGBC4O99BDTMF+TY0ygx55hCo5x14UATYDsldgepGkGl3jeAySzD1qpkhaL0UG HvXD8IziFnZOatoBu2B3CG+ItpJGmYxxdJEJKU4gwaUmAa3JHBcKAj/kM5gYtyINcxJi EBKg== X-Gm-Message-State: AC+VfDyWYwZPDimDpN8DNNZmWUgudxu0eI6muO1Rpz1gG85JqDgCt9WV 8ESyIjsRys8Mmm+gbjID9ltvUgrdb+5//dmkW6A= X-Google-Smtp-Source: ACHHUZ6V3Pz4+KyZWReIN9tAN3AZ4pqCeAF6xR7oBVQS4atDo95JnsawpjKFkkLRWkxP4tTI1GFCAA== X-Received: by 2002:adf:e708:0:b0:311:91c:ddfc with SMTP id c8-20020adfe708000000b00311091cddfcmr8483679wrm.10.1687176145893; Mon, 19 Jun 2023 05:02:25 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:25 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 39/45] x86: Make sure that the LPC is active before SDRAM init Date: Mon, 19 Jun 2023 12:59:54 +0100 Message-ID: <20230619120011.1587499-9-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some boards need to access GPIOs to determine which SDRAM is fitted to the board, for example chromebook_link. Probe this device (if it exists) to make sure that this works as expected. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Add new patch to make sure that the LPC is active before SDRAM init arch/x86/lib/spl.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 6886587f647f..fb7dac68d7aa 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -65,6 +65,8 @@ static int set_max_freq(void) static int x86_spl_init(void) { + struct udevice *dev; + #ifndef CONFIG_TPL /* * TODO(sjg@chromium.org): We use this area of RAM for the stack @@ -109,6 +111,13 @@ static int x86_spl_init(void) return ret; } #endif + /* probe the LPC so we get the GPIO_BASE set up correctly */ + ret = uclass_first_device_err(UCLASS_LPC, &dev); + if (ret && ret != -ENODEV) { + log_debug("lpc probe failed\n"); + return ret; + } + ret = dram_init(); if (ret) { log_debug("dram_init() failed (err=%d)\n", ret); From patchwork Mon Jun 19 11:59:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796574 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:26 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 40/45] log: Support outputing function names in SPL Date: Mon, 19 Jun 2023 12:59:55 +0100 Message-ID: <20230619120011.1587499-10-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The output is garbled when tiny printf() is used. Correct this by adding a special case. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Add new patch to support outputing function names in SPL common/log_console.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/common/log_console.c b/common/log_console.c index f1dcc04b97c9..bb091ce21a4a 100644 --- a/common/log_console.c +++ b/common/log_console.c @@ -37,8 +37,14 @@ static int log_console_emit(struct log_device *ldev, struct log_rec *rec) printf("%s:", rec->file); if (fmt & BIT(LOGF_LINE)) printf("%d-", rec->line); - if (fmt & BIT(LOGF_FUNC)) - printf("%*s()", CONFIG_LOGF_FUNC_PAD, rec->func); + if (fmt & BIT(LOGF_FUNC)) { + if (CONFIG_IS_ENABLED(USE_TINY_PRINTF)) { + printf("%s()", rec->func); + } else { + printf("%*s()", CONFIG_LOGF_FUNC_PAD, + rec->func); + } + } } if (fmt & BIT(LOGF_MSG)) printf("%s%s", add_space ? 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:27 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 41/45] sandbox: Correct header order in board file Date: Mon, 19 Jun 2023 12:59:56 +0100 Message-ID: <20230619125956.v4.41.If98bd1d7175ba37c571b3da11e278462397e2421@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Fix the header order in this file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) board/sandbox/sandbox.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index c7b6cb78fff5..54c119daeeeb 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -11,16 +11,16 @@ #include #include #include +#include #include #include +#include #include #include #include #include #include -#include - -#include +#include /* * Pointer to initial global data area From patchwork Mon Jun 19 11:59:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1796575 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=E2wiNdJh; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ql7xM4vJkz20Wk for ; Mon, 19 Jun 2023 22:14:47 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9CE4385362; Mon, 19 Jun 2023 14:14:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="E2wiNdJh"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AFDB886342; Mon, 19 Jun 2023 14:04:04 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 17A0186351 for ; Mon, 19 Jun 2023 14:02:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f901f87195so15459125e9.1 for ; Mon, 19 Jun 2023 05:02:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1687176149; x=1689768149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UT18RyYaD/6dZxd27WniDZx87FajBAvs3hPdy2nwZV0=; b=E2wiNdJhSISF2161Loovr5BEMh8Nh3ZHxw4TuFHN6Fllb+u0cdRTVoP5pA9z5z3chx 1HnGRy1LLzebmlvyw1ygXXPw7DRiqthv3U+RbcHHlpofld2DvWI1lg2ujk1drIPsex9a 57HfQBpi8ToCzZY74DOlXRe+FV1fOw9OjO/MA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687176149; x=1689768149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UT18RyYaD/6dZxd27WniDZx87FajBAvs3hPdy2nwZV0=; b=clXtCjpb/06HCsZ/QEKN5ZSduUvv1DGkRT9vkWjg+5TrmU5FC7AS27v0TotGnIr5Fz Tdbrl72y3mx8zyOPcAZO0MkTkN36VgewcFD2fhLd3xXFOL/ZVI+NUp+SESSChV6+V96C ANJ6MX591Ek2j/8HsObsxw5JDvQads6GW+WmyIMkRc6A+ETXIwnkPvtcnxVl8Jr3kq5H fnva8aC+LWx/kPxiIYNEKhD7vnPitepHlYaM5o/yIBThg2l0GruiFuvt2hYY3aSt/Ehu bMBQo33tJWUsxobKgYU0XGmr4lpCtljnVHcvkYPvyGbw9DiZJeQVsbh27FBM9DwJ2jCA wY2Q== X-Gm-Message-State: AC+VfDwZtZlUKM0EpnXbH63LcAxK387SzkaBEZpIsrCpekmx3C7nBV7c adYneVfXv6q/+9aWxKZTNAb8VC8rSCUrKXhScUI= X-Google-Smtp-Source: ACHHUZ6s3Ls4UhgWt10F9I8KPT/0mNxYSvu1YL4qHYCSAmWbZhg+m8ycDJz232C/F5fEAa3RmpmL2g== X-Received: by 2002:a05:600c:a382:b0:3f9:b61:8ca8 with SMTP id hn2-20020a05600ca38200b003f90b618ca8mr3461330wmb.6.1687176149337; Mon, 19 Jun 2023 05:02:29 -0700 (PDT) Received: from sjg1.roam.corp.google.com (79-67-123-132.dynamic.dsl.as9105.com. [79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:28 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 42/45] sandbox: Install ACPI tables on startup Date: Mon, 19 Jun 2023 12:59:57 +0100 Message-ID: <20230619125956.v4.42.Iac7708c2705505ade345890cbd4cd83d3bd1c1bf@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean With x86 we set up the ACPI tables on startup so they can be examined. Do the same with sandbox, so it is consistent. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v1) board/sandbox/sandbox.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 54c119daeeeb..9d58860451c5 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -15,7 +15,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -154,6 +156,8 @@ int extension_board_scan(struct list_head *extension_list) int board_late_init(void) { struct udevice *dev; + ulong addr, end; + void *ptr; int ret; ret = uclass_first_device_err(UCLASS_CROS_EC, &dev); @@ -166,6 +170,18 @@ int board_late_init(void) panic("Cannot init cros-ec device"); return -1; } + + if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) { + /* Reserve 64K for ACPI tables, aligned to a 4K boundary */ + ptr = memalign(SZ_4K, SZ_64K); + addr = map_to_sysmem(ptr); + + /* Generate ACPI tables */ + end = write_acpi_tables(addr); + gd->arch.table_start = addr; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:29 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 43/45] efi: Use the installed ACPI tables Date: Mon, 19 Jun 2023 12:59:58 +0100 Message-ID: <20230619125956.v4.43.I86db03df16c50b2b03532f99064a26c14704056f@changeid> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean U-Boot sets up the ACPI tables during startup. Rather than creating a new set, install the existing ones. Create a memory-map record to cover the tables. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: - Drop patch "video: Allow building video drivers for SPL" Changes in v2: - Drop patch to set high bits of the mtrr base register, for now lib/efi_loader/efi_acpi.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c index 2ddc3502b5df..f755af76f866 100644 --- a/lib/efi_loader/efi_acpi.c +++ b/lib/efi_loader/efi_acpi.c @@ -10,6 +10,9 @@ #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID; @@ -20,26 +23,28 @@ static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID; */ efi_status_t efi_acpi_register(void) { - /* Map within the low 32 bits, to allow for 32bit ACPI tables */ - u64 acpi = U32_MAX; + ulong addr, start, end; efi_status_t ret; - ulong addr; - /* Reserve 64kiB page for ACPI */ - ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, - EFI_ACPI_RECLAIM_MEMORY, 16, &acpi); + /* Mark space used for tables */ + start = ALIGN_DOWN(gd->arch.table_start, EFI_PAGE_MASK); + end = ALIGN(gd->arch.table_end, EFI_PAGE_MASK); + ret = efi_add_memory_map(start, end - start, EFI_ACPI_RECLAIM_MEMORY); if (ret != EFI_SUCCESS) return ret; + if (gd->arch.table_start_high) { + start = ALIGN_DOWN(gd->arch.table_start_high, EFI_PAGE_MASK); + end = ALIGN(gd->arch.table_end_high, EFI_PAGE_MASK); + ret = efi_add_memory_map(start, end - start, + EFI_ACPI_RECLAIM_MEMORY); + if (ret != EFI_SUCCESS) + return ret; + } - /* - * Generate ACPI tables - we know that efi_allocate_pages() returns - * a 4k-aligned address, so it is safe to assume that - * write_acpi_tables() will write the table at that address. - */ - addr = map_to_sysmem((void *)(ulong)acpi); - write_acpi_tables(addr); + addr = gd_acpi_start(); + printf("EFI using ACPI tables at %lx\n", addr); /* And expose them to our EFI payload */ return efi_install_configuration_table(&acpi_guid, - (void *)(uintptr_t)acpi); + (void *)(ulong)addr); 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:31 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass , Anatolij Gustschin Subject: [PATCH v4 44/45] x86: video: Add a driver for QEMU bochs emulation Date: Mon, 19 Jun 2023 12:59:59 +0100 Message-ID: <20230619120011.1587499-11-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Bochs is convenient with QEMU on x86 since it does not require a video BIOS. Add a driver for it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Bring in to qemu series - Rebase to -next - Drop unused of_match - Fix Boschs typo - Rename bochs_init_linear_fb() function to drop 'linear' - Fix uninited variable drivers/video/Kconfig | 30 ++++++++++ drivers/video/Makefile | 1 + drivers/video/bochs.c | 123 +++++++++++++++++++++++++++++++++++++++++ drivers/video/bochs.h | 36 ++++++++++++ 4 files changed, 190 insertions(+) create mode 100644 drivers/video/bochs.c create mode 100644 drivers/video/bochs.h diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 49762950719e..2ba4f5eac7f3 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -278,6 +278,36 @@ config VIDCONSOLE_AS_NAME possible to update the environment, the breakage may be confusing for users. This option will be removed around the end of 2020. +config VIDEO_BOCHS + bool "Enable Bochs video emulation for QEMU" + depends on X86 + help + Enable this to use the Bochs video support provided in the QEMU + emulator. This appears as a PCI device which U-Boot can set up to + provide a frame buffer. + +if VIDEO_BOCHS + +config VIDEO_BOCHS_SIZE_X + int "Width of display (X resolution)" + default 1280 + help + Sets the width of the display. + + These two options control the size of the display set up by QEMU. + Typical sizes are 1024 x 768 or 1280 x 1024. + +config VIDEO_BOCHS_SIZE_Y + int "High of display (Y resolution)" + default 1024 + help + Sets the height of the display. + + These two options control the size of the display set up by QEMU. + Typical sizes are 1024 x 768 or 1280 x 1024. + +endif + config VIDEO_COREBOOT bool "Enable coreboot framebuffer driver support" depends on X86 diff --git a/drivers/video/Makefile b/drivers/video/Makefile index f99d7e3c3d90..a9263709084d 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_OSD) += video_osd-uclass.o obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o +obj-$(CONFIG_VIDEO_BOCHS) += bochs.o obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o diff --git a/drivers/video/bochs.c b/drivers/video/bochs.c new file mode 100644 index 000000000000..2136b5119368 --- /dev/null +++ b/drivers/video/bochs.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Modified from coreboot bochs.c + */ + +#define LOG_CATEGORY UCLASS_VIDEO + +#include +#include +#include +#include +#include +#include +#include +#include +#include "bochs.h" + +static int xsize = CONFIG_VIDEO_BOCHS_SIZE_X; +static int ysize = CONFIG_VIDEO_BOCHS_SIZE_Y; + +static void bochs_write(void *mmio, int index, int val) +{ + writew(val, mmio + MMIO_BASE + index * 2); +} + +static int bochs_read(void *mmio, int index) +{ + return readw(mmio + MMIO_BASE + index * 2); +} + +static void bochs_vga_write(int index, uint8_t val) +{ + outb(val, VGA_INDEX); +} + +static int bochs_init_fb(struct udevice *dev) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + ulong fb; + void *mmio; + int id, mem; + + log_debug("probing %s at PCI %x\n", dev->name, dm_pci_get_bdf(dev)); + fb = dm_pci_read_bar32(dev, 0); + if (!fb) + return log_msg_ret("fb", -EIO); + + /* MMIO bar supported since qemu 3.0+ */ + mmio = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_TYPE, + PCI_REGION_MEM); + + if (!mmio) + return log_msg_ret("map", -EIO); + + /* bochs dispi detection */ + id = bochs_read(mmio, INDEX_ID); + if ((id & 0xfff0) != ID0) { + log_debug("ID mismatch\n"); + return -EPROTONOSUPPORT; + } + mem = bochs_read(mmio, INDEX_VIDEO_MEMORY_64K) * SZ_64K; + log_debug("QEMU VGA: bochs @ %p: %d MiB FB at %lx\n", mmio, mem / SZ_1M, + fb); + + uc_priv->xsize = xsize; + uc_priv->ysize = ysize; + uc_priv->bpix = VIDEO_BPP32; + + /* setup video mode */ + bochs_write(mmio, INDEX_ENABLE, 0); + bochs_write(mmio, INDEX_BANK, 0); + bochs_write(mmio, INDEX_BPP, VNBITS(uc_priv->bpix)); + bochs_write(mmio, INDEX_XRES, xsize); + bochs_write(mmio, INDEX_YRES, ysize); + bochs_write(mmio, INDEX_VIRT_WIDTH, xsize); + bochs_write(mmio, INDEX_VIRT_HEIGHT, ysize); + bochs_write(mmio, INDEX_X_OFFSET, 0); + bochs_write(mmio, INDEX_Y_OFFSET, 0); + bochs_write(mmio, INDEX_ENABLE, ENABLED | LFB_ENABLED); + + bochs_vga_write(0, 0x20); /* disable blanking */ + + plat->base = fb; + + return 0; +} + +static int bochs_video_probe(struct udevice *dev) +{ + int ret; + + ret = bochs_init_fb(dev); + if (ret) + return log_ret(ret); + + return 0; +} + +static int bochs_video_bind(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + + /* Set the maximum supported resolution */ + uc_plat->size = 2560 * 1600 * 4; + log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); + + return 0; +} + +U_BOOT_DRIVER(bochs_video) = { + .name = "bochs_video", + .id = UCLASS_VIDEO, + .bind = bochs_video_bind, + .probe = bochs_video_probe, +}; + +static struct pci_device_id bochs_video_supported[] = { + { PCI_DEVICE(0x1234, 0x1111) }, + { }, +}; + +U_BOOT_PCI_DEVICE(bochs_video, bochs_video_supported); diff --git a/drivers/video/bochs.h b/drivers/video/bochs.h new file mode 100644 index 000000000000..4c8ec83a550e --- /dev/null +++ b/drivers/video/bochs.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Modified from coreboot bochs.c + */ + +#ifndef __BOCHS_H +#define __BOCHS_H + +#define VGA_INDEX 0x3c0 + +#define IOPORT_INDEX 0x01ce +#define IOPORT_DATA 0x01cf + +enum { + INDEX_ID, + INDEX_XRES, + INDEX_YRES, + INDEX_BPP, + INDEX_ENABLE, + INDEX_BANK, + INDEX_VIRT_WIDTH, + INDEX_VIRT_HEIGHT, + INDEX_X_OFFSET, + INDEX_Y_OFFSET, + INDEX_VIDEO_MEMORY_64K +}; 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[79.67.123.132]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b0031122bd3c82sm8886794wrp.17.2023.06.19.05.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 05:02:32 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Nikhil M Jain , Simon Glass Subject: [PATCH v4 45/45] x86: Switch QEMU over to use the bochs driver Date: Mon, 19 Jun 2023 13:00:00 +0100 Message-ID: <20230619120011.1587499-12-sjg@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230619120011.1587499-1-sjg@chromium.org> References: <20230619120011.1587499-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This is more convenient since it does not require a video BIOS. Enable it for QEMU. Also drop use of video in SPL for the 64-bit qmeu, since it not needed now. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: - Drop use of video in SPL - Bring in bochs patch to this series arch/x86/cpu/qemu/Kconfig | 2 +- configs/qemu-x86_64_defconfig | 4 ---- configs/qemu-x86_defconfig | 3 --- 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index f8f2f6473088..aa329b0dab29 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -12,7 +12,7 @@ config QEMU imply SYS_NS16550 imply USB imply USB_EHCI_HCD - imply VIDEO_VESA + imply VIDEO_BOCHS if QEMU diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 79ea35918575..870332a1e625 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -84,10 +84,6 @@ CONFIG_SPL_DM_RTC=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y -CONFIG_SPL_VIDEO=y -CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_USER=y -CONFIG_FRAMEBUFFER_VESA_MODE=0x144 CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_FAT_BLK_XLATE=y # CONFIG_SPL_USE_TINY_PRINTF is not set diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 9bf29647fe59..fcf429f77115 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -54,9 +54,6 @@ CONFIG_NVME_PCI=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y -CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_USER=y -CONFIG_FRAMEBUFFER_VESA_MODE=0x144 CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_GENERATE_ACPI_TABLE=y # CONFIG_GZIP is not set