From patchwork Tue Mar 27 04:42:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Smith X-Patchwork-Id: 891378 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 409Jh308kfz9ryr for ; Tue, 27 Mar 2018 15:58:59 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 409Jh20pX4zF21R for ; Tue, 27 Mar 2018 15:58:58 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=stewart@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 409JKq0FwXzF24q for ; Tue, 27 Mar 2018 15:43:10 +1100 (AEDT) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w2R4edAs002496 for ; Tue, 27 Mar 2018 00:43:08 -0400 Received: from e35.co.us.ibm.com (e35.co.us.ibm.com [32.97.110.153]) by mx0a-001b2d01.pphosted.com with ESMTP id 2gyeaj1qkq-1 (version=TLSv1.2 cipher=AES256-SHA256 bits=256 verify=NOT) for ; Tue, 27 Mar 2018 00:43:08 -0400 Received: from localhost by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 26 Mar 2018 22:43:05 -0600 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w2R4h4ZS9306414; Mon, 26 Mar 2018 21:43:04 -0700 Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EE82E136043; Mon, 26 Mar 2018 22:43:03 -0600 (MDT) Received: from birb.localdomain (unknown [9.81.192.6]) by b03ledav002.gho.boulder.ibm.com (Postfix) with SMTP id 0498A13603A; Mon, 26 Mar 2018 22:43:01 -0600 (MDT) Received: by birb.localdomain (Postfix, from userid 1000) id 32A344EC62A; Tue, 27 Mar 2018 15:42:58 +1100 (AEDT) From: Stewart Smith To: skiboot@lists.ozlabs.org Date: Tue, 27 Mar 2018 15:42:57 +1100 X-Mailer: git-send-email 2.14.3 X-TM-AS-GCONF: 00 x-cbid: 18032704-0012-0000-0000-000015F4533A X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008751; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000255; SDB=6.01008983; UDB=6.00513952; IPR=6.00788265; MB=3.00020263; MTD=3.00000008; XFM=3.00000015; UTC=2018-03-27 04:43:06 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18032704-0013-0000-0000-00005208EDB4 Message-Id: <20180327044258.21876-1-stewart@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-03-27_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1803270049 Subject: [Skiboot] [PATCH 1/2] Revert "NPU2 HMIs: dump out a *LOT* of npu2 registers for debugging" X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: rblack@us.ibm.com, zshelle@us.ibm.com, camille@us.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This reverts commit fbdc91e693fc3103f7e2a65054ed32bfb26a2e17. We don't need this as we need to do it a different way, with a explicit set of registers as otherwise we trip other random FIR bits and everything becomes even more terrible. I suggest alcohol. Cc: stable Signed-off-by: Stewart Smith --- core/hmi.c | 38 +------------------------------------- hw/slw.c | 4 ++-- hw/xscom.c | 36 ++++++++++++++---------------------- include/npu2-regs.h | 7 +------ include/xscom.h | 4 ++-- 5 files changed, 20 insertions(+), 69 deletions(-) diff --git a/core/hmi.c b/core/hmi.c index 846d2b9270a8..1a6d145c19db 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -1,4 +1,4 @@ -/* Copyright 2013-2018 IBM Corp. +/* Copyright 2013-2014 IBM Corp. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -29,7 +29,6 @@ #include #include #include -#include /* * HMER register layout: @@ -585,10 +584,7 @@ static void find_npu2_checkstop_reason(int flat_chip_id, uint64_t npu2_fir_action0_addr; uint64_t npu2_fir_action1_addr; uint64_t fatal_errors; - uint64_t npu_scom_dump[2]; - bool npu2_hmi_verbose; int total_errors = 0; - uint64_t r; /* Find the NPU on the chip associated with the HMI. */ for_each_phb(phb) { @@ -640,38 +636,6 @@ static void find_npu2_checkstop_reason(int flat_chip_id, if (!total_errors) return; - npu2_hmi_verbose = nvram_query_eq("npu2-hmi-verbose", "true"); - /* Force this for now until we sort out something better */ - npu2_hmi_verbose = true; - - if (npu2_hmi_verbose) { - _xscom_lock(); - for (r = NPU2_DEBUG_REG_START; r < NPU2_DEBUG_REG_END; r++) { - npu_scom_dump[0] = npu_scom_dump[1] = 0; - _xscom_read(flat_chip_id, r++, &npu_scom_dump[0], false, true); - _xscom_read(flat_chip_id, r, &npu_scom_dump[1], false, true); - prlog(PR_ERR, "NPU: 0x%016llx=0x%016llx 0x%016llx=0x%016llx\n", - r-1, npu_scom_dump[0], - r, npu_scom_dump[1]); - } - for (r = NPU2_FIR_REGISTER_0; r < NPU2_FIR_REGISTER_END; r++) { - npu_scom_dump[0] = npu_scom_dump[1] = 0; - _xscom_read(flat_chip_id, r++, &npu_scom_dump[0], false, true); - _xscom_read(flat_chip_id, r, &npu_scom_dump[1], false, true); - prlog(PR_ERR, "NPU: 0x%016llx=0x%016llx 0x%016llx=0x%016llx\n", - r-1, npu_scom_dump[0], - r, npu_scom_dump[1]); - } - _xscom_unlock(); - prlog(PR_ERR, " _________________________ \n"); - prlog(PR_ERR, "< It's Driver Debug time! >\n"); - prlog(PR_ERR, " ------------------------- \n"); - prlog(PR_ERR, " \\ ,__, \n"); - prlog(PR_ERR, " \\ (oo)____ \n"); - prlog(PR_ERR, " (__) )\\ \n"); - prlog(PR_ERR, " ||--|| * \n"); - } - /* Set up the HMI event */ hmi_evt->severity = OpalHMI_SEV_WARNING; hmi_evt->type = OpalHMI_ERROR_MALFUNC_ALERT; diff --git a/hw/slw.c b/hw/slw.c index 515582b6f359..905e54c9be36 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -1620,7 +1620,7 @@ void slw_update_timer_expiry(uint64_t new_target) /* Grab generation and spin if odd */ _xscom_lock(); for (;;) { - rc = _xscom_read(slw_timer_chip, 0xE0006, &gen, false, false); + rc = _xscom_read(slw_timer_chip, 0xE0006, &gen, false); if (rc) { prerror("SLW: Error %lld reading tmr gen " " count\n", rc); @@ -1664,7 +1664,7 @@ void slw_update_timer_expiry(uint64_t new_target) } /* Re-check gen count */ - rc = _xscom_read(slw_timer_chip, 0xE0006, &gen2, false, false); + rc = _xscom_read(slw_timer_chip, 0xE0006, &gen2, false); if (rc) { prerror("SLW: Error %lld re-reading tmr gen " " count\n", rc); diff --git a/hw/xscom.c b/hw/xscom.c index 1bcfd475e737..05012780aafe 100644 --- a/hw/xscom.c +++ b/hw/xscom.c @@ -215,9 +215,8 @@ static int xscom_clear_error(uint32_t gcid, uint32_t pcb_addr) } static int64_t xscom_handle_error(uint64_t hmer, uint32_t gcid, uint32_t pcb_addr, - bool is_write, int64_t retries, - int64_t *xscom_clear_retries, - bool ignore_error) + bool is_write, int64_t retries, + int64_t *xscom_clear_retries) { unsigned int stat = GETFIELD(SPR_HMER_XSCOM_STATUS, hmer); int64_t rc = OPAL_HARDWARE; @@ -278,12 +277,9 @@ static int64_t xscom_handle_error(uint64_t hmer, uint32_t gcid, uint32_t pcb_add } /* XXX: Create error log entry ? */ - if (!ignore_error) - log_simple_error(&e_info(OPAL_RC_XSCOM_RW), - "XSCOM: %s error gcid=0x%x " - "pcb_addr=0x%x stat=0x%x\n", - is_write ? "write" : "read", gcid, - pcb_addr, stat); + log_simple_error(&e_info(OPAL_RC_XSCOM_RW), + "XSCOM: %s error gcid=0x%x pcb_addr=0x%x stat=0x%x\n", + is_write ? "write" : "read", gcid, pcb_addr, stat); /* We need to reset the XSCOM or we'll hang on the next access */ xscom_reset(gcid, false); @@ -326,16 +322,14 @@ static inline bool xscom_is_multicast_addr(uint32_t addr) * Low level XSCOM access functions, perform a single direct xscom * access via MMIO */ -static int __xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val, - bool ignore_error) +static int __xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val) { uint64_t hmer; int64_t ret, retries; int64_t xscom_clear_retries = XSCOM_CLEAR_MAX_RETRIES; if (!xscom_gcid_ok(gcid)) { - if (!ignore_error) - prerror("%s: invalid XSCOM gcid 0x%x\n", __func__, gcid); + prerror("%s: invalid XSCOM gcid 0x%x\n", __func__, gcid); return OPAL_PARAMETER; } @@ -357,7 +351,7 @@ static int __xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val, /* Handle error and possibly eventually retry */ ret = xscom_handle_error(hmer, gcid, pcb_addr, false, retries, - &xscom_clear_retries, ignore_error); + &xscom_clear_retries); if (ret != OPAL_BUSY) break; } @@ -376,8 +370,7 @@ static int __xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val, if (proc_gen == proc_gen_p9 && ret == OPAL_XSCOM_CHIPLET_OFF) return ret; - if (!ignore_error) - prerror("XSCOM: Read failed, ret = %lld\n", ret); + prerror("XSCOM: Read failed, ret = %lld\n", ret); return ret; } @@ -410,7 +403,7 @@ static int __xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val) /* Handle error and possibly eventually retry */ ret = xscom_handle_error(hmer, gcid, pcb_addr, true, retries, - &xscom_clear_retries, false); + &xscom_clear_retries); if (ret != OPAL_BUSY) break; } @@ -458,7 +451,7 @@ static int xscom_indirect_read_form0(uint32_t gcid, uint64_t pcb_addr, /* Wait for completion */ for (retries = 0; retries < XSCOM_IND_MAX_RETRIES; retries++) { - rc = __xscom_read(gcid, addr, &data, false); + rc = __xscom_read(gcid, addr, &data); if (rc) goto bail; if ((data & XSCOM_DATA_IND_COMPLETE) && @@ -520,7 +513,7 @@ static int xscom_indirect_write_form0(uint32_t gcid, uint64_t pcb_addr, /* Wait for completion */ for (retries = 0; retries < XSCOM_IND_MAX_RETRIES; retries++) { - rc = __xscom_read(gcid, addr, &data, false); + rc = __xscom_read(gcid, addr, &data); if (rc) goto bail; if ((data & XSCOM_DATA_IND_COMPLETE) && @@ -595,8 +588,7 @@ void _xscom_unlock(void) /* * External API */ -int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, - bool take_lock, bool ignore_error) +int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, bool take_lock) { uint32_t gcid; int rc; @@ -643,7 +635,7 @@ int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, if (pcb_addr & XSCOM_ADDR_IND_FLAG) rc = xscom_indirect_read(gcid, pcb_addr, val); else - rc = __xscom_read(gcid, pcb_addr & 0x7fffffff, val, ignore_error); + rc = __xscom_read(gcid, pcb_addr & 0x7fffffff, val); /* Unlock it */ if (take_lock) diff --git a/include/npu2-regs.h b/include/npu2-regs.h index be57fd920e19..a8f571eba143 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -1,4 +1,4 @@ -/* Copyright 2013-2018 IBM Corp. +/* Copyright 2013-2016 IBM Corp. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -29,10 +29,6 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, uint64_t reg, uint64_t size, uint64_t val); -/* SCOM Registers to dump on HMI to aid in debugging */ -#define NPU2_DEBUG_REG_START 0x5011000 -#define NPU2_DEBUG_REG_END 0x50110FF - /* These aren't really NPU specific registers but we initialise them in NPU * code */ #define MCD0_BANK0_CN3 0x301100d @@ -576,7 +572,6 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_FIR_REGISTER_0 0x0000000005013C00 #define NPU2_FIR_REGISTER_1 0x0000000005013C40 #define NPU2_FIR_REGISTER_2 0x0000000005013C80 -#define NPU2_FIR_REGISTER_END 0x0000000005013CFF #define NPU2_TOTAL_FIR_REGISTERS 3 diff --git a/include/xscom.h b/include/xscom.h index 3193abdbb6e9..98532240b116 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -225,7 +225,7 @@ /* Use only in select places where multiple SCOMs are time/latency sensitive */ extern void _xscom_lock(void); -extern int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, bool take_lock, bool ignore_error); +extern int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, bool take_lock); extern int _xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val, bool take_lock); extern void _xscom_unlock(void); @@ -233,7 +233,7 @@ extern void _xscom_unlock(void); /* Targeted SCOM access */ static inline int xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val) { - return _xscom_read(partid, pcb_addr, val, true, false); + return _xscom_read(partid, pcb_addr, val, true); } static inline int xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val) { return _xscom_write(partid, pcb_addr, val, true); From patchwork Tue Mar 27 04:42:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Smith X-Patchwork-Id: 891379 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 409JhR0wlxz9ryr for ; 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Violators will be prosecuted; Mon, 26 Mar 2018 22:43:05 -0600 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w2R4h4bh13435272; Mon, 26 Mar 2018 21:43:04 -0700 Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DB51978037; Mon, 26 Mar 2018 22:43:03 -0600 (MDT) Received: from birb.localdomain (unknown [9.81.192.6]) by b03ledav004.gho.boulder.ibm.com (Postfix) with SMTP id 04F5478041; Mon, 26 Mar 2018 22:43:01 -0600 (MDT) Received: by birb.localdomain (Postfix, from userid 1000) id 383844EC653; Tue, 27 Mar 2018 15:42:58 +1100 (AEDT) From: Stewart Smith To: skiboot@lists.ozlabs.org Date: Tue, 27 Mar 2018 15:42:58 +1100 X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180327044258.21876-1-stewart@linux.vnet.ibm.com> References: <20180327044258.21876-1-stewart@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18032704-0012-0000-0000-000015F4533B X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008751; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000255; SDB=6.01008983; UDB=6.00513952; IPR=6.00788265; MB=3.00020263; MTD=3.00000008; XFM=3.00000015; UTC=2018-03-27 04:43:06 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18032704-0013-0000-0000-00005208EDB6 Message-Id: <20180327044258.21876-2-stewart@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-03-27_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1803270049 Subject: [Skiboot] [PATCH 2/2] NPU2: dump NPU2 registers on npu2 HMI X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: rblack@us.ibm.com, zshelle@us.ibm.com, camille@us.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Due to the nature of debugging npu2 issues, folk are wanting the full list of NPU2 registers dumped when there's a problem. We have to list out each register as traversing the range triggers FIR bits that confuse PRD. Suggested-by: Ryan Black Signed-off-by: Stewart Smith --- core/hmi.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/core/hmi.c b/core/hmi.c index 1a6d145c19db..162dd8a11253 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -1,4 +1,4 @@ -/* Copyright 2013-2014 IBM Corp. +/* Copyright 2013-2018 IBM Corp. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -29,6 +29,7 @@ #include #include #include +#include /* * HMER register layout: @@ -567,6 +568,59 @@ static void find_nx_checkstop_reason(int flat_chip_id, *event_generated = true; } +/* + * If the year is 2018 and you still see all these hardcoded, you + * should really replace this with the neat macros that's in the + * NPU2 code rather than this horrible listing of every single + * NPU2 register hardcoded for a specific chip. + * + * I feel dirty having even written it. + */ +static uint32_t npu2_scom_dump[] = { + 0x5011017, 0x5011047, 0x5011077, 0x50110A7, + 0x5011217, 0x5011247, 0x5011277, 0x50112A7, + 0x5011417, 0x5011447, 0x5011477, 0x50114A7, + 0x50110DA, 0x50112DA, 0x50114DA, + 0x50110DB, 0x50112DB, 0x50114DB, + 0x5011011, 0x5011041, 0x5011071, 0x50110A1, + 0x5011211, 0x5011241, 0x5011271, 0x50112A1, + 0x5011411, 0x5011441, 0x5011471, 0x50114A1, + 0x5011018, 0x5011048, 0x5011078, 0x50110A8, + 0x5011218, 0x5011248, 0x5011278, 0x50112A8, + 0x5011418, 0x5011448, 0x5011478, 0x50114A8, + 0x5011640, + 0x5011114, 0x5011134, 0x5011314, 0x5011334, + 0x5011514, 0x5011534, 0x5011118, 0x5011138, + 0x5011318, 0x5011338, 0x5011518, 0x5011538, + 0x50110D8, 0x50112D8, 0x50114D8, + 0x50110D9, 0x50112D9, 0x50114D9, + 0x5011019, 0x5011049, 0x5011079, 0x50110A9, + 0x5011219, 0x5011249, 0x5011279, 0x50112A9, + 0x5011419, 0x5011449, 0x5011479, 0x50114A9, + 0x50110F4, 0x50112F4, 0x50114F4, + 0x50110F5, 0x50112F5, 0x50114F5, + 0x50110F6, 0x50112F6, 0x50114F6, + 0x50110FD, 0x50112FD, 0x50114FD, + 0x50110FE, 0x50112FE, 0x50114FE, + 0x00 +}; + +static void dump_scoms(int flat_chip_id, const char *unit, uint32_t *scoms) +{ + uint64_t value; + int r; + + while (*scoms != 0) { + value = 0; + r = _xscom_read(flat_chip_id, *scoms, &value, false); + if (r != OPAL_SUCCESS) + continue; + prlog(PR_ERR, "%s: 0x%08x=0x%016llx\n", + unit, *scoms, value); + scoms++; + } +} + static void find_npu2_checkstop_reason(int flat_chip_id, struct OpalHMIEvent *hmi_evt, bool *event_generated) @@ -574,7 +628,7 @@ static void find_npu2_checkstop_reason(int flat_chip_id, struct phb *phb; struct npu *p = NULL; int i; - + bool npu2_hmi_verbose = false; uint64_t npu2_fir; uint64_t npu2_fir_mask; uint64_t npu2_fir_action0; @@ -636,6 +690,23 @@ static void find_npu2_checkstop_reason(int flat_chip_id, if (!total_errors) return; + npu2_hmi_verbose = nvram_query_eq("npu2-hmi-verbose", "true"); + /* Force this for now until we sort out something better */ + npu2_hmi_verbose = true; + + if (npu2_hmi_verbose) { + _xscom_lock(); + dump_scoms(flat_chip_id, "NPU2", npu2_scom_dump); + _xscom_unlock(); + prlog(PR_ERR, " _________________________ \n"); + prlog(PR_ERR, "< It's Driver Debug time! >\n"); + prlog(PR_ERR, " ------------------------- \n"); + prlog(PR_ERR, " \\ ,__, \n"); + prlog(PR_ERR, " \\ (oo)____ \n"); + prlog(PR_ERR, " (__) )\\ \n"); + prlog(PR_ERR, " ||--|| * \n"); + } + /* Set up the HMI event */ hmi_evt->severity = OpalHMI_SEV_WARNING; hmi_evt->type = OpalHMI_ERROR_MALFUNC_ALERT;