From patchwork Mon Jun 12 07:35:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1793776 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qfk5t4JMBz20QH for ; Mon, 12 Jun 2023 17:36:50 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 306C385F1F; Mon, 12 Jun 2023 09:36:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinylab.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id D1FCA86129; Mon, 12 Jun 2023 09:36:31 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.154.221.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EB2D885EEF for ; Mon, 12 Jun 2023 09:36:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinylab.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bmeng@tinylab.org X-QQ-mid: bizesmtp85t1686555370txon1jb8 Received: from pek-vx-bsp2.wrs.com ( [60.247.85.88]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 12 Jun 2023 15:36:09 +0800 (CST) X-QQ-SSF: 01200000000000E0G000000A0000000 X-QQ-FEAT: eSZ1CZgv+JBLMBInMIktn19PaAvmq7dRW+ssEggrbip/qJUyx8Jv/R6UXaJYp MpKDx5ROJ4lUhrZfGx4YJcQHwmqQQrdhbedvg6J/vfDayHr1f2sgSAx4XXTUcz2dy9jJeO5 IWs2nt9bN0xZXQrBNUplCbze8BrZgcVTpbtORT3gXP6f4N5LpaGvYc74dQStu5OEE+AjT9i iOE0jDGABnzIgmBz7M6OQUJSOsSrFp6b4XwpxC3Y+6zb5uBxRTImxcGZk3EoiZf2ScvusLz +1+RlVCGv4Pp1oP5Ogu44RcVkMVT4+Hy+blv2WQI2GtoBaI7nc374LhVTr2QYRaMpNBMnCD v5bhTV9Iu5PGxlvWc20X2RwFtDtUVbKP6g9xSbrQHB7LtAdosY= X-QQ-GoodBg: 0 X-BIZMAIL-ID: 6735396306147590146 From: Bin Meng To: u-boot@lists.denx.de Cc: Anup Patel , Atish Patra , Bin Meng , Palmer Dabbelt , Paul Walmsley , Rick Chen Subject: [PATCH 1/3] riscv: timer: Update the sifive clint timer driver to support aclint Date: Mon, 12 Jun 2023 15:35:48 +0800 Message-Id: <20230612073551.885100-2-bmeng@tinylab.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230612073551.885100-1-bmeng@tinylab.org> References: <20230612073551.885100-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvrgz:qybglogicsvrgz7a-0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint timer driver to support ACLINT mtimer device, using a per-driver data field to hold the mtimer offset to the base address encoded in the mtimer node. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng --- drivers/timer/sifive_clint_timer.c | 16 +++++++++++----- include/configs/ae350.h | 2 +- include/configs/qemu-riscv.h | 2 +- include/configs/sifive-unleashed.h | 2 +- include/configs/starfive-visionfive2.h | 1 + 5 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c index 939b99d937..be45f17ddf 100644 --- a/drivers/timer/sifive_clint_timer.c +++ b/drivers/timer/sifive_clint_timer.c @@ -12,12 +12,16 @@ #include #include +#define CLINT_MTIME_OFFSET 0xbff8 +#define ACLINT_MTIME_OFFSET 0 + /* mtime register */ -#define MTIME_REG(base) ((ulong)(base) + 0xbff8) +#define MTIME_REG(base, offset) ((ulong)(base) + (offset)) static u64 notrace sifive_clint_get_count(struct udevice *dev) { - return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); + return readq((void __iomem *)MTIME_REG(dev_get_priv(dev), + dev_get_driver_data(dev))); } #if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) @@ -35,7 +39,8 @@ unsigned long notrace timer_early_get_rate(void) */ u64 notrace timer_early_get_count(void) { - return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE, + RISCV_MMODE_TIMEROFF)); } #endif @@ -53,8 +58,9 @@ static int sifive_clint_probe(struct udevice *dev) } static const struct udevice_id sifive_clint_ids[] = { - { .compatible = "riscv,clint0" }, - { .compatible = "sifive,clint0" }, + { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET }, + { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET }, + { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET }, { } }; diff --git a/include/configs/ae350.h b/include/configs/ae350.h index b566ecf296..02c5c80215 100644 --- a/include/configs/ae350.h +++ b/include/configs/ae350.h @@ -8,8 +8,8 @@ #define __CONFIG_H #define RISCV_MMODE_TIMERBASE 0xe6000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 60000000 - #define RISCV_SMODE_TIMER_FREQ 60000000 /* diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 20135f569e..f6d326bda0 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -11,8 +11,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 1000000 - #define RISCV_SMODE_TIMER_FREQ 1000000 /* Environment options */ diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index de3a0dcdd5..f208f5e20d 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -14,8 +14,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 1000000 - #define RISCV_SMODE_TIMER_FREQ 1000000 /* Environment options */ diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 93dcc22d36..4ee02b8420 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -9,6 +9,7 @@ #define _STARFIVE_VISIONFIVE2_H #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 4000000 #define RISCV_SMODE_TIMER_FREQ 4000000 From patchwork Mon Jun 12 07:35:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1793775 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qfk5d4QvVz20QH for ; Mon, 12 Jun 2023 17:36:37 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9E4D886068; Mon, 12 Jun 2023 09:36:28 +0200 (CEST) Authentication-Results: phobos.denx.de; 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Mon, 12 Jun 2023 15:36:14 +0800 (CST) X-QQ-SSF: 01200000000000E0G000000A0000000 X-QQ-FEAT: ILHsT53NKPim+rX9DEvLh4ssgqYTGOVWquzrbFxNWj/tlLUwT6lsd5RFSauOB r/b+AW+euZUM740vdP2oIm8N/f7Qm3LtjDFSlx+3RGjE7j5PETDEyJVzMf0choUzBdXoDtF FzZNgfVsyoeJiuF3mkfA30HtSSquHpDqz6eoYU27G1V1y2e/ElUBlFaVQKCXIkmhagEalE7 c+wljo/IO38eutF8Blq0dzN23inWXTsIot6bCP1jTCWYUcVhjnTTBNc2sQ2MG4knW6SUyQm b9DFN57GWfRq2Py4YKXgj6XyqZpXydwJeXtwHS4vcAq8I2yv/eI3eh+8/t4iba6HGSYfQU4 LABIToxsoQLOZQRT3N7LNbCvGziJAkiaK4Ig9lLXDhegrSmPvc= X-QQ-GoodBg: 0 X-BIZMAIL-ID: 11917093514151562577 From: Bin Meng To: u-boot@lists.denx.de Cc: Leo , Rick Chen Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint Date: Mon, 12 Jun 2023 15:35:49 +0800 Message-Id: <20230612073551.885100-3-bmeng@tinylab.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230612073551.885100-1-bmeng@tinylab.org> References: <20230612073551.885100-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvrgz:qybglogicsvrgz7a-0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint ipi driver to support ACLINT mswi device, by checking the per-driver data field of the ACLINT mtimer driver to determine whether a syscon based approach needs to be taken to get the base address of the ACLINT mswi device. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/Kconfig | 4 ++++ arch/riscv/lib/sifive_clint.c | 21 ++++++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f6ed05906a..9fcdd8c451 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -188,6 +188,8 @@ config DMA_ADDR_T_64BIT config SIFIVE_CLINT bool depends on RISCV_MMODE + select REGMAP + select SYSCON help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. @@ -195,6 +197,8 @@ config SIFIVE_CLINT config SPL_SIFIVE_CLINT bool depends on SPL_RISCV_MMODE + select SPL_REGMAP + select SPL_SYSCON help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index ab22395c55..f242168381 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -10,9 +10,12 @@ #include #include +#include +#include #include #include #include +#include #include /* MSIP registers */ @@ -30,7 +33,11 @@ int riscv_init_ipi(void) if (ret) return ret; - gd->arch.clint = dev_read_addr_ptr(dev); + if (dev_get_driver_data(dev) != 0) + gd->arch.clint = dev_read_addr_ptr(dev); + else + gd->arch.clint = syscon_get_first_range(RISCV_SYSCON_CLINT); + if (!gd->arch.clint) return -EINVAL; @@ -57,3 +64,15 @@ int riscv_get_ipi(int hart, int *pending) return 0; } + +static const struct udevice_id riscv_aclint_swi_ids[] = { + { .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_CLINT }, + { } +}; + +U_BOOT_DRIVER(riscv_aclint_swi) = { + .name = "riscv_aclint_swi", + .id = UCLASS_SYSCON, + .of_match = riscv_aclint_swi_ids, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Mon Jun 12 07:35:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1793777 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qfk6W4Qfnz20QH for ; Mon, 12 Jun 2023 17:37:23 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 27D3B860BB; Mon, 12 Jun 2023 09:37:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinylab.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7E9EA8615A; Mon, 12 Jun 2023 09:37:19 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.154.221.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2656B85C2B for ; Mon, 12 Jun 2023 09:37:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinylab.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bmeng@tinylab.org X-QQ-mid: bizesmtp62t1686555381t0j6x6j6 Received: from pek-vx-bsp2.wrs.com ( [60.247.85.88]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 12 Jun 2023 15:36:18 +0800 (CST) X-QQ-SSF: 01200000000000E0G000000A0000000 X-QQ-FEAT: k0mQ4ihyJQPpQd+/vX4kPAhDUGWUYfzL1IWynO2DikoVnS089j8GwGRQBqUBl RG5mh9Ju8FVvANm3wQ6KxumzgOOtzQOuxfxT8zCzkrownx9PG5mznsybTwT8ziETuoMp4WF bZdy/2cSQ2cVv29mq+3G7I9xcROl/hHh3r/U9Wq2Q0wy5cfID2NHyStPfpVdEtmWssLPHda PKOQ2MiZ0a+T00pZ8vdqTfBg6o/th54WmV2ctQ5aNgHeMEEEFRDZsoeTVXqsZRS8jOOxXut Hrr4t46E8bYBsXGBmxlIkKuAAU6N2J6KHAzsz6wTlnEeEiO+I2y1HE8gP+KsogXKdJRkd7K eh0C9sqNoOQ8+lleCQZRZuE66FKQ1pS7TuMYSSLpDolqJ0+lAQ= X-QQ-GoodBg: 0 X-BIZMAIL-ID: 16131212618697782594 From: Bin Meng To: u-boot@lists.denx.de Cc: Andre Przywara , Anup Patel , =?utf-8?q?Jonas_Schw=C3=B6bel?= , Kautuk Consul , Leo , Michael Walle , Michal Simek , Nikita Shubin , Rick Chen , Sean Anderson , Sergei Antonov , Simon Glass , Stefan Herbrechtsmeier , Svyatoslav Ryhel , Tianrui Wei , William Zhang , Yanhong Wang , Yu Chien Peter Lin Subject: [PATCH 3/3] riscv: Rename SiFive CLINT to RISC-V ALINT Date: Mon, 12 Jun 2023 15:35:50 +0800 Message-Id: <20230612073551.885100-4-bmeng@tinylab.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230612073551.885100-1-bmeng@tinylab.org> References: <20230612073551.885100-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvrgz:qybglogicsvrgz7a-0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng Reviewed-by: Rick Chen --- MAINTAINERS | 2 +- arch/riscv/Kconfig | 8 ++++---- arch/riscv/cpu/fu540/Kconfig | 2 +- arch/riscv/cpu/fu740/Kconfig | 2 +- arch/riscv/cpu/generic/Kconfig | 4 ++-- arch/riscv/cpu/jh7110/Kconfig | 2 +- arch/riscv/include/asm/global_data.h | 4 ++-- arch/riscv/include/asm/syscon.h | 2 +- arch/riscv/lib/Makefile | 2 +- .../lib/{sifive_clint.c => aclint_ipi.c} | 16 +++++++-------- board/openpiton/riscv64/Kconfig | 2 +- board/sipeed/maix/Kconfig | 2 +- drivers/timer/Makefile | 2 +- ...ive_clint_timer.c => riscv_aclint_timer.c} | 20 +++++++++---------- 14 files changed, 35 insertions(+), 35 deletions(-) rename arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (73%) rename drivers/timer/{sifive_clint_timer.c => riscv_aclint_timer.c} (75%) diff --git a/MAINTAINERS b/MAINTAINERS index 228d8af433..91f125aed0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1328,7 +1328,7 @@ F: doc/arch/riscv.rst F: doc/usage/sbi.rst F: drivers/sysreset/sysreset_sbi.c F: drivers/timer/andes_plmt_timer.c -F: drivers/timer/sifive_clint_timer.c +F: drivers/timer/riscv_aclint_timer.c F: tools/prelink-riscv.c RISC-V CANAAN KENDRYTE K210 diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9fcdd8c451..de7d5a9549 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -185,22 +185,22 @@ config DMA_ADDR_T_64BIT bool default y if 64BIT -config SIFIVE_CLINT +config RISCV_ACLINT bool depends on RISCV_MMODE select REGMAP select SYSCON help - The SiFive CLINT block holds memory-mapped control and status registers + The RISC-V ACLINT block holds memory-mapped control and status registers associated with software and timer interrupts. -config SPL_SIFIVE_CLINT +config SPL_RISCV_ACLINT bool depends on SPL_RISCV_MMODE select SPL_REGMAP select SPL_SYSCON help - The SiFive CLINT block holds memory-mapped control and status registers + The RISC-V ACLINT block holds memory-mapped control and status registers associated with software and timer interrupts. config SIFIVE_CACHE diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index 1604b412b4..c68209d8fb 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -11,7 +11,7 @@ config SIFIVE_FU540 imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply SPL_SIFIVE_CLINT + imply SPL_RISCV_ACLINT imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index 3e0c1fddc8..d7ca968717 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -11,7 +11,7 @@ config SIFIVE_FU740 imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply SPL_SIFIVE_CLINT + imply SPL_RISCV_ACLINT imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig index e025134b23..897765c3c6 100644 --- a/arch/riscv/cpu/generic/Kconfig +++ b/arch/riscv/cpu/generic/Kconfig @@ -9,8 +9,8 @@ config GENERIC_RISCV imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply SIFIVE_CLINT if RISCV_MMODE - imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE + imply RISCV_ACLINT if RISCV_MMODE + imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 3f145415eb..4d9581165b 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -25,4 +25,4 @@ config STARFIVE_JH7110 imply SPL_CPU imply SPL_LOAD_FIT imply SPL_OPENSBI - imply SPL_SIFIVE_CLINT + imply SPL_RISCV_ACLINT diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 31ba72693d..9d97517e12 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -18,8 +18,8 @@ struct arch_global_data { long boot_hart; /* boot hart id */ phys_addr_t firmware_fdt_addr; -#if CONFIG_IS_ENABLED(SIFIVE_CLINT) - void __iomem *clint; /* clint base address */ +#if CONFIG_IS_ENABLED(RISCV_ACLINT) + void __iomem *aclint; /* aclint base address */ #endif #ifdef CONFIG_ANDES_PLICSW void __iomem *plicsw; /* andes plicsw base address */ diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h index f2b37975f3..5787702e74 100644 --- a/arch/riscv/include/asm/syscon.h +++ b/arch/riscv/include/asm/syscon.h @@ -12,7 +12,7 @@ */ enum { RISCV_NONE, - RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */ + RISCV_SYSCON_ACLINT, /* Advanced Core Local Interruptor (ACLINT) */ RISCV_SYSCON_PLICSW, /* Andes PLICSW */ }; diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index e5a81ba722..02c4d8fcc6 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -12,7 +12,7 @@ obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) -obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o +obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += aclint_ipi.o obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o else obj-$(CONFIG_SBI) += sbi.o diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/aclint_ipi.c similarity index 73% rename from arch/riscv/lib/sifive_clint.c rename to arch/riscv/lib/aclint_ipi.c index f242168381..90b8e128cb 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/aclint_ipi.c @@ -29,16 +29,16 @@ int riscv_init_ipi(void) struct udevice *dev; ret = uclass_get_device_by_driver(UCLASS_TIMER, - DM_DRIVER_GET(sifive_clint), &dev); + DM_DRIVER_GET(riscv_aclint_timer), &dev); if (ret) return ret; if (dev_get_driver_data(dev) != 0) - gd->arch.clint = dev_read_addr_ptr(dev); + gd->arch.aclint = dev_read_addr_ptr(dev); else - gd->arch.clint = syscon_get_first_range(RISCV_SYSCON_CLINT); + gd->arch.aclint = syscon_get_first_range(RISCV_SYSCON_ACLINT); - if (!gd->arch.clint) + if (!gd->arch.aclint) return -EINVAL; return 0; @@ -46,27 +46,27 @@ int riscv_init_ipi(void) int riscv_send_ipi(int hart) { - writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); + writel(1, (void __iomem *)MSIP_REG(gd->arch.aclint, hart)); return 0; } int riscv_clear_ipi(int hart) { - writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); + writel(0, (void __iomem *)MSIP_REG(gd->arch.aclint, hart)); return 0; } int riscv_get_ipi(int hart, int *pending) { - *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart)); + *pending = readl((void __iomem *)MSIP_REG(gd->arch.aclint, hart)); return 0; } static const struct udevice_id riscv_aclint_swi_ids[] = { - { .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_CLINT }, + { .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_ACLINT }, { } }; diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig index eb0db8a64c..21da1dc346 100644 --- a/board/openpiton/riscv64/Kconfig +++ b/board/openpiton/riscv64/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPPORT_SPL imply CPU_RISCV imply RISCV_TIMER - imply SPL_SIFIVE_CLINT + imply SPL_RISCV_ACLINT imply CMD_CPU imply SPL_CPU_SUPPORT imply SPL_SMP diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig index 2d212ec5a3..d34ea4be71 100644 --- a/board/sipeed/maix/Kconfig +++ b/board/sipeed/maix/Kconfig @@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS imply SMP imply DM_SERIAL imply SIFIVE_SERIAL - imply SIFIVE_CLINT + imply RISCV_ACLINT imply POWER_DOMAIN imply SIMPLE_PM_BUS imply CLK_K210 diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index cdc20f5e94..1ca74805fd 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -25,7 +25,7 @@ obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_SP804_TIMER) += sp804_timer.o -obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o +obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += riscv_aclint_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/riscv_aclint_timer.c similarity index 75% rename from drivers/timer/sifive_clint_timer.c rename to drivers/timer/riscv_aclint_timer.c index be45f17ddf..e29d527c8d 100644 --- a/drivers/timer/sifive_clint_timer.c +++ b/drivers/timer/riscv_aclint_timer.c @@ -18,7 +18,7 @@ /* mtime register */ #define MTIME_REG(base, offset) ((ulong)(base) + (offset)) -static u64 notrace sifive_clint_get_count(struct udevice *dev) +static u64 notrace riscv_aclint_timer_get_count(struct udevice *dev) { return readq((void __iomem *)MTIME_REG(dev_get_priv(dev), dev_get_driver_data(dev))); @@ -44,11 +44,11 @@ u64 notrace timer_early_get_count(void) } #endif -static const struct timer_ops sifive_clint_ops = { - .get_count = sifive_clint_get_count, +static const struct timer_ops riscv_aclint_timer_ops = { + .get_count = riscv_aclint_timer_get_count, }; -static int sifive_clint_probe(struct udevice *dev) +static int riscv_aclint_timer_probe(struct udevice *dev) { dev_set_priv(dev, dev_read_addr_ptr(dev)); if (!dev_get_priv(dev)) @@ -57,18 +57,18 @@ static int sifive_clint_probe(struct udevice *dev) return timer_timebase_fallback(dev); } -static const struct udevice_id sifive_clint_ids[] = { +static const struct udevice_id riscv_aclint_timer_ids[] = { { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET }, { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET }, { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET }, { } }; -U_BOOT_DRIVER(sifive_clint) = { - .name = "sifive_clint", +U_BOOT_DRIVER(riscv_aclint_timer) = { + .name = "riscv_aclint_timer", .id = UCLASS_TIMER, - .of_match = sifive_clint_ids, - .probe = sifive_clint_probe, - .ops = &sifive_clint_ops, + .of_match = riscv_aclint_timer_ids, + .probe = riscv_aclint_timer_probe, + .ops = &riscv_aclint_timer_ops, .flags = DM_FLAG_PRE_RELOC, };