From patchwork Tue Jun 6 11:46:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 1791107 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qb7xt0FZsz20WK for ; Tue, 6 Jun 2023 21:47:28 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 10E5138323FF for ; Tue, 6 Jun 2023 11:47:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id 41360385588B for ; Tue, 6 Jun 2023 11:46:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 41360385588B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp75t1686051998tvrovwrf Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 06 Jun 2023 19:46:38 +0800 (CST) X-QQ-SSF: 01400000000000F0S000000A0000000 X-QQ-FEAT: q+EIYT+FhZpua786lLpr9UGw1LY+eEBALxzQRnY5TqcK66IFYGBczdtSgIH6X Y0qu4p5WCp/DaAnETIPcZIMBshF6y0c4BGJuP1qI6u4/Cj5xOuWoPeRPKvCmbAqDXXO6z9+ 6fXON9lsg4je3jtq/GVzM/dZksf7KZUTDShObQ3u9lKDj5WDDCWz6sEcznIMTDAJpeFlH+A E0qHj/cFPE9bQXaBVofPEQTA7/nOU2CPMOtPUo2WaRSVA3M+VLPo8JE0kYgraz5L4p+DXTr X0RO2O2UqrwinII75ju4G3HItpeGQ5nw39q0FLSiK49yYLsZJVScSmoxitLgXu+wmz3S7dk pxA8TWrhgzG0V5IaN1YgDf9y4KT6+CzuWzuIfhTX6T46SWw5DRAcF2ti5bpKVUtjqghAqp3 s3UbvgQudlwm37AHQt8Ebg== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 948782303754987380 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Enable SELECT_VL for RVV Date: Tue, 6 Jun 2023 19:46:31 +0800 Message-Id: <20230606114632.1629751-2-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230606114632.1629751-1-juzhe.zhong@rivai.ai> References: <20230606114632.1629751-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong gcc/ChangeLog: * config/riscv/autovec.md (select_vl): New pattern. * config/riscv/riscv-protos.h (gen_no_side_effects_vsetvl_rtx): export global. * config/riscv/riscv-v.cc (force_vector_length_operand): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Adapt test. * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: New test. --- gcc/config/riscv/autovec.md | 19 +++++++++++++ gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 2 +- .../riscv/rvv/autovec/partial/select_vl-1.c | 28 +++++++++++++++++++ .../riscv/rvv/autovec/ternop/ternop-2.c | 2 +- .../riscv/rvv/autovec/ternop/ternop-5.c | 2 +- 6 files changed, 51 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 9f4492db23c..c298f069714 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -18,6 +18,25 @@ ;; along with GCC; see the file COPYING3. If not see ;; . +;; ========================================================================= +;; == SELECT_VL +;; ========================================================================= + +(define_expand "select_vl" + [(match_operand:P 0 "register_operand") + (match_operand:P 1 "vector_length_operand") + (match_operand:P 2 "")] + "TARGET_VECTOR" +{ + poly_int64 nunits = rtx_to_poly_int64 (operands[2]); + /* We arbitrary picked QImode as inner scalar mode to get vector mode. + since vsetvl only demand ratio. We let VSETVL PASS to optimize it. */ + scalar_int_mode mode = QImode; + machine_mode rvv_mode = riscv_vector::get_vector_mode (mode, nunits).require (); + emit_insn (riscv_vector::gen_no_side_effects_vsetvl_rtx (rvv_mode, operands[0], operands[1])); + DONE; +}) + ;; ========================================================================= ;; == Loads/Stores ;; ========================================================================= diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 00e1b20c6c6..d770e5e826e 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -232,6 +232,7 @@ enum vlen_enum RVV_64 = 64, RVV_65536 = 65536 }; +rtx gen_no_side_effects_vsetvl_rtx (machine_mode, rtx, rtx); bool slide1_sew64_helper (int, machine_mode, machine_mode, machine_mode, rtx *); rtx gen_avl_for_scalar_move (rtx); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 49752cd8899..83277fc2c05 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1280,7 +1280,7 @@ force_vector_length_operand (rtx vl) return vl; } -static rtx +rtx gen_no_side_effects_vsetvl_rtx (machine_mode vmode, rtx vl, rtx avl) { unsigned int sew = get_sew (vmode); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c new file mode 100644 index 00000000000..b8e0ca0f1f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */ + +#include + +#define TEST_TYPE(TYPE) \ + __attribute__ ((noipa)) void select_vl_##TYPE (TYPE *__restrict dst, \ + TYPE *__restrict a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i]; \ + } + +#define TEST_ALL() \ + TEST_TYPE (int8_t) \ + TEST_TYPE (uint8_t) \ + TEST_TYPE (int16_t) \ + TEST_TYPE (uint16_t) \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) \ + TEST_TYPE (float) \ + TEST_TYPE (double) + +TEST_ALL () + +/* { dg-final { scan-tree-dump-times "\.SELECT_VL" 10 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c index 89eeaf6315f..e52e07ddd09 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c index a9a7198feb4..49c85efbf3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns" } */ #include