From patchwork Thu May 25 06:48:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 1785918 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QRdvq4RhCz20QL for ; Thu, 25 May 2023 16:49:43 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AB28B3857738 for ; Thu, 25 May 2023 06:49:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id 00F6F3858D28 for ; Thu, 25 May 2023 06:48:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 00F6F3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp80t1684997288t3ij7lsl Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 25 May 2023 14:48:07 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: hJ5650VbgwD/U8Y8OXzhanxR3T1aavlXwV3cJXhNuO9LzEiSW3yZ6gufOArPZ WTQvk5JvD4v7gvKFxcLnOcmr+8vPX/x+4CE+gTDiix9DG5QStJDnSjObuanad4m8TAcoiG0 33krnQ3IzdQ8YRtXRnRlYCN3wTTdpNmD1BjAd0l5puAk7WA+lx0YF8F/lTTsn6t5sbCp/be 8NU9Y1xbBfRrdIlUMbKjrhc9+De7D8ULS8yrGttg8bBVVj7HiwqgeS28tkg5ORi8SAkb4qD mktvBsEY/XNYD2Lh2ju4DjMr9orEpZWiwMxphgj4K7f2lYEZ7T35YDMgD5BrlklLLQ616up YgdD8mwr2gOhreepnugvte3XCdS+eJ0b5IThK2u8Ym2h7F3SXO5YQgFJyFT3czYn5O/VyGC yFlFu0bRNY/1v+miywwqbw== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 17913990913828604860 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, pan2.li@intel.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM Date: Thu, 25 May 2023 14:48:06 +0800 Message-Id: <20230525064806.1676311-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong Currenty mode switching incorrect codegen for the following case: void fn (void); void f (void * in, void *out, int32_t x, int n, int m) { for (int i = 0; i < n; i++) { vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4); vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); fn (); v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4); } } Before this patch: Preheader: ... csrwi vxrm,2 Loop Body: ... (no cswri vxrm,2) vaadd.vx ... vaadd.vx ... This codegen is incorrect. After this patch: Preheader: ... csrwi vxrm,2 Loop Body: ... vaadd.vx ... csrwi vxrm,2 ... vaadd.vx ... cross-compile build PASS and regression PASS Ok for trunk ? gcc/ChangeLog: * config/riscv/riscv.cc (global_state_unknown_p): New function. (riscv_mode_after): Fix incorrect VXM. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vxrm-11.c: New test. * gcc.target/riscv/rvv/base/vxrm-12.c: New test. --- gcc/config/riscv/riscv.cc | 29 ++++++++++++++++++- .../gcc.target/riscv/rvv/base/vxrm-11.c | 20 +++++++++++++ .../gcc.target/riscv/rvv/base/vxrm-12.c | 18 ++++++++++++ 3 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 09fc9e5d95e..26c78078981 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7549,6 +7549,31 @@ riscv_mode_needed (int entity, rtx_insn *insn) } } +/* Return true if the VXRM/FRM status of the INSN is unknown. */ +static bool +global_state_unknown_p (rtx_insn *insn, unsigned int regno) +{ + struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); + df_ref ref; + + /* Return true if there is a definition of VXRM. */ + for (ref = DF_INSN_INFO_DEFS (insn_info); ref; ref = DF_REF_NEXT_LOC (ref)) + if (DF_REF_REGNO (ref) == regno) + return true; + + /* A CALL function may contain an instruction that modifies the VXRM, + return true in this situation. */ + if (recog_memoized (insn) >= 0 && CALL_P (insn)) + return true; + + /* Return true for all assembly since users may hardcode a assembly + like this: asm volatile ("csrwi vxrm, 0"). */ + extract_insn (insn); + if (recog_data.is_asm) + return true; + return false; +} + /* Return the mode that an insn results in. */ static int @@ -7557,7 +7582,9 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn) switch (entity) { case RISCV_VXRM: - if (recog_memoized (insn) >= 0) + if (global_state_unknown_p (insn, VXRM_REGNUM)) + return VXRM_MODE_NONE; + else if (recog_memoized (insn) >= 0) return reg_mentioned_p (gen_rtx_REG (SImode, VXRM_REGNUM), PATTERN (insn)) ? get_attr_vxrm_mode (insn) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c new file mode 100644 index 00000000000..7f637a8b7f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void fn (void); + +void f (void * in, void *out, int32_t x, int n, int m) +{ + for (int i = 0; i < n; i++) { + vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); + fn (); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4); + } +} + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c new file mode 100644 index 00000000000..c3ab509f106 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void f (void * in, void *out, int32_t x, int n, int m) +{ + for (int i = 0; i < n; i++) { + vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4); + vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4); + asm volatile ("csrwi\tvxrm,1"); + v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4); + __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4); + } +} + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 2 } } */