From patchwork Wed May 24 09:41:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1785653 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=I0iCNC5g; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QR5nP5lWYz20Pb for ; Wed, 24 May 2023 19:42:17 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0DA003857714 for ; Wed, 24 May 2023 09:42:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from s01.bc.larksuite.com (s01.bc.larksuite.com [209.127.230.13]) by sourceware.org (Postfix) with UTF8SMTPS id A27D13857715 for ; Wed, 24 May 2023 09:41:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A27D13857715 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921272; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=pvu/S+3bYH/Ci/svQLAIj1CuriD/gFOqR+Ey03tjJ/w=; b=I0iCNC5g7fmF1fQsTgSiUjTzHe16TeE5atIOs5DogluJG3oFbH+ZH0hZsHHuc/gEJJet9K g5XgSZSYrtBAnTTaOV8mwmFmkW4bKhOlQLaEATz88NMm3SzR6PXvgSwU6wnsFDKZAoMIAO Rq+hcbIfcs8v8b2Xafrp29TBPnIZQTUkWf4ethYKFjt3nmPWUmib459pC+qkoR2sG7krPS hNyaMsF7DdSeR0LcYTsg6rz4FCNrZ1lfFbs5UbjlhDBKo/3hdeoFaaqWD5khwglPQSYFRz Dex6GKjaMMsZ9qjJS/19gT6WSJjfw/mDs5wYlNrVdEI56uQZFWSQU8cOY4qzLw== To: Cc: "YunQiang Su" , "Maciej W . Rozycki" X-Mailer: git-send-email 2.40.1 Subject: [PATCH v3 1/9] MIPS: Add basic support for mips16e2 Date: Wed, 24 May 2023 17:41:11 +0800 References: Message-Id: <200d163cccf88fadc85927562ae54ae1275fe7e5.1684918168.git.jie.mei@oss.cipunited.com> Mime-Version: 1.0 In-Reply-To: From: "Jie Mei" X-Lms-Return-Path: X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. It defines new special instructions for increasing code density (e.g. Extend, PC-relative instructions, etc.). This patch adds basic support for mips16e2 used by the following series of patches. gcc/ChangeLog: * config/mips/mips.cc(mips_file_start): Add mips16e2 info for output file. * config/mips/mips.h(__mips_mips16e2): Defined a new predefine macro. (ISA_HAS_MIPS16E2): Defined a new macro. (ASM_SPEC): Pass mmips16e2 to the assembler. * config/mips/mips.opt: Add -m(no-)mips16e2 option. * config/mips/predicates.md: Add clause for TARGET_MIPS16E2. * doc/invoke.texi: Add -m(no-)mips16e2 option.. gcc/testsuite/ChangeLog: * gcc.target/mips/mips.exp(mips_option_groups): Add -mmips16e2 option. (mips-dg-init): Handle the recognization of mips16e2 targets. (mips-dg-options): Add dependencies for mips16e2. --- gcc/config/mips/mips.cc | 3 ++- gcc/config/mips/mips.h | 8 ++++++++ gcc/config/mips/mips.opt | 4 ++++ gcc/config/mips/predicates.md | 2 +- gcc/doc/invoke.texi | 7 +++++++ gcc/testsuite/gcc.target/mips/mips.exp | 10 ++++++++++ 6 files changed, 32 insertions(+), 2 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index ca822758b41..585a3682c7b 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -10047,7 +10047,8 @@ mips_file_start (void) fputs ("\t.module\tmsa\n", asm_out_file); if (TARGET_XPA) fputs ("\t.module\txpa\n", asm_out_file); - /* FIXME: MIPS16E2 is not supported by GCC? gas does support it */ + if (TARGET_MIPS16E2) + fputs ("\t.module\tmips16e2\n", asm_out_file); if (TARGET_CRC) fputs ("\t.module\tcrc\n", asm_out_file); if (TARGET_GINV) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 6daf6d37165..c6781670a54 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -475,6 +475,9 @@ struct mips_cpu_info { if (mips_base_compression_flags & MASK_MIPS16) \ builtin_define ("__mips16"); \ \ + if (TARGET_MIPS16E2) \ + builtin_define ("__mips_mips16e2"); \ + \ if (TARGET_MIPS3D) \ builtin_define ("__mips3d"); \ \ @@ -1291,6 +1294,10 @@ struct mips_cpu_info { /* The MSA ASE is available. */ #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16) +/* The MIPS16e V2 instructions are available. */ +#define ISA_HAS_MIPS16E2 (TARGET_MIPS16 && TARGET_MIPS16E2 \ + && !TARGET_64BIT) + /* True if the result of a load is not available to the next instruction. A nop will then be needed between instructions like "lw $4,..." and "addiu $4,$4,1". */ @@ -1450,6 +1457,7 @@ struct mips_cpu_info { %{msym32} %{mno-sym32} \ %{mtune=*}" \ FP_ASM_SPEC "\ +%{mmips16e2} \ %(subtarget_asm_spec)" /* Extra switches sometimes passed to the linker. */ diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 195f5be01cc..4968ed0d544 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -380,6 +380,10 @@ msplit-addresses Target Mask(SPLIT_ADDRESSES) Optimize lui/addiu address loads. +mmips16e2 +Target Var(TARGET_MIPS16E2) Init(0) +Enable the MIPS16e V2 instructions. + msym32 Target Var(TARGET_SYM32) Assume all symbols have 32-bit values. diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md index e34de2937cc..87460a64652 100644 --- a/gcc/config/mips/predicates.md +++ b/gcc/config/mips/predicates.md @@ -369,7 +369,7 @@ { /* When generating mips16 code, TARGET_LEGITIMATE_CONSTANT_P rejects CONST_INTs that can't be loaded using simple insns. */ - if (TARGET_MIPS16) + if (TARGET_MIPS16 && !TARGET_MIPS16E2) return false; /* Don't handle multi-word moves this way; we don't want to introduce diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ee78591c73e..1fa00594a91 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -26735,6 +26735,13 @@ MIPS16 code generation can also be controlled on a per-function basis by means of @code{mips16} and @code{nomips16} attributes. @xref{Function Attributes}, for more information. +@opindex mmips16e2 +@opindex mno-mips16e2 +@item -mmips16e2 +@itemx -mno-mips16e2 +Use (do not use) the MIPS16e2 ASE. This option modifies the behavior +of the @option{-mips16} option such that it targets the MIPS16e2 ASE@. + @opindex mflip-mips16 @item -mflip-mips16 Generate MIPS16 code on alternating functions. This option is provided diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 15d574202d3..e79f685ceb0 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -301,6 +301,7 @@ foreach option { loongson-mmi loongson-ext loongson-ext2 + mips16e2 } { lappend mips_option_groups $option "-m(no-|)$option" } @@ -821,6 +822,12 @@ proc mips-dg-init {} { "-mno-mips16", #endif + #ifdef __mips_mips16e2 + "-mmips16e2", + #else + "-mno-mips16e2", + #endif + #ifdef __mips3d "-mips3d", #else @@ -1038,6 +1045,7 @@ proc mips-dg-options { args } { # dependency diagram. mips_option_dependency options "-mips16" "-mno-micromips" mips_option_dependency options "-mmicromips" "-mno-mips16" + mips_option_dependency options "-mmicromips" "-mno-mips16e2" mips_option_dependency options "-mips3d" "-mpaired-single" mips_option_dependency options "-mips3d" "-mno-micromips" mips_option_dependency options "-mpaired-single" "-mfp64" @@ -1417,6 +1425,7 @@ proc mips-dg-options { args } { mips_make_test_option options "-mfp32" } mips_make_test_option options "-mno-dsp" + mips_make_test_option options "-mno-mips16e2" mips_make_test_option options "-mno-synci" mips_make_test_option options "-mno-micromips" mips_make_test_option options "-mnan=legacy" @@ -1449,6 +1458,7 @@ proc mips-dg-options { args } { # Handle dependencies between options on the right of the diagram. mips_option_dependency options "-mno-dsp" "-mno-dspr2" + mips_option_dependency options "-mno-mips16" "-mno-mips16e2" mips_option_dependency options "-mno-explicit-relocs" "-mgpopt" switch -- [mips_test_option options small-data] { "" - From patchwork Wed May 24 09:41:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1785652 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=uMHMODFq; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QR5nD3fjZz20Pb for ; Wed, 24 May 2023 19:42:08 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 20DCA382E6B8 for ; Wed, 24 May 2023 09:42:04 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from s01.bc.larksuite.com (s01.bc.larksuite.com [209.127.230.13]) by sourceware.org (Postfix) with UTF8SMTPS id 60A2C3857704 for ; Wed, 24 May 2023 09:41:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 60A2C3857704 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921274; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=xb67mRnXDzfxN+5ds8mKCL6S/H9malu5JnoOcAE5Hcs=; b=uMHMODFqoWbqSaZKprFIzujTvixycZnOue6Ot/rKExSYE+qB/HHooxfbYD94jvv+gxcGOa 7sz3GUF1Q7stZkGZUB+qphfUS9sbuGf4EP3GF2ZmojD2av7EHPOFuUSmFul9mU46MTylAq GHzhH1ibQc3Tmab7RJ3RUwU+f4s1fx8DCEFZFkSqkrmHB3BmK9Ji+SYoEZeHq2QNFbLCVB jvQTGGjs8PlzzLAENPzpOZgXfNEzZ01bLWl4IsQvw4fs1tWkwcUtLcgRPRENLMop95TXAp 6ZzXT9pVk2nGTC45lHObp5Erfd8CHTN9gduQ2Bm/iis2CJQ4rP241jnYtriIRw== Subject: [PATCH v3 2/9] MIPS: Add MOVx instructions support for mips16e2 X-Mailer: git-send-email 2.40.1 Cc: "YunQiang Su" , "Maciej W . Rozycki" From: "Jie Mei" Date: Wed, 24 May 2023 17:41:13 +0800 References: In-Reply-To: To: Message-Id: <8e0c8971407e0ad350476051e8061172ed706f33.1684918168.git.jie.mei@oss.cipunited.com> Mime-Version: 1.0 X-Lms-Return-Path: X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds MOVx instructions from mips16e2 (movn,movz,movtn,movtz) with corresponding tests. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for ISA_HAS_MIPS16E2. * config/mips/mips.md(*mov_on_): Add logics for MOVx insts. (*mov_on__mips16e2): Generate MOVx instruction. (*mov_on__ne): Add logics for MOVx insts. (*mov_on__ne_mips16e2): Generate MOVx instruction. * config/mips/predicates.md(reg_or_0_operand_mips16e2): New predicate for MOVx insts. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-cmov.c: Added tests for MOVx instructions. --- gcc/config/mips/mips.h | 1 + gcc/config/mips/mips.md | 38 ++++++++++- gcc/config/mips/predicates.md | 6 ++ gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 68 +++++++++++++++++++ 4 files changed, 111 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cmov.c diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index c6781670a54..a94b253e898 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1081,6 +1081,7 @@ struct mips_cpu_info { ST Loongson 2E/2F. */ #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \ || TARGET_MIPS5900 \ + || ISA_HAS_MIPS16E2 \ || TARGET_LOONGSON_2EF) /* ISA has LDC1 and SDC1. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index ac1d77afc7d..48d5f419ce0 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -7341,26 +7341,60 @@ (const_int 0)]) (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] - "ISA_HAS_CONDMOVE" + "!TARGET_MIPS16 && ISA_HAS_CONDMOVE" "@ mov%T4\t%0,%z2,%1 mov%t4\t%0,%z3,%1" [(set_attr "type" "condmove") (set_attr "mode" "")]) +(define_insn "*mov_on__mips16e2" + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") + (if_then_else:GPR + (match_operator 4 "equality_operator" + [(match_operand:MOVECC 1 "register_operand" ",,t,t") + (const_int 0)]) + (match_operand:GPR 2 "reg_or_0_operand_mips16e2" "dJ,0,dJ,0") + (match_operand:GPR 3 "reg_or_0_operand_mips16e2" "0,dJ,0,dJ")))] + "ISA_HAS_MIPS16E2 && ISA_HAS_CONDMOVE" + "@ + mov%T4\t%0,%z2,%1 + mov%t4\t%0,%z3,%1 + movt%T4\t%0,%z2 + movt%t4\t%0,%z3" + [(set_attr "type" "condmove") + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) + (define_insn "*mov_on__ne" [(set (match_operand:GPR 0 "register_operand" "=d,d") (if_then_else:GPR (match_operand:GPR2 1 "register_operand" ",") (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] - "ISA_HAS_CONDMOVE" + "!TARGET_MIPS16 && ISA_HAS_CONDMOVE" "@ movn\t%0,%z2,%1 movz\t%0,%z3,%1" [(set_attr "type" "condmove") (set_attr "mode" "")]) +(define_insn "*mov_on__ne_mips16e2" + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") + (if_then_else:GPR + (match_operand:GPR2 1 "register_operand" ",,t,t") + (match_operand:GPR 2 "reg_or_0_operand_mips16e2" "dJ,0,dJ,0") + (match_operand:GPR 3 "reg_or_0_operand_mips16e2" "0,dJ,0,dJ")))] + "ISA_HAS_MIPS16E2 && ISA_HAS_CONDMOVE" + "@ + movn\t%0,%z2,%1 + movz\t%0,%z3,%1 + movtn\t%0,%z2 + movtz\t%0,%z3" + [(set_attr "type" "condmove") + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) + (define_insn "*mov_on_" [(set (match_operand:SCALARF 0 "register_operand" "=f,f") (if_then_else:SCALARF diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md index 87460a64652..e2cd5a8c65f 100644 --- a/gcc/config/mips/predicates.md +++ b/gcc/config/mips/predicates.md @@ -114,6 +114,12 @@ (not (match_test "TARGET_MIPS16"))) (match_operand 0 "register_operand"))) +(define_predicate "reg_or_0_operand_mips16e2" + (ior (and (match_operand 0 "const_0_operand") + (ior (not (match_test "TARGET_MIPS16")) + (match_test "ISA_HAS_MIPS16E2"))) + (match_operand 0 "register_operand"))) + (define_predicate "const_1_operand" (and (match_code "const_int,const_double,const_vector") (match_test "op == CONST1_RTX (GET_MODE (op))"))) diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c new file mode 100644 index 00000000000..6e9dd82ebf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c @@ -0,0 +1,68 @@ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* Test MOVN. */ + +/* { dg-final { scan-assembler-times "test01:.*\tmovn\t.*test01\n" 1 } } */ +int +test01 (int a, int b, int c) +{ + return (a==0) ? b : c; +} + +/* { dg-final { scan-assembler-times "test02:.*\tmovn\t\\\$.,\\\$0.*test02\n" 1 } } */ +int +test02 (int a, int b, int c) +{ + return (a==0) ? b : 0; +} + +/* Test MOVZ. */ + +/* { dg-final { scan-assembler-times "test03:.*\tmovz\t.*test03\n" 1 } } */ +int +test03 (int a, int b, int c) +{ + return a ? b : c; +} + +/* { dg-final { scan-assembler-times "test04:.*\tmovz\t\\\$.,\\\$0.*test04\n" 1 } } */ +int +test04 (int a, int b, int c) +{ + return a ? b : 0; +} + +/* Test MOVTN. */ + +/* { dg-final { scan-assembler-times "test05:.*\tmovtn\t.*test05\n" 1 } } */ +int +test05 (int a, int b, int c, int d) +{ + return a >= b ? c : d; +} + +/* { dg-final { scan-assembler-times "test06:.*\tmovtn\t\\\$2,\\\$0.*test06\n" 1 } } */ +int +test06 (int a, int b, int c, int d) +{ + return a >= b ? c : 0; +} + +/* Test MOVTZ. */ + +/* { dg-final { scan-assembler-times "test07:.*\tmovtz\t.*test07\n" 1 } } */ +int +test07 (int a, int b, int c, int d) +{ + return a < b ? c : d; +} + +/* { dg-final { scan-assembler-times "test08:.*\tmovtz\t\\\$.,\\\$0.*test08\n" 1 } } */ +int +test08 (int a, int b, int c, int d) +{ + return a < b ? c : 0; +} + + From patchwork Wed May 24 09:41:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1785655 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=cjSxm5Zv; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QR5p66bGlz20Pb for ; Wed, 24 May 2023 19:42:54 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E8D06381A894 for ; Wed, 24 May 2023 09:42:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.34]) by sourceware.org (Postfix) with UTF8SMTPS id 33BCD3858414 for ; Wed, 24 May 2023 09:41:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 33BCD3858414 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921276; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=rsb/1Lzga1LNtUMcBouqGWhEdqpkXaPqAi3bHFrnUbY=; b=cjSxm5Zv6LEbjcRgL0UC3G1hdRg6DKML5tEwz+sgsJ2tO8n4+NV+ugnrCOBds6YD9QLuV3 ca26xiXQcUOszSg/9UXscBDgVJLoNEC/HrPwuOzDPJB7ORiyq0Yn6m1r2UNW4B/2nPJbz/ SQ542DRMAjrmSryinkDT4lN+Au4Mjdr0cqJjLK+fruoUH290ga9w93wjLXDic/CPg47voG bSV36gvI23GKojgMeJc+Bb/x82vksRQAjFKRCVVcQ2NoT6zZcuEPyX9aNQ9REsIk5VVnxi Djw127XibVfERvs7akApYhliCYwsevDkMr3Z7YVoF3pAbsq7Ln1FVTqxD1JjQw== Subject: [PATCH v3 3/9] MIPS: Add instruction about global pointer register for mips16e2 X-Mailer: git-send-email 2.40.1 To: References: From: "Jie Mei" Date: Wed, 24 May 2023 17:41:15 +0800 Mime-Version: 1.0 In-Reply-To: X-Lms-Return-Path: Cc: "YunQiang Su" , "Maciej W . Rozycki" Message-Id: X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, HTML_NONELEMENT_30_40, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The mips16e2 ASE uses eight general-purpose registers from mips32, with some special-purpose registers, these registers are GPRs: s0-1, v0-1, a0-3, and special registers: t8, gp, sp, ra. As mentioned above, the special register gp is used in mips16e2, which is the global pointer register, it is used by some of the instructions in the ASE, for instance, ADDIU, LB/LBU, etc. . This patch adds these instructions with corresponding tests. gcc/ChangeLog: * config/mips/mips.cc(mips_regno_mode_ok_for_base_p): Generate instructions that uses global pointer register. (mips16_unextended_reference_p): Same as above. (mips_pic_base_register): Same as above. (mips_init_relocs): Same as above. * config/mips/mips.h(MIPS16_GP_LOADS): Defined a new macro. (GLOBAL_POINTER_REGNUM): Moved to machine description `mips.md`. * config/mips/mips.md(GLOBAL_POINTER_REGNUM): Moved to here from above. (*lowsi_mips16_gp):New `define_insn *low_mips16`. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-gp.c: New tests for mips16e2. --- gcc/config/mips/mips.cc | 10 +- gcc/config/mips/mips.h | 6 +- gcc/config/mips/mips.md | 11 +++ gcc/testsuite/gcc.target/mips/mips16e2-gp.c | 101 ++++++++++++++++++++ 4 files changed, 121 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-gp.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 585a3682c7b..be470bbb50d 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2474,6 +2474,9 @@ mips_regno_mode_ok_for_base_p (int regno, machine_mode mode, if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM) return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8; + if (MIPS16_GP_LOADS && regno == GLOBAL_POINTER_REGNUM) + return (UNITS_PER_WORD > 4 ? GET_MODE_SIZE (mode) <= 4 : true); + return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); } @@ -2689,7 +2692,8 @@ static bool mips16_unextended_reference_p (machine_mode mode, rtx base, unsigned HOST_WIDE_INT offset) { - if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0) + if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0 + && REGNO (base) != GLOBAL_POINTER_REGNUM) { if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx) return offset < 256U * GET_MODE_SIZE (mode); @@ -3249,7 +3253,7 @@ mips16_gp_pseudo_reg (void) rtx mips_pic_base_register (rtx temp) { - if (!TARGET_MIPS16) + if (MIPS16_GP_LOADS ||!TARGET_MIPS16) return pic_offset_table_rtx; if (currently_expanding_to_rtl) @@ -8756,7 +8760,7 @@ mips_init_relocs (void) } } - if (TARGET_MIPS16) + if (!MIPS16_GP_LOADS && TARGET_MIPS16) { /* The high part is provided by a pseudo copy of $gp. */ mips_split_p[SYMBOL_GP_RELATIVE] = true; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index a94b253e898..3ec33fbba71 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1375,6 +1375,8 @@ struct mips_cpu_info { /* ISA includes the pop instruction. */ #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) +#define MIPS16_GP_LOADS (ISA_HAS_MIPS16E2 && !TARGET_64BIT) + /* The CACHE instruction is available in non-MIPS16 code. */ #define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3) @@ -2067,10 +2069,6 @@ FP_ASM_SPEC "\ function address than to call an address kept in a register. */ #define NO_FUNCTION_CSE 1 -/* The ABI-defined global pointer. Sometimes we use a different - register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ -#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) - /* We normally use $28 as the global pointer. However, when generating n32/64 PIC, it is better for leaf functions to use a call-clobbered register instead. They can then avoid saving and restoring $28 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 48d5f419ce0..9de5013aad1 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -167,6 +167,7 @@ (GET_FCSR_REGNUM 2) (SET_FCSR_REGNUM 4) (PIC_FUNCTION_ADDR_REGNUM 25) + (GLOBAL_POINTER_REGNUM 28) (RETURN_ADDR_REGNUM 31) (CPRESTORE_SLOT_REGNUM 76) (GOT_VERSION_REGNUM 79) @@ -4678,6 +4679,16 @@ [(set_attr "alu_type" "add") (set_attr "mode" "")]) +(define_insn "*lowsi_mips16_gp" + [(set (match_operand:SI 0 "register_operand" "=d") + (lo_sum:SI (reg:SI GLOBAL_POINTER_REGNUM) + (match_operand 1 "immediate_operand" "")))] + "MIPS16_GP_LOADS" + "addiu\t%0,$28,%R1" + [(set_attr "alu_type" "add") + (set_attr "mode" "SI") + (set_attr "extended_mips16" "yes")]) + (define_insn "*low_mips16" [(set (match_operand:P 0 "register_operand" "=d") (lo_sum:P (match_operand:P 1 "register_operand" "0") diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c new file mode 100644 index 00000000000..7955472bde3 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c @@ -0,0 +1,101 @@ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */ +/* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */ + +/* Generate GP-relative ADDIU. */ + +/* { dg-final { scan-assembler "test01:.*\taddiu\t\\\$2,\\\$28.*test01\n" } } */ +int arr[2]; + +int * +test01 (void) +{ + return (&arr[1]); +} + +/* Test LB[GP]. */ + +/* { dg-final { scan-assembler "test02:.*\tlb\t.*\\\$28.*test02\n" } } */ +signed char c02; + +signed char +test02 (void) +{ + return c02; +} + +/* Test LBU[GP]. */ + +/* { dg-final { scan-assembler "test03:.*\tlbu\t.*\\\$28.*test03\n" } } */ +unsigned char uc03; + +unsigned char +test03 (void) +{ + return uc03; +} + +/* Test LH[GP]. */ + +/* { dg-final { scan-assembler "test04:.*\tlh\t.*\\\$28.*test04\n" } } */ +short s04; + +short +test04 (void) +{ + return s04; +} + +/* Test LHU[GP]. */ + +/* { dg-final { scan-assembler "test05:.*\tlhu\t.*\\\$28.*test05\n" } } */ +unsigned short s05; + +unsigned short +test05 (void) +{ + return s05; +} + +/* Test LW[GP]. */ + +/* { dg-final { scan-assembler "test06:.*\tlw\t.*\\\$28.*test06\n" } } */ +int i06; + +int +test06 (void) +{ + return i06; +} + +/* Test SB[GP]. */ + +/* { dg-final { scan-assembler "test07:.*\tsb\t.*\\\$28.*test07\n" } } */ +char c07; + +void +test07 (char x) +{ + c07 = x; +} + +/* Test SH[GP]. */ + +/* { dg-final { scan-assembler "test08:.*\tsh\t.*\\\$28.*test08\n" } } */ +short s08; + +void +test08 (short x) +{ + s08 = x; +} + +/* Test SW[GP]. */ + +/* { dg-final { scan-assembler "test09:.*\tsw\t.*\\\$28.*test09\n" } } */ +int i09; + +void +test09 (int x) +{ + i09 = x; +} From patchwork Wed May 24 09:41:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1785650 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=nrf6WqZB; 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Rozycki" Subject: [PATCH v3 4/9] MIPS: Add bitwise instructions for mips16e2 Date: Wed, 24 May 2023 17:41:16 +0800 In-Reply-To: To: X-Mailer: git-send-email 2.40.1 X-Lms-Return-Path: References: From: "Jie Mei" Message-Id: Mime-Version: 1.0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" There are shortened bitwise instructions in the mips16e2 ASE, for instance, ANDI, ORI/XORI, EXT, INS etc. . This patch adds these instrutions with corresponding tests. gcc/ChangeLog: * config/mips/constraints.md(Yz): New constraints for mips16e2. * config/mips/mips-protos.h(mips_bit_clear_p): Declared new function. (mips_bit_clear_info): Same as above. * config/mips/mips.cc(mips_bit_clear_info): New function for generating instructions. (mips_bit_clear_p): Same as above. * config/mips/mips.h(ISA_HAS_EXT_INS): Add clause for ISA_HAS_MIPS16E2. * config/mips/mips.md(extended_mips16): Generates EXT and INS instructions. (*and3): Generates INS instruction. (*and3_mips16): Generates EXT, INS and ANDI instructions. (ior3): Add logics for ORI instruction. (*ior3_mips16_asmacro): Generates ORI instrucion. (*ior3_mips16): Add logics for XORI instruction. (*xor3_mips16): Generates XORI instrucion. (*extzv): Add logics for EXT instruction. (*insv): Add logics for INS instruction. * config/mips/predicates.md(bit_clear_operand): New predicate for generating bitwise instructions. (and_reg_operand): Add logics for generating bitwise instructions. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: New tests for mips16e2. --- gcc/config/mips/constraints.md | 4 + gcc/config/mips/mips-protos.h | 4 + gcc/config/mips/mips.cc | 67 ++++++++++++++- gcc/config/mips/mips.h | 3 +- gcc/config/mips/mips.md | 91 ++++++++++++++++---- gcc/config/mips/predicates.md | 13 ++- gcc/testsuite/gcc.target/mips/mips16e2.c | 102 +++++++++++++++++++++++ 7 files changed, 263 insertions(+), 21 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2.c diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index 49d1a43c613..22d4d84f074 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -264,6 +264,10 @@ (and (match_code "const_vector") (match_test "op == CONST0_RTX (mode)"))) +(define_constraint "Yz" + "@internal" + (match_operand 0 "bit_clear_operand")) + (define_constraint "YA" "@internal An unsigned 6-bit constant." diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 20483469105..2791b9f220a 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -388,4 +388,8 @@ extern void mips_register_frame_header_opt (void); extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *); extern void mips_expand_vec_cmp_expr (rtx *); +extern bool mips_bit_clear_p (enum machine_mode, unsigned HOST_WIDE_INT); +extern void mips_bit_clear_info (enum machine_mode, unsigned HOST_WIDE_INT, + int *, int *); + #endif /* ! GCC_MIPS_PROTOS_H */ diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index be470bbb50d..d86911d10c2 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -3895,6 +3895,10 @@ mips16_constant_cost (int code, HOST_WIDE_INT x) return 0; return -1; + case ZERO_EXTRACT: + /* The bit position and size are immediate operands. */ + return ISA_HAS_EXT_INS ? COSTS_N_INSNS (1) : -1; + default: return -1; } @@ -22753,7 +22757,68 @@ mips_asm_file_end (void) if (NEED_INDICATE_EXEC_STACK) file_end_indicate_exec_stack (); } - + +void +mips_bit_clear_info (enum machine_mode mode, unsigned HOST_WIDE_INT m, + int *start_pos, int *size) +{ + unsigned int shift = 0; + unsigned int change_count = 0; + unsigned int prev_val = 1; + unsigned int curr_val = 0; + unsigned int end_pos = GET_MODE_SIZE (mode) * BITS_PER_UNIT; + + for (shift = 0 ; shift < (GET_MODE_SIZE (mode) * BITS_PER_UNIT) ; shift++) + { + curr_val = (unsigned int)((m & (unsigned int)(1 << shift)) >> shift); + if (curr_val != prev_val) + { + change_count++; + switch (change_count) + { + case 1: + *start_pos = shift; + break; + case 2: + end_pos = shift; + break; + default: + gcc_unreachable (); + } + } + prev_val = curr_val; + } + *size = (end_pos - *start_pos); +} + +bool +mips_bit_clear_p (enum machine_mode mode, unsigned HOST_WIDE_INT m) +{ + unsigned int shift = 0; + unsigned int change_count = 0; + unsigned int prev_val = 1; + unsigned int curr_val = 0; + + if (mode != SImode && mode != VOIDmode) + return false; + + if (!ISA_HAS_EXT_INS) + return false; + + for (shift = 0 ; shift < (UNITS_PER_WORD * BITS_PER_UNIT) ; shift++) + { + curr_val = (unsigned int)((m & (unsigned int)(1 << shift)) >> shift); + if (curr_val != prev_val) + change_count++; + prev_val = curr_val; + } + + if (change_count == 2) + return true; + + return false; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 3ec33fbba71..eefe2aa0910 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1266,7 +1266,8 @@ struct mips_cpu_info { #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16) /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ -#define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16) +#define ISA_HAS_EXT_INS ((mips_isa_rev >= 2 && !TARGET_MIPS16) \ + || ISA_HAS_MIPS16E2) /* ISA has instructions for accessing top part of 64-bit fp regs. */ #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 9de5013aad1..9f652310aa2 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -461,7 +461,7 @@ (if_then_else (ior ;; In general, constant-pool loads are extended ;; instructions. We don't yet optimize for 16-bit ;; PC-relative references. - (eq_attr "move_type" "sll0,loadpool") + (eq_attr "move_type" "sll0,loadpool,ext_ins") (eq_attr "jal" "direct") (eq_attr "got" "load")) (const_string "yes") @@ -3312,12 +3312,13 @@ ;; register =op1 x (define_insn "*and3" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d") - (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d") - (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Uean,K,Yx,Yw,!u,d")))] + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d,d") + (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d,0") + (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Uean,K,Yx,Yw,!u,d,Yz")))] "!TARGET_MIPS16 && and_operands_ok (mode, operands[1], operands[2])" { int len; + int pos; switch (which_alternative) { @@ -3342,20 +3343,28 @@ case 7: case 8: return "and\t%0,%1,%2"; + case 9: + mips_bit_clear_info (mode, INTVAL (operands[2]), &pos, &len); + operands[1] = GEN_INT (pos); + operands[2] = GEN_INT (len); + return "ins\t%0,$0,%1,%2"; default: gcc_unreachable (); } } - [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical") - (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*") + [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical,ext_ins") + (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*,*") (set_attr "mode" "")]) (define_insn "*and3_mips16" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d") - (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0") - (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))] + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d,d") + (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0,d,0,0?") + (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d,Yx,Yz,K")))] "TARGET_MIPS16 && and_operands_ok (mode, operands[1], operands[2])" { + int len; + int pos; + switch (which_alternative) { case 0: @@ -3371,12 +3380,32 @@ return "#"; case 4: return "and\t%0,%2"; + case 5: + len = low_bitmask_len (mode, INTVAL (operands[2])); + operands[2] = GEN_INT (len); + return "ext\t%0,%1,0,%2"; + case 6: + mips_bit_clear_info (mode, INTVAL (operands[2]), &pos, &len); + operands[1] = GEN_INT (pos); + operands[2] = GEN_INT (len); + return "ins\t%0,$0,%1,%2"; + case 7: + return "andi\t%0,%x2"; default: gcc_unreachable (); } } - [(set_attr "move_type" "load,load,load,shift_shift,logical") - (set_attr "mode" "")]) + [(set_attr "move_type" "load,load,load,shift_shift,logical,ext_ins,ext_ins,andi") + (set_attr "mode" "") + (set_attr "extended_mips16" "no,no,no,no,no,yes,yes,yes") + (set (attr "enabled") + (cond [(and (eq_attr "alternative" "7") + (not (match_test "ISA_HAS_MIPS16E2"))) + (const_string "no") + (and (eq_attr "alternative" "0,1") + (match_test "!GENERATE_MIPS16E")) + (const_string "no")] + (const_string "yes")))]) (define_expand "ior3" [(set (match_operand:GPR 0 "register_operand") @@ -3384,7 +3413,7 @@ (match_operand:GPR 2 "uns_arith_operand")))] "" { - if (TARGET_MIPS16) + if (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) operands[2] = force_reg (mode, operands[2]); }) @@ -3401,11 +3430,23 @@ (set_attr "compression" "micromips,*,*") (set_attr "mode" "")]) +(define_insn "*ior3_mips16_asmacro" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (ior:GPR (match_operand:GPR 1 "register_operand" "%0,0") + (match_operand:GPR 2 "uns_arith_operand" "d,K")))] + "ISA_HAS_MIPS16E2" + "@ + or\t%0,%2 + ori\t%0,%x2" + [(set_attr "alu_type" "or") + (set_attr "mode" "") + (set_attr "extended_mips16" "*,yes")]) + (define_insn "*ior3_mips16" [(set (match_operand:GPR 0 "register_operand" "=d") (ior:GPR (match_operand:GPR 1 "register_operand" "%0") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_MIPS16" + "TARGET_MIPS16 && !ISA_HAS_MIPS16E2" "or\t%0,%2" [(set_attr "alu_type" "or") (set_attr "mode" "")]) @@ -3430,19 +3471,31 @@ (set_attr "compression" "micromips,*,*") (set_attr "mode" "")]) +;; We increase statically the cost of the output register for XORI +;; to counterweight LRA cost calculation as XORI tends to be chosen +;; frequently hurting the code size. The reason of not choosing CMPI is +;; that LRA tends to add up the cost of the T register as it is in a small +;; class and a possible reload. In reality, the use of T register comes for +;; free in a number of cases as we don't need any MIPS16 registers. (define_insn "*xor3_mips16" - [(set (match_operand:GPR 0 "register_operand" "=d,t,t,t") - (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d,d") - (match_operand:GPR 2 "uns_arith_operand" "d,Uub8,K,d")))] + [(set (match_operand:GPR 0 "register_operand" "=d,t,t,t,d?") + (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d,d,0") + (match_operand:GPR 2 "uns_arith_operand" "d,Uub8,K,d,K")))] "TARGET_MIPS16" "@ xor\t%0,%2 cmpi\t%1,%2 cmpi\t%1,%2 - cmp\t%1,%2" + cmp\t%1,%2 + xori\t%0,%x2" [(set_attr "alu_type" "xor") (set_attr "mode" "") - (set_attr "extended_mips16" "no,no,yes,no")]) + (set_attr "extended_mips16" "no,no,yes,no,yes") + (set (attr "enabled") + (cond [(and (eq_attr "alternative" "4") + (not (match_test "ISA_HAS_MIPS16E2"))) + (const_string "no")] + (const_string "yes")))]) (define_insn "*nor3" [(set (match_operand:GPR 0 "register_operand" "=d") @@ -4342,6 +4395,7 @@ INTVAL (operands[3]))" "ext\t%0,%1,%3,%2" [(set_attr "type" "arith") + (set_attr "extended_mips16" "yes") (set_attr "mode" "")]) (define_insn "*extzv_truncsi_exts" @@ -4392,6 +4446,7 @@ INTVAL (operands[2]))" "ins\t%0,%z3,%2,%1" [(set_attr "type" "arith") + (set_attr "extended_mips16" "yes") (set_attr "mode" "")]) ;; Combiner pattern for cins (clear and insert bit field). We can diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md index e2cd5a8c65f..eabe322cc1d 100644 --- a/gcc/config/mips/predicates.md +++ b/gcc/config/mips/predicates.md @@ -170,6 +170,10 @@ (and (match_code "const_int") (match_test "UINTVAL (op) == 0xffffffff"))) +(define_predicate "bit_clear_operand" + (and (match_code "const_int") + (match_test "mips_bit_clear_p (mode, INTVAL (op))"))) + (define_predicate "and_load_operand" (ior (match_operand 0 "qi_mask_operand") (match_operand 0 "hi_mask_operand") @@ -184,8 +188,15 @@ (ior (match_operand 0 "register_operand") (and (not (match_test "TARGET_MIPS16")) (match_operand 0 "const_uns_arith_operand")) + (and (match_test "ISA_HAS_MIPS16E2") + (match_operand 0 "const_uns_arith_operand") + (not (match_operand 0 "hi_mask_operand")) + (not (match_operand 0 "qi_mask_operand"))) + (and (match_test "ISA_HAS_MIPS16E2") + (match_operand 0 "const_uns_arith_operand")) (match_operand 0 "low_bitmask_operand") - (match_operand 0 "si_mask_operand"))) + (match_operand 0 "si_mask_operand") + (match_operand 0 "bit_clear_operand"))) (define_predicate "and_operand" (ior (match_operand 0 "and_load_operand") diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.target/mips/mips16e2.c new file mode 100644 index 00000000000..ce8b4f1819b --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips16e2.c @@ -0,0 +1,102 @@ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */ +/* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */ + +/* ANDI is a two operand instruction. Hence, it won't be generated if src and + * dest are in different registers. */ + +/* { dg-final { scan-assembler "test01:.*\tandi\t.*test01\n" } } */ +unsigned int +test01 (unsigned int a) +{ + return ((a + 0x2) & 0x3ff); +} + +/* Test EXT */ + +/* { dg-final { scan-assembler "test02:.*\text\t.*test02\n" } } */ +struct +{ + unsigned int a:9; + unsigned int d:31; + unsigned int e:9; + unsigned int f:10; +} t02; + +unsigned int +test02 (void) +{ + return t02.f; +} + +/* Use EXT when ANDing with low-order bitmasks. */ + +/* { dg-final { scan-assembler "test03:.*\text\t.*test03\n" } } */ +/* { dg-final { scan-assembler-not "test03.*\tandi?\t.*test03\n" } } */ +unsigned int +test03 (unsigned int x) +{ + return (x & 0x1fffffff); +} + +/* Test INS */ + +/* { dg-final { scan-assembler "test04:.*\tins\t.*test04\n" } } */ +struct +{ + unsigned int i : 9; + unsigned int j : 15; + unsigned int k : 4; +} s04; + +void +test04 (void) +{ + s04.j = 1; +} + +/* Use INS with hardcoded $0. */ + +/* { dg-final { scan-assembler "test05:.*\tins\t\\\$.*,\\\$0.*test05\n" } } */ +struct +{ + unsigned int i : 8; + unsigned int j : 9; + unsigned int k : 10; +} __attribute__ ((packed)) s05 __attribute__((aligned(1))); + +void +test05 (void) +{ + s05.k = 0; +} + +/* Use INS when ANDing to clear only one consecutive chunk of bits. */ + +/* { dg-final { scan-assembler "test06:.*\tins\t\\\$.*,\\\$0,11,5.*test06\n" } } */ +/* { dg-final { scan-assembler-not "test06:.*\tandi?\t.*test06\n" } } */ +unsigned int +test06 (unsigned int x) +{ + return (x & 0xffff07ff); +} + +/* ORI is a two operand instruction. Hence, it won't be generated if src and + dest are in different registers. */ + +/* { dg-final { scan-assembler "test07:.*\tori\t.*test07\n" } } */ +unsigned int +test07 (unsigned int a) +{ + return (a + 0x2) | 0x7f0; +} + +/* XORI is a two operand instruction. Hence, it won't be generated if src and + dest are in different registers. */ + +/* { dg-final { scan-assembler "test08:.*\txori\t.*test08\n" } } */ +unsigned int +test08 (unsigned int a) +{ + return ((a + 0x2) ^ 0x3f0); +} + From patchwork Wed May 24 09:41:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1785651 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=CD4PnVhy; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QR5ml3Dcsz20dp for ; Wed, 24 May 2023 19:41:43 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7030A3882039 for ; Wed, 24 May 2023 09:41:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from s01.bc.larksuite.com (s01.bc.larksuite.com [209.127.230.14]) by sourceware.org (Postfix) with UTF8SMTPS id 349083856241 for ; Wed, 24 May 2023 09:41:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 349083856241 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921279; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=47q9iI4Jv+t2/c57MqvrE7+PNXqp3XEtOFaM+gox4xk=; b=CD4PnVhyOuFVIec7fFUEMt5EAvR8gJTpdU9vQ/ZWdRS5nbS5hBmY7Hp5F9yJ1u2LuuhUWp f3oMa/WrWa3RPemHiJSSFel8uZayf9kgzFVs2RVYGYcZXYke0wlve7ibopryKASd8rbQcb o7dejyDALXwfA+EZyrqCPF8ld5wn1Ld5ndErYQRNjbRDmOh5zjnv7ZxuBrvyQqqFWVUp4F alMfhtQRVU7f0CGQYa3LnqbMp2BmEWdPip2JYfC1nlZHqm7BchCPVVPv5UYc2i2z5oKAEE GSCuiVHd2E0sZZQVf6/64utC3LHTC1qmHIaDkSnYGsJ+FGiG5y3tpzaKWSRf3A== Cc: "YunQiang Su" , "Maciej W . Rozycki" Message-Id: Mime-Version: 1.0 In-Reply-To: From: "Jie Mei" References: X-Mailer: git-send-email 2.40.1 To: Subject: [PATCH v3 5/9] MIPS: Add LUI instruction for mips16e2 Date: Wed, 24 May 2023 17:41:18 +0800 X-Lms-Return-Path: X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds LUI instruction from mips16e2 with corresponding test. gcc/ChangeLog: * config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction. (mips_const_insns): Same as above. (mips_output_move): Same as above. (mips_output_function_prologue): Same as above. * config/mips/mips.md: Same as above gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: Add new tests for mips16e2. --- gcc/config/mips/mips.cc | 44 ++++++++++++++++++------ gcc/config/mips/mips.md | 2 +- gcc/testsuite/gcc.target/mips/mips16e2.c | 22 ++++++++++++ 3 files changed, 56 insertions(+), 12 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index d86911d10c2..0792f89cab4 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2295,7 +2295,9 @@ mips_symbol_insns_1 (enum mips_symbol_type type, machine_mode mode) The final address is then $at + %lo(symbol). With 32-bit symbols we just need a preparatory LUI for normal mode and a preparatory LI and SLL for MIPS16. */ - return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2; + return ABI_HAS_64BIT_SYMBOLS + ? 6 + : (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) ? 3 : 2; case SYMBOL_GP_RELATIVE: /* Treat GP-relative accesses as taking a single instruction on @@ -2867,7 +2869,7 @@ mips_const_insns (rtx x) /* This is simply an LUI for normal mode. It is an extended LI followed by an extended SLL for MIPS16. */ - return TARGET_MIPS16 ? 4 : 1; + return TARGET_MIPS16 ? (ISA_HAS_MIPS16E2 ? 2 : 4) : 1; case CONST_INT: if (TARGET_MIPS16) @@ -2879,7 +2881,10 @@ mips_const_insns (rtx x) : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2 : IN_RANGE (-INTVAL (x), 0, 255) ? 2 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3 - : 0); + : ISA_HAS_MIPS16E2 + ? (trunc_int_for_mode (INTVAL (x), SImode) == INTVAL (x) + ? 4 : 8) + : 0); return mips_build_integer (codes, INTVAL (x)); @@ -5252,6 +5257,11 @@ mips_output_move (rtx dest, rtx src) if (!TARGET_MIPS16) return "li\t%0,%1\t\t\t# %X1"; + if (ISA_HAS_MIPS16E2 + && LUI_INT (src) + && !SMALL_OPERAND_UNSIGNED (INTVAL (src))) + return "lui\t%0,%%hi(%1)\t\t\t# %X1"; + if (SMALL_OPERAND_UNSIGNED (INTVAL (src))) return "li\t%0,%1"; @@ -5260,7 +5270,7 @@ mips_output_move (rtx dest, rtx src) } if (src_code == HIGH) - return TARGET_MIPS16 ? "#" : "lui\t%0,%h1"; + return (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) ? "#" : "lui\t%0,%h1"; if (CONST_GP_P (src)) return "move\t%0,%1"; @@ -11983,13 +11993,25 @@ mips_output_function_prologue (FILE *file) { if (TARGET_MIPS16) { - /* This is a fixed-form sequence. The position of the - first two instructions is important because of the - way _gp_disp is defined. */ - output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); - output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); - output_asm_insn ("sll\t$2,16", 0); - output_asm_insn ("addu\t$2,$3", 0); + if (ISA_HAS_MIPS16E2) + { + /* This is a fixed-form sequence. The position of the + first two instructions is important because of the + way _gp_disp is defined. */ + output_asm_insn ("lui\t$2,%%hi(_gp_disp)", 0); + output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); + output_asm_insn ("addu\t$2,$3", 0); + } + else + { + /* This is a fixed-form sequence. The position of the + first two instructions is important because of the + way _gp_disp is defined. */ + output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); + output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); + output_asm_insn ("sll\t$2,16", 0); + output_asm_insn ("addu\t$2,$3", 0); + } } else { diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 9f652310aa2..73c9acd484f 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4634,7 +4634,7 @@ (define_split [(set (match_operand:P 0 "d_operand") (high:P (match_operand:P 1 "symbolic_operand_with_high")))] - "TARGET_MIPS16 && reload_completed" + "TARGET_MIPS16 && reload_completed && !ISA_HAS_MIPS16E2" [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH)) (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))]) diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.target/mips/mips16e2.c index ce8b4f1819b..780891b4056 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2.c @@ -100,3 +100,25 @@ test08 (unsigned int a) return ((a + 0x2) ^ 0x3f0); } +/* Test LUI. */ + +/* { dg-final { scan-assembler "test09:.*\tlui\t.*test09\n" } } */ +int +test09 (void) +{ + return 0x44440000; +} + +/* Test LUI relocation sequence chang. */ + +/* { dg-final { scan-assembler "test10:.*\tlui\t.*test10\n" } } */ +int *a10; + +int +test10 (int i) +{ + a10 = &i; + *a10 = 0x44440000; + return i; +} + From patchwork Wed May 24 09:41:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1785654 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=qP93p7r3; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QR5nt4N4nz20Pb for ; Wed, 24 May 2023 19:42:42 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 68C753894C20 for ; Wed, 24 May 2023 09:42:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.34]) by sourceware.org (Postfix) with UTF8SMTPS id 96DD538560B6 for ; Wed, 24 May 2023 09:41:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 96DD538560B6 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921280; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=DY8i46yGO2YnAVQfLao5RkFtmC4WvyT1aCgeyUTIGJ0=; b=qP93p7r309ER7KA/m5+9x+LWAgRoRzmYNcQSw9l3/T4jTcqpfGbZk19gz41zbA08ljsqqZ EvhdZmJGSA929AeTawSScmJpakPAGWwndrCro1EcX4wOgg1zWB9pFYAr6xpKztMU+Y80iE oAn4MRz8BXS3TZQu4RvupDna2ox1/9adm8Yjakt9RDbCH7sWQkuyAdst3BOHikZIAOoyGe z4pj/q7n0pZCpaY4DbmKq8ubRBPj67VeUYkP8mJbWQ40O2zREAv7+6GutW4CBslykftcWg jFqXJV/ivIdPsm+TT49IIsvxslV7rvAXoXZzK+wUsYuh1WpxtipMCRBZTZY4VA== In-Reply-To: Cc: "YunQiang Su" , "Maciej W . Rozycki" Subject: [PATCH v3 6/9] MIPS: Add load/store word left/right instructions for mips16e2 Date: Wed, 24 May 2023 17:41:19 +0800 Mime-Version: 1.0 To: From: "Jie Mei" Message-Id: <4dcc4535d30655302abfdc354fc786c28bed4b91.1684918169.git.jie.mei@oss.cipunited.com> X-Lms-Return-Path: X-Mailer: git-send-email 2.40.1 References: X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds LWL/LWR, SWL/SWR instructions with their corresponding tests. gcc/ChangeLog: * config/mips/mips.cc(mips_expand_ins_as_unaligned_store): Add logics for generating instruction. * config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2. * config/mips/mips.md(mov_l): Generates instructions. (mov_r): Same as above. (mov_l): Adjusted for the conditions above. (mov_r): Same as above. (mov_l_mips16e2): Add machine description for `define_insn mov_l_mips16e2`. (mov_r_mips16e2): Add machine description for `define_insn mov_r_mips16e2`. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: New tests for mips16e2. --- gcc/config/mips/mips.cc | 15 ++- gcc/config/mips/mips.h | 2 +- gcc/config/mips/mips.md | 43 +++++++-- gcc/testsuite/gcc.target/mips/mips16e2.c | 116 +++++++++++++++++++++++ 4 files changed, 168 insertions(+), 8 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 0792f89cab4..275efc5a390 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -8603,12 +8603,25 @@ mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width, return false; mode = int_mode_for_size (width, 0).require (); - src = gen_lowpart (mode, src); + if (TARGET_MIPS16 + && src == const0_rtx) + src = force_reg (mode, src); + else + src = gen_lowpart (mode, src); + if (mode == DImode) { + if (TARGET_MIPS16) + gcc_unreachable (); emit_insn (gen_mov_sdl (dest, src, left)); emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right)); } + else if (TARGET_MIPS16) + { + emit_insn (gen_mov_swl_mips16e2 (dest, src, left)); + emit_insn (gen_mov_swr_mips16e2 (copy_rtx (dest), copy_rtx (src), + right)); + } else { emit_insn (gen_mov_swl (dest, src, left)); diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index eefe2aa0910..b6c100060da 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1180,7 +1180,7 @@ struct mips_cpu_info { && (MODE) == V2SFmode)) \ && !TARGET_MIPS16) -#define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16) +#define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 73c9acd484f..5ef8d99d99c 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4488,10 +4488,12 @@ (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") (match_operand:QI 2 "memory_operand" "ZC")] UNSPEC_LOAD_LEFT))] - "!TARGET_MIPS16 && mips_mem_fits_mode_p (mode, operands[1])" + "(!TARGET_MIPS16 || ISA_HAS_MIPS16E2) + && mips_mem_fits_mode_p (mode, operands[1])" "l\t%0,%2" [(set_attr "move_type" "load") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) (define_insn "mov_r" [(set (match_operand:GPR 0 "register_operand" "=d") @@ -4499,17 +4501,20 @@ (match_operand:QI 2 "memory_operand" "ZC") (match_operand:GPR 3 "register_operand" "0")] UNSPEC_LOAD_RIGHT))] - "!TARGET_MIPS16 && mips_mem_fits_mode_p (mode, operands[1])" + "(!TARGET_MIPS16 || ISA_HAS_MIPS16E2) + && mips_mem_fits_mode_p (mode, operands[1])" "r\t%0,%2" [(set_attr "move_type" "load") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) (define_insn "mov_l" [(set (match_operand:BLK 0 "memory_operand" "=m") (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") (match_operand:QI 2 "memory_operand" "ZC")] UNSPEC_STORE_LEFT))] - "!TARGET_MIPS16 && mips_mem_fits_mode_p (mode, operands[0])" + "!TARGET_MIPS16 + && mips_mem_fits_mode_p (mode, operands[0])" "l\t%z1,%2" [(set_attr "move_type" "store") (set_attr "mode" "")]) @@ -4520,11 +4525,37 @@ (match_operand:QI 2 "memory_operand" "ZC") (match_dup 0)] UNSPEC_STORE_RIGHT))] - "!TARGET_MIPS16 && mips_mem_fits_mode_p (mode, operands[0])" + "!TARGET_MIPS16 + && mips_mem_fits_mode_p (mode, operands[0])" "r\t%z1,%2" [(set_attr "move_type" "store") (set_attr "mode" "")]) +(define_insn "mov_l_mips16e2" + [(set (match_operand:BLK 0 "memory_operand" "=m") + (unspec:BLK [(match_operand:GPR 1 "register_operand" "d") + (match_operand:QI 2 "memory_operand" "ZC")] + UNSPEC_STORE_LEFT))] + "TARGET_MIPS16 && ISA_HAS_MIPS16E2 + && mips_mem_fits_mode_p (mode, operands[0])" + "l\t%1,%2" + [(set_attr "move_type" "store") + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) + +(define_insn "mov_r_mips16e2" + [(set (match_operand:BLK 0 "memory_operand" "+m") + (unspec:BLK [(match_operand:GPR 1 "register_operand" "d") + (match_operand:QI 2 "memory_operand" "ZC") + (match_dup 0)] + UNSPEC_STORE_RIGHT))] + "TARGET_MIPS16 && ISA_HAS_MIPS16E2 + && mips_mem_fits_mode_p (mode, operands[0])" + "r\t%1,%2" + [(set_attr "move_type" "store") + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) + ;; Unaligned direct access (define_expand "movmisalign" [(set (match_operand:JOIN_MODE 0) diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.target/mips/mips16e2.c index 780891b4056..166aa742268 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2.c @@ -122,3 +122,119 @@ test10 (int i) return i; } +/* Test 32bit unaligned load. */ + +/* { dg-final { scan-assembler "test11:.*\tlwl\t.*test11\n" } } */ +/* { dg-final { scan-assembler "test11:.*\tlwr\t.*test11\n" } } */ +struct node11 +{ + char c; + int i; +} __attribute__ ((packed)) obj11 __attribute__((aligned(1))); + +int +test11 (void) +{ + return obj11.i; +} + +/* Test 32bit unaligned load. */ + +/* { dg-final { scan-assembler "test12:.*\tlwl\t.*test12\n" } } */ +/* { dg-final { scan-assembler "test12:.*\tlwr\t.*test12\n" } } */ +struct node12 +{ + unsigned int i : 8; + unsigned int j : 32; +} __attribute__ ((packed)) obj12 __attribute__((aligned(16))); + +int +test12 (void) +{ + return obj12.j; +} + +/* Test 32bit unaligned store with non-zero constant */ + +/* { dg-final { scan-assembler "test13:.*\tswl\t.*test13\n" } } */ +/* { dg-final { scan-assembler "test13:.*\tswr\t.*test13\n" } } */ +struct node13 +{ + char c; + int i; +} __attribute__ ((packed)) obj13 __attribute__((aligned(1))); + +void +test13 (void) +{ + obj13.i = 1234; +} + +/* Test 32bit unaligned store with zero constant. */ + +/* { dg-final { scan-assembler "test14:.*\tswl\t.*test14\n" } } */ +/* { dg-final { scan-assembler "test14:.*\tswr\t.*test14\n" } } */ +/* { dg-final { scan-assembler-not "test14:.*\tswl\t\\\$0,.*test14\n" } } */ +/* { dg-final { scan-assembler-not "test14:.*\tswr\t\\\$0,.*test14\n" } } */ +struct node14 +{ + char c; + int i; +} __attribute__ ((packed)) obj14 __attribute__((aligned(1))); + +void +test14 (void) +{ + obj14.i = 0; +} + +/* Test 32bit unaligned store with non-constant. */ + +/* { dg-final { scan-assembler "test15:.*\tswl\t.*test15\n" } } */ +/* { dg-final { scan-assembler "test15:.*\tswr\t.*test15\n" } } */ +struct node15 +{ + char c; + int i; +} __attribute__ ((packed)) obj15 __attribute__((aligned(1))); + +int i15 = 1234; + +void +test15 (void) +{ + obj15.i = i15; +} + +/* Test 32bit unaligned store with non-constant */ + +/* { dg-final { scan-assembler "test16:.*\tswl\t.*test16\n" } } */ +/* { dg-final { scan-assembler "test16:.*\tswr\t.*test16\n" } } */ +struct node16 +{ + char c; + int i; +} __attribute__ ((packed)) obj16 __attribute__((aligned(1))); + +void +test16 (int i) +{ + obj16.i = i; +} + +/* Test 32bit unaligned store with non-constant. */ + +/* { dg-final { scan-assembler "test17:.*\tswl\t.*test17\n" } } */ +/* { dg-final { scan-assembler "test17:.*\tswr\t.*test17\n" } } */ +struct node17 +{ + unsigned int i : 8; + unsigned int j : 32; +} __attribute__ ((packed)) obj17 __attribute__((aligned(16))); + +void +test17 (int i) +{ + obj17.j = i; +} + From patchwork Wed May 24 09:41:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1785656 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Rozycki" Date: Wed, 24 May 2023 17:41:21 +0800 Message-Id: <0ac6b0c13cfd5465a6ce38a5f04fc172e4ffb7da.1684918169.git.jie.mei@oss.cipunited.com> Subject: [PATCH v3 7/9] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 Mime-Version: 1.0 X-Mailer: git-send-email 2.40.1 References: X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_NUMSUBJECT, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The MIPS16e2 ASE has PREF, LL and SC instructions, they use 9 bits immediate, like mips32r6. The MIPS32 PRE-R6 uses 16 bits immediate. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause for ISA_HAS_MIPS16E2. (ISA_HAS_SYNC): Same as above. (ISA_HAS_LL_SC): Same as above. --- gcc/config/mips/mips.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index b6c100060da..f50b279af33 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1247,7 +1247,8 @@ struct mips_cpu_info { && !TARGET_MIPS16) /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */ -#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6) +#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6 \ + || ISA_HAS_MIPS16E2) /* ISA has data indexed prefetch instructions. This controls use of 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. @@ -1340,7 +1341,8 @@ struct mips_cpu_info { #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16) /* ISA includes sync. */ -#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) && !TARGET_MIPS16) +#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define GENERATE_SYNC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ @@ -1349,7 +1351,8 @@ struct mips_cpu_info { /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC instructions. */ -#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 && !TARGET_MIPS16) +#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define GENERATE_LL_SC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ From patchwork Wed May 24 09:41:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1785657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=MAhixqw/; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QR5pn0d6kz20Pb for ; Wed, 24 May 2023 19:43:29 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2A7DD3857437 for ; Wed, 24 May 2023 09:43:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.36]) by sourceware.org (Postfix) with UTF8SMTPS id BA29F38555A4 for ; Wed, 24 May 2023 09:41:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BA29F38555A4 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921283; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=JYEmLF4gplG37KZd6/v7mDZx7S4gT5uqAFX3O7TvGBA=; b=MAhixqw//ZIKwuEztR9dkZtiXFbY1ZwyTcZ3u8E5oTsgt9VB/g53sl1J9/jiEY3y/bPPCr VnXL7N93vzorGy4Czf4whIHlIwOcnqIqabPwVQEFb55Ym7QqWL1fI9M2UguP/N5LSwwNcj hDTnSNFOYFTAvNV2TRVBhBAhK8UMLsRJbjafDxu1Scj27judds+sZd4M+fWx2MnLbTdanf KRrR9RbImyTn/EzUL3wV1LGGCGDpgOe+YU8JsDYG1vHp6QuPW6PtCEnqLZF/X97zgSoUST qqXcM376ZmpKYxOkkCTvZFO+ArSEqb+KXDsuE9IYdwv2krHgsy/TN3adSYM6+w== Message-Id: <8b1e378dd44da420d2a7e6c2691f1d809066c422.1684918169.git.jie.mei@oss.cipunited.com> Mime-Version: 1.0 References: X-Mailer: git-send-email 2.40.1 Subject: [PATCH v3 8/9] MIPS: Add CACHE instruction for mips16e2 From: "Jie Mei" Cc: "YunQiang Su" , "Maciej W . Rozycki" Date: Wed, 24 May 2023 17:41:22 +0800 In-Reply-To: X-Lms-Return-Path: To: X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds CACHE instruction from mips16e2 with corresponding tests. gcc/ChangeLog: * config/mips/mips.c(mips_9bit_offset_address_p): Restrict the address register to M16_REGS for MIPS16. (BUILTIN_AVAIL_MIPS16E2): Defined a new macro. (AVAIL_MIPS16E2_OR_NON_MIPS16): Same as above. (AVAIL_NON_MIPS16 (cache..)): Update to AVAIL_MIPS16E2_OR_NON_MIPS16. * config/mips/mips.h (ISA_HAS_CACHE): Add clause for ISA_HAS_MIPS16E2. * config/mips/mips.md (mips_cache): Mark as extended MIPS16. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-cache.c: New tests for mips16e2. --- gcc/config/mips/mips.cc | 25 ++++++++++++-- gcc/config/mips/mips.h | 3 +- gcc/config/mips/mips.md | 3 +- .../gcc.target/mips/mips16e2-cache.c | 34 +++++++++++++++++++ 4 files changed, 60 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cache.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 275efc5a390..e6f4701ad3a 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2845,6 +2845,9 @@ mips_9bit_offset_address_p (rtx x, machine_mode mode) return (mips_classify_address (&addr, x, mode, false) && addr.type == ADDRESS_REG && CONST_INT_P (addr.offset) + && (!TARGET_MIPS16E2 + || M16_REG_P (REGNO (addr.reg)) + || REGNO (addr.reg) >= FIRST_PSEUDO_REGISTER) && MIPS_9BIT_OFFSET_P (INTVAL (addr.offset))); } @@ -15412,9 +15415,13 @@ mips_loongson_ext2_prefetch_cookie (rtx write, rtx) The function is available on the current target if !TARGET_MIPS16. BUILTIN_AVAIL_MIPS16 - The function is available on the current target if TARGET_MIPS16. */ + The function is available on the current target if TARGET_MIPS16. + + BUILTIN_AVAIL_MIPS16E2 + The function is available on the current target if TARGET_MIPS16E2. */ #define BUILTIN_AVAIL_NON_MIPS16 1 #define BUILTIN_AVAIL_MIPS16 2 +#define BUILTIN_AVAIL_MIPS16E2 4 /* Declare an availability predicate for built-in functions that require non-MIPS16 mode and also require COND to be true. @@ -15426,6 +15433,17 @@ mips_loongson_ext2_prefetch_cookie (rtx write, rtx) return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \ } +/* Declare an availability predicate for built-in functions that + require non-MIPS16 mode or MIPS16E2 and also require COND to be true. + NAME is the main part of the predicate's name. */ +#define AVAIL_MIPS16E2_OR_NON_MIPS16(NAME, COND) \ + static unsigned int \ + mips_builtin_avail_##NAME (void) \ + { \ + return ((COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16E2 \ + : 0); \ + } + /* Declare an availability predicate for built-in functions that support both MIPS16 and non-MIPS16 code and also require COND to be true. NAME is the main part of the predicate's name. */ @@ -15471,7 +15489,7 @@ AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP) AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP) AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI) -AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) +AVAIL_MIPS16E2_OR_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) AVAIL_NON_MIPS16 (msa, TARGET_MSA) /* Construct a mips_builtin_description from the given arguments. @@ -17471,7 +17489,8 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, d = &mips_builtins[fcode]; avail = d->avail (); gcc_assert (avail != 0); - if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16)) + if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16) + && (!TARGET_MIPS16E2 || !(avail & BUILTIN_AVAIL_MIPS16E2))) { error ("built-in function %qE not supported for MIPS16", DECL_NAME (fndecl)); diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index f50b279af33..c29c5a8543d 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1385,7 +1385,8 @@ struct mips_cpu_info { #define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3) /* The CACHE instruction is available. */ -#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) +#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && (!TARGET_MIPS16 \ + || TARGET_MIPS16E2)) /* Tell collect what flags to pass to nm. */ #ifndef NM_FLAGS diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 5ef8d99d99c..7eb65891820 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -5751,7 +5751,8 @@ (match_operand:QI 1 "address_operand" "ZD")] UNSPEC_MIPS_CACHE))] "ISA_HAS_CACHE" - "cache\t%X0,%a1") + "cache\t%X0,%a1" + [(set_attr "extended_mips16" "yes")]) ;; Similar, but with the operands hard-coded to an R10K cache barrier ;; operation. We keep the pattern distinct so that we can identify diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c new file mode 100644 index 00000000000..dcc39b580f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c @@ -0,0 +1,34 @@ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips32r2 -mips16 -mmips16e2" } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* Test cache. */ + +void +test01 (int *area) +{ + __builtin_mips_cache (20, area); +} + +void +test02 (const short *area) +{ + __builtin_mips_cache (24, area + 10); +} + +void +test03 (volatile unsigned int *area, int offset) +{ + __builtin_mips_cache (0, area + offset); +} + +void +test04 (const volatile unsigned char *area) +{ + __builtin_mips_cache (4, area - 80); +} + +/* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t(0x|)0,0\\(\\\$.\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */ + From patchwork Wed May 24 09:41:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1785658 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=ELOPTgMe; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QR5qV5Jp4z20Pb for ; Wed, 24 May 2023 19:44:06 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C9B3B392AC1F for ; Wed, 24 May 2023 09:44:04 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from s02.bc.larksuite.com (s02.bc.larksuite.com [209.127.230.20]) by sourceware.org (Postfix) with UTF8SMTPS id CF3253857016 for ; Wed, 24 May 2023 09:41:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CF3253857016 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921284; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=tfHUlndUS9Ke/H/BH7Go1jTTKd2EhtlEyAPsB2QvChI=; b=ELOPTgMenpqFcFvPSrnUZqedugpvObsfmwBOP1XbXj+WpdhW1XeuicJ254KG2UX8nUjGIw WMHvB4W5U2/YTV32UOK62FOTdfZCOWgcgLEOsKotQvyq8I3C55nZZewtT7TYtW3wuM6cFE 8ExJrI/BZ3oNHUgy8Gz5XXI5a+3fFu98c0b9QZSbsdqoA48mZs9cl+jO2BRlun7QgRWhcE llt/S9T3sqaPF/bEGWBqgADqx5GQIx1LDNu7wKEjsHx1Y8swazRoxw+6NobX85CTx7nsuG c7mtGKsRI9L1IGDPnpdStoSCuDoMdFyyqQk+Z0oWnIZVd5ufh542RdeVsq6xUg== Cc: "YunQiang Su" , "Maciej W . Rozycki" Mime-Version: 1.0 X-Lms-Return-Path: From: "Jie Mei" Subject: [PATCH v3 9/9] MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions Message-Id: <7b8c006b3cd91120331c759b213bac49ad7a8286.1684918169.git.jie.mei@oss.cipunited.com> X-Mailer: git-send-email 2.40.1 To: Date: Wed, 24 May 2023 17:41:24 +0800 In-Reply-To: References: X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, HTML_NONELEMENT_30_40, KAM_DMARC_STATUS, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch allows mips16e2 acts the same with -O1~3 when generating ZEB/ZEH instead of ANDI under the -O0 option, which shrinks the code size. gcc/ChangeLog: * config/mips/mips.md(*and3_mips16): Generates ZEB/ZEH instructions. --- gcc/config/mips/mips.md | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 7eb65891820..85ed1735d83 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3357,9 +3357,9 @@ (set_attr "mode" "")]) (define_insn "*and3_mips16" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d,d") - (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0,d,0,0?") - (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d,Yx,Yz,K")))] + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d,d,d,d") + (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,W,W,W,d,0,d,0,0?") + (match_operand:GPR 2 "and_operand" "Yb,Yh,Yb,Yh,Yw,Yw,d,Yx,Yz,K")))] "TARGET_MIPS16 && and_operands_ok (mode, operands[1], operands[2])" { int len; @@ -3368,38 +3368,42 @@ switch (which_alternative) { case 0: + return "zeb\t%0"; + case 1: + return "zeh\t%0"; + case 2: operands[1] = gen_lowpart (QImode, operands[1]); return "lbu\t%0,%1"; - case 1: + case 3: operands[1] = gen_lowpart (HImode, operands[1]); return "lhu\t%0,%1"; - case 2: + case 4: operands[1] = gen_lowpart (SImode, operands[1]); return "lwu\t%0,%1"; - case 3: + case 5: return "#"; - case 4: + case 6: return "and\t%0,%2"; - case 5: + case 7: len = low_bitmask_len (mode, INTVAL (operands[2])); operands[2] = GEN_INT (len); return "ext\t%0,%1,0,%2"; - case 6: + case 8: mips_bit_clear_info (mode, INTVAL (operands[2]), &pos, &len); operands[1] = GEN_INT (pos); operands[2] = GEN_INT (len); return "ins\t%0,$0,%1,%2"; - case 7: + case 9: return "andi\t%0,%x2"; default: gcc_unreachable (); } } - [(set_attr "move_type" "load,load,load,shift_shift,logical,ext_ins,ext_ins,andi") + [(set_attr "move_type" "andi,andi,load,load,load,shift_shift,logical,ext_ins,ext_ins,andi") (set_attr "mode" "") - (set_attr "extended_mips16" "no,no,no,no,no,yes,yes,yes") + (set_attr "extended_mips16" "no,no,no,no,no,no,no,yes,yes,yes") (set (attr "enabled") - (cond [(and (eq_attr "alternative" "7") + (cond [(and (eq_attr "alternative" "9") (not (match_test "ISA_HAS_MIPS16E2"))) (const_string "no") (and (eq_attr "alternative" "0,1")