From patchwork Wed May 24 01:28:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 1785498 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QQtrX4kmBz20QL for ; Wed, 24 May 2023 11:29:16 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 647F73857714 for ; Wed, 24 May 2023 01:29:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id 6DDA93858D35 for ; Wed, 24 May 2023 01:28:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6DDA93858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp74t1684891730tbwpm3hh Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 24 May 2023 09:28:49 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: 239gR2IZrlskV9whLgMdy+9ET38zRG9CHFs4dDOqijZnSBucnd/8rQMtOZC3b /abgmEVHiWvrvIwdN0X5X6mqsxX9NduDVlOlRlrw5KhXH2B1NfA5G/3Q2wU08tU+UT/KGhb U5yMeYY0L7f4InO9w7+j9mPENz1g1TIQOyOWpoiRMC+JMwjUFka0XQ0/t08lkF1JzWIcmS3 k/eGkKL4qHt6vdLOTqMTJnZJLHpePG9MRhdYx+4tBE1fJuyDkcJyThs3muVu/6ZQHLHaJWk 1R5wcVD0LnWAVzRAttVw6uypzzfchcxdvbuNV7+0rH7jAmtLRA8y4Ia6YXF8IB/RnJzalQG RrQWP1Y5Do4QiEfn6q7K3TCS5hey8rvPIBCjRAUQHsc6EBtBnuP74O2L4D5frZ+AXG5zkgQ X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5240261946314646094 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH V2] RISC-V: Fix magic number of RVV auto-vectorization expander Date: Wed, 24 May 2023 09:28:48 +0800 Message-Id: <20230524012848.1097889-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong This simple patch fixes the magic number, remove magic number make codes more reasonable. Ok for trunk ? gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vec_series): Remove magic number. (expand_const_vector): Ditto. (legitimize_move): Ditto. (sew64_scalar_helper): Ditto. (expand_tuple_move): Ditto. (expand_vector_init_insert_elems): Ditto. * config/riscv/riscv.cc (vector_zero_call_used_regs): Ditto. Reviewed-by: Palmer Dabbelt Reviewed-by: Palmer Dabbelt --- gcc/config/riscv/riscv-v.cc | 53 +++++++++++++++++-------------------- gcc/config/riscv/riscv.cc | 2 +- 2 files changed, 26 insertions(+), 29 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 478a052a779..fa61a850a22 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -406,14 +406,14 @@ expand_vec_series (rtx dest, rtx base, rtx step) int shift = exact_log2 (INTVAL (step)); rtx shift_amount = gen_int_mode (shift, Pmode); insn_code icode = code_for_pred_scalar (ASHIFT, mode); - rtx ops[3] = {step_adj, vid, shift_amount}; - emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, ops); + rtx ops[] = {step_adj, vid, shift_amount}; + emit_vlmax_insn (icode, RVV_BINOP, ops); } else { insn_code icode = code_for_pred_scalar (MULT, mode); - rtx ops[3] = {step_adj, vid, step}; - emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, ops); + rtx ops[] = {step_adj, vid, step}; + emit_vlmax_insn (icode, RVV_BINOP, ops); } } @@ -428,8 +428,8 @@ expand_vec_series (rtx dest, rtx base, rtx step) { rtx result = gen_reg_rtx (mode); insn_code icode = code_for_pred_scalar (PLUS, mode); - rtx ops[3] = {result, step_adj, base}; - emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, ops); + rtx ops[] = {result, step_adj, base}; + emit_vlmax_insn (icode, RVV_BINOP, ops); emit_move_insn (dest, result); } } @@ -445,8 +445,8 @@ expand_const_vector (rtx target, rtx src) gcc_assert ( const_vec_duplicate_p (src, &elt) && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx))); - rtx ops[2] = {target, src}; - emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::RVV_UNOP, ops); + rtx ops[] = {target, src}; + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); return; } @@ -458,16 +458,14 @@ expand_const_vector (rtx target, rtx src) we use vmv.v.i instruction. */ if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src)) { - rtx ops[2] = {tmp, src}; - emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::RVV_UNOP, - ops); + rtx ops[] = {tmp, src}; + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); } else { elt = force_reg (elt_mode, elt); - rtx ops[2] = {tmp, elt}; - emit_vlmax_insn (code_for_pred_broadcast (mode), - riscv_vector::RVV_UNOP, ops); + rtx ops[] = {tmp, elt}; + emit_vlmax_insn (code_for_pred_broadcast (mode), RVV_UNOP, ops); } if (tmp != target) @@ -536,9 +534,8 @@ legitimize_move (rtx dest, rtx src) rtx tmp = gen_reg_rtx (mode); if (MEM_P (src)) { - rtx ops[2] = {tmp, src}; - emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::RVV_UNOP, - ops); + rtx ops[] = {tmp, src}; + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); } else emit_move_insn (tmp, src); @@ -548,8 +545,8 @@ legitimize_move (rtx dest, rtx src) if (satisfies_constraint_vu (src)) return false; - rtx ops[2] = {dest, src}; - emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::RVV_UNOP, ops); + rtx ops[] = {dest, src}; + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); return true; } @@ -813,7 +810,7 @@ sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx vl, *scalar_op = force_reg (scalar_mode, *scalar_op); rtx tmp = gen_reg_rtx (vector_mode); - rtx ops[3] = {tmp, *scalar_op, vl}; + rtx ops[] = {tmp, *scalar_op, vl}; riscv_vector::emit_nonvlmax_insn (code_for_pred_broadcast (vector_mode), riscv_vector::RVV_UNOP, ops); emit_vector_func (operands, tmp); @@ -1122,9 +1119,9 @@ expand_tuple_move (rtx *ops) if (fractional_p) { - rtx operands[3] = {subreg, mem, ops[4]}; - emit_vlmax_insn (code_for_pred_mov (subpart_mode), - riscv_vector::RVV_UNOP, operands); + rtx operands[] = {subreg, mem, ops[4]}; + emit_vlmax_insn (code_for_pred_mov (subpart_mode), RVV_UNOP, + operands); } else emit_move_insn (subreg, mem); @@ -1147,9 +1144,9 @@ expand_tuple_move (rtx *ops) if (fractional_p) { - rtx operands[3] = {mem, subreg, ops[4]}; - emit_vlmax_insn (code_for_pred_mov (subpart_mode), - riscv_vector::RVV_UNOP, operands); + rtx operands[] = {mem, subreg, ops[4]}; + emit_vlmax_insn (code_for_pred_mov (subpart_mode), RVV_UNOP, + operands); } else emit_move_insn (mem, subreg); @@ -1281,8 +1278,8 @@ expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, unsigned int unspec = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN; insn_code icode = code_for_pred_slide (unspec, mode); - rtx ops[3] = {target, target, builder.elt (i)}; - emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, ops); + rtx ops[] = {target, target, builder.elt (i)}; + emit_vlmax_insn (icode, RVV_BINOP, ops); } } diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e7300b2e97c..09fc9e5d95e 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7396,7 +7396,7 @@ vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) emitted_vlmax_vsetvl = true; } - rtx ops[3] = {target, CONST0_RTX (mode), vl}; + rtx ops[] = {target, CONST0_RTX (mode), vl}; riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::RVV_UNOP, ops);