From patchwork Fri Mar 23 16:34:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 890054 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="IX18golY"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4078Lb716Nz9s0v for ; Sat, 24 Mar 2018 03:36:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752324AbeCWQe7 (ORCPT ); Fri, 23 Mar 2018 12:34:59 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:45541 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751923AbeCWQe5 (ORCPT ); Fri, 23 Mar 2018 12:34:57 -0400 Received: by mail-pg0-f68.google.com with SMTP id y63so1635198pgy.12 for ; Fri, 23 Mar 2018 09:34:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IsEWvgJNcKsjkd8SgDGPMM8oASotOa0bRX2Uz5aPRz4=; b=IX18golYYwxoybZBqWn+4BmYlWXFwOSjf4yV7/E4+OlUJjx4JpIjT5dVYDJjvNOQqu oAUelX4VgJ2EWOq9Zgphlv/CdE6rqVvF5Jewga5jpXVbl3VxQ9/8W/jXC/yDrgEypLrL Ya34ldg6j76OYNGASoBiXdw3Tq8Umozam2fGk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IsEWvgJNcKsjkd8SgDGPMM8oASotOa0bRX2Uz5aPRz4=; b=JoQ6k/t9u8dvAbLSU9AE4Dq5Q1F/axwfXu/4MB+eDGljsJ/HdjMmT/x6Y8T2eFT72t Ht/KoQ95TqALTUHegp4BASk2Cz1kUFQL3Koq8bEcpL1vbOeyxxkltCoR0vmOPPJ+2LOO g2vKdQofTGMnd0bLDhYN94TZfuChZJUmG6D5wTHv1t/rMBKnXA63wGukP8RoDmI1IM2z U3YpcHn9MA5A3TzNEa6onRdiJ55PT6dgqBHU99+QdzGZ5tAtzLLujEdpNI4ZqGPb+H/W IgdiPQpvgPp4f1+/yqiZb+wwfzcQUSwwYmmr1UQlYjFW85JdaINoqsfMxU7qriIFGhAI plfw== X-Gm-Message-State: AElRT7F59+H9hLPSw6sW8Wxr8Ww8v9IP5HvvPeGMZHTi5Q9T/5jW4OmS T4vODo/JFuu75Ta4vpAuIqjqyg== X-Google-Smtp-Source: AG47ELs2UXdPd98Z9Mgxkyjerrplp698cKmP+M/g+F0CbCNntEqvZhXM4vFzKSQQ2uJ16TvEy81BbA== X-Received: by 10.99.96.19 with SMTP id u19mr20948540pgb.261.1521822896786; Fri, 23 Mar 2018 09:34:56 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id s78sm19131294pfa.161.2018.03.23.09.34.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Mar 2018 09:34:56 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Timur Tabi , Bjorn Andersson , Grant Likely , linux-gpio@vger.kernel.org, Andy Shevchenko Subject: [PATCH v4 1/5] dt-bindings: gpio: Add a gpio-reserved-ranges property Date: Fri, 23 Mar 2018 09:34:49 -0700 Message-Id: <20180323163453.96495-2-swboyd@chromium.org> X-Mailer: git-send-email 2.17.0.rc0.231.g781580f067-goog In-Reply-To: <20180323163453.96495-1-swboyd@chromium.org> References: <20180323163453.96495-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Stephen Boyd Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Introduce a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. Cc: Grant Likely Cc: Signed-off-by: Stephen Boyd Signed-off-by: Stephen Boyd Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/gpio/gpio.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index b5de08e3b1a2..a7c31de29362 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -151,9 +151,9 @@ in a lot of designs, some using all 32 bits, some using 18 and some using first 18 GPIOs, at local offset 0 .. 17, are in use. If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an -additional bitmask is needed to specify which GPIOs are actually in use, -and which are dummies. The bindings for this case has not yet been -specified, but should be specified if/when such hardware appears. +additional set of tuples is needed to specify which GPIOs are unusable, with +the gpio-reserved-ranges binding. This property indicates the start and size +of the GPIOs that can't be used. Optionally, a GPIO controller may have a "gpio-line-names" property. This is an array of strings defining the names of the GPIO lines going out of the @@ -178,6 +178,7 @@ gpio-controller@00000000 { gpio-controller; #gpio-cells = <2>; ngpios = <18>; + gpio-reserved-ranges = <0 4>, <12 2>; gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R", "LED G", "LED B", "Col A", "Col B", "Col C", "Col D", "Row A", "Row B", "Row C", "Row D", "NMI button", From patchwork Fri Mar 23 16:34:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 890055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="d9GjtxAW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4078Lm33n3z9s0w for ; Sat, 24 Mar 2018 03:36:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752394AbeCWQga (ORCPT ); Fri, 23 Mar 2018 12:36:30 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:38049 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751806AbeCWQe6 (ORCPT ); Fri, 23 Mar 2018 12:34:58 -0400 Received: by mail-pg0-f68.google.com with SMTP id a15so4775007pgn.5 for ; Fri, 23 Mar 2018 09:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FGqHvdtEXH6ISReSBpU2jC6lg7R0YUgxQtmnA6KZ8S4=; b=d9GjtxAWH2zckAHynuVgiDkZEqEVCoswJyDpNPao/Pgz84fDzPX5kGdI9hWy4l7DvH hNsWLgTmcvNp4zMHALicfuE8YGzglOqyJaqVYxtvDXD5LVYwIWGaXBErKxccegsiGq+i p58rs8jWwqH5izOZuSx7r1K5HXaOAEKHbOys8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FGqHvdtEXH6ISReSBpU2jC6lg7R0YUgxQtmnA6KZ8S4=; b=fMZ+JnNZmUug8+aHc97P0RghXIL+ErwT1rOsu73IIiReoblcb2jBfrFE22mKbwXqwA 4iHCymUNBXw1kfIc+qvD8GwfihTUjg2lhjdkbApoM68OY7it+zM3Ss8Iw0cTyg+Yc6Rj xZA2MG85NuMuhX7YXQtDVbDVnt2OsIi1gpETpbQ8LwIMDp2Y7uNOIhFiY9Z2gRYQhVNh 5qGjiSgsXSA1lOS2CVAuw3q3K5o22x4hh90fyveHOFDF7BPBca2XJ2r8sCHKMHL+8akI LsGjgdMZWBeG3s6A1tYo4ty7woUp2Tt/W8WeZz7w2T+0kQoyUK2T6CqGhyIWrNr97ALg +S0A== X-Gm-Message-State: AElRT7GcDQjfuFm4FGC/zZ244cfpjGOHjs2Tn63FLpT014emC1VXUL24 WE5Tznq/cWEkhoh0Cp2BeaS71w== X-Google-Smtp-Source: AG47ELskd6GPdfVEai96i1NCFmZKy0XqNCO1P8XlWuxYakj7ELOBtjBkFhje14MzbOEwrrSBagHUCQ== X-Received: by 10.99.4.3 with SMTP id 3mr1425708pge.147.1521822897775; Fri, 23 Mar 2018 09:34:57 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id s78sm19131294pfa.161.2018.03.23.09.34.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Mar 2018 09:34:57 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Timur Tabi , Bjorn Andersson , Grant Likely , linux-gpio@vger.kernel.org, Andy Shevchenko Subject: [PATCH v4 2/5] gpiolib: Extract mask allocation into subroutine Date: Fri, 23 Mar 2018 09:34:50 -0700 Message-Id: <20180323163453.96495-3-swboyd@chromium.org> X-Mailer: git-send-email 2.17.0.rc0.231.g781580f067-goog In-Reply-To: <20180323163453.96495-1-swboyd@chromium.org> References: <20180323163453.96495-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We're going to use similar code to allocate and set all the bits in a mask for valid gpios to use. Extract the code from the irqchip version so it can be reused. Signed-off-by: Stephen Boyd --- drivers/gpio/gpiolib.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index d66de67ef307..cc0e1519da45 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -337,6 +337,20 @@ static int gpiochip_set_desc_names(struct gpio_chip *gc) return 0; } +static unsigned long *gpiochip_allocate_mask(struct gpio_chip *chip) +{ + unsigned long *p; + + p = kcalloc(BITS_TO_LONGS(chip->ngpio), sizeof(long), GFP_KERNEL); + if (!p) + return NULL; + + /* Assume by default all GPIOs are valid */ + bitmap_fill(p, chip->ngpio); + + return p; +} + /* * GPIO line handle management */ @@ -1506,14 +1520,10 @@ static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip) if (!gpiochip->irq.need_valid_mask) return 0; - gpiochip->irq.valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio), - sizeof(long), GFP_KERNEL); + gpiochip->irq.valid_mask = gpiochip_allocate_mask(gpiochip); if (!gpiochip->irq.valid_mask) return -ENOMEM; - /* Assume by default all GPIOs are valid */ - bitmap_fill(gpiochip->irq.valid_mask, gpiochip->ngpio); - return 0; } From patchwork Fri Mar 23 16:34:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 890052 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="bsh2+MtB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4078LD1XvYz9s0w for ; Sat, 24 Mar 2018 03:36:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752257AbeCWQfo (ORCPT ); Fri, 23 Mar 2018 12:35:44 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:46604 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752318AbeCWQe7 (ORCPT ); Fri, 23 Mar 2018 12:34:59 -0400 Received: by mail-pl0-f65.google.com with SMTP id f5-v6so7734301plj.13 for ; Fri, 23 Mar 2018 09:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8a+2CNaXeAxl73qV9mKREYLkFBHIUoYQlPR+otQ5uao=; b=bsh2+MtBilBwnA1ToaOc1NZRboko42CA3UlM4h1EucTuxNmZC8sz+Bxw/hOEmUsj2s Fimra0WgPuXeJUDfU4Pv3aI7R7a7hV+QDfqzCJIpyUqc7+NH+6rRWRBjisKmfEx0D1BP U0zdK4nIMlCCT5Qzx/eM0d9eIaNQP1PHAaWt4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8a+2CNaXeAxl73qV9mKREYLkFBHIUoYQlPR+otQ5uao=; b=s5NPR+8zLrzuLXFV7sPj6oOrmupaoSrMDEtPfYrn40t4XVQbAlkz4lfrw6/FsdyMe3 SxG+Kh9Uu82McIp+D/YDwAn2Nl2UjyzPFaChQrP5AEfOHlJuxlbHUFulllJvEWiZx3UJ OSgKN/KKWz+uMHt68LKIbZvwbhSYx8HbkNWoeoOt9RqezuxKet8vFawgY8rJQJcU+rd/ GV5a6oPFHAlqvKfhDH79ZaV9hYgaYApEcGIkRZWqOB9t/QEjMcYTDoWOLArn+BaoIU7p /YPOki4BNrE1XiTYVc72jEiEwvGjRzKtlNXCKsK4dR4rIvMvaSRWji75SejWTyZtpFP4 D88Q== X-Gm-Message-State: AElRT7F4SbdyF9Zwbt249y0tFOqMRfyGxmDX8qlJCOO9bYRVq1WHSIUD G7CTVy+qOTcYCob9KtEXhGnWbw== X-Google-Smtp-Source: AG47ELurtOVrGk7sIWRHsYTZMGGbEH/p1yKHR031w9AK255350OCRD2Yl/nNoEZ0ZRhSx74jH4P8NQ== X-Received: by 2002:a17:902:8602:: with SMTP id f2-v6mr29850263plo.6.1521822898638; Fri, 23 Mar 2018 09:34:58 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id s78sm19131294pfa.161.2018.03.23.09.34.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Mar 2018 09:34:58 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Timur Tabi , Bjorn Andersson , Grant Likely , linux-gpio@vger.kernel.org, Andy Shevchenko Subject: [PATCH v4 3/5] gpiolib: Change bitmap allocation to kmalloc_array Date: Fri, 23 Mar 2018 09:34:51 -0700 Message-Id: <20180323163453.96495-4-swboyd@chromium.org> X-Mailer: git-send-email 2.17.0.rc0.231.g781580f067-goog In-Reply-To: <20180323163453.96495-1-swboyd@chromium.org> References: <20180323163453.96495-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We don't need to clear out these bits when we set them immediately after. Use kmalloc_array() to skip clearing the bits. Suggested-by: Andy Shevchenko Signed-off-by: Stephen Boyd --- drivers/gpio/gpiolib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index cc0e1519da45..db3788d17ba0 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -341,7 +341,7 @@ static unsigned long *gpiochip_allocate_mask(struct gpio_chip *chip) { unsigned long *p; - p = kcalloc(BITS_TO_LONGS(chip->ngpio), sizeof(long), GFP_KERNEL); + p = kmalloc_array(BITS_TO_LONGS(chip->ngpio), sizeof(*p), GFP_KERNEL); if (!p) return NULL; From patchwork Fri Mar 23 16:34:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 890051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="kfO73BxT"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4078Ks25wZz9s0v for ; Sat, 24 Mar 2018 03:35:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752453AbeCWQfl (ORCPT ); Fri, 23 Mar 2018 12:35:41 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:41728 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751632AbeCWQfA (ORCPT ); Fri, 23 Mar 2018 12:35:00 -0400 Received: by mail-pg0-f65.google.com with SMTP id m24so4765973pgv.8 for ; Fri, 23 Mar 2018 09:34:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FrKr6AWLDlFaFHlo+xRWa/n4P4IrEyRlW7IfDiPRycE=; b=kfO73BxT0MpewOvOFH1kuydZm+QZck59S1MZp2Kk6qFUU9iCOS6DK25ST/VFLyEXaT koGW3+qfSEZNnKO8JtSJwsw/Ml/MwdX7vh3i2BbnUxgHk3jZJBLSNXLLoSnj8YDj1/4i h0Az1NQEvGJ+xl9WLoM5okjwJdiYmsKQ2zm+E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FrKr6AWLDlFaFHlo+xRWa/n4P4IrEyRlW7IfDiPRycE=; b=Y6sQMXFRF3Pip0zqjyR/XHEwpH8wa+TylgKOI7l9/tvAkQ3qsIXVL8HAJtAhqFmnck vaBLbWLkRfeicBLGNmgYequPHceMVPrnMX6Y6fujRZtQisCDq9KB55Zto8+qR4UpqwLR twQScIlZRNglO+rq/wKRUZzhM3C7e4v51KLzEgRVs5OLvGmSE+oaxQIQ7s60//ae7hxH cK5PRBuQGjG9r3FGlZXuyB6oW+f1qofWbGnSSMEYvclZQV+HyhhRaJmXjfRRxqTm4AuX TwieET59idOiyafruPlMcpFkgirVjQn9jB9ZfWBXMlLtDAAxCTiatyNeIKDkAzRXvSAr rGbQ== X-Gm-Message-State: AElRT7E4t5DmMUR+TCJRMEu4e/3ImgsEfLZ4K0a1SQ1H+fHQ5ixCKUiq HrK3cmravbXZ7hF1aaI3ecTq5g== X-Google-Smtp-Source: AG47ELstUqe5vnhWEKfCuG5iNXcVG6ATmW9AhWvSiVfW0D6fMvkD20I3Ajuwt+Pwvkh7vNhmbDYqZA== X-Received: by 10.99.184.1 with SMTP id p1mr18763155pge.96.1521822899527; Fri, 23 Mar 2018 09:34:59 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id s78sm19131294pfa.161.2018.03.23.09.34.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Mar 2018 09:34:59 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Timur Tabi , Bjorn Andersson , Grant Likely , linux-gpio@vger.kernel.org, Andy Shevchenko Subject: [PATCH v4 4/5] gpiolib: Support 'gpio-reserved-ranges' property Date: Fri, 23 Mar 2018 09:34:52 -0700 Message-Id: <20180323163453.96495-5-swboyd@chromium.org> X-Mailer: git-send-email 2.17.0.rc0.231.g781580f067-goog In-Reply-To: <20180323163453.96495-1-swboyd@chromium.org> References: <20180323163453.96495-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Stephen Boyd Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Add support for a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. Non-DT platforms can add support by directly updating the chip->valid_mask. Signed-off-by: Stephen Boyd Signed-off-by: Stephen Boyd --- drivers/gpio/gpiolib-of.c | 24 +++++++++++++++++++ drivers/gpio/gpiolib.c | 46 +++++++++++++++++++++++++++++++++++++ include/linux/gpio/driver.h | 16 +++++++++++++ 3 files changed, 86 insertions(+) diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index 84e5a9df2344..ed81d9a6316f 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -511,6 +511,28 @@ void of_mm_gpiochip_remove(struct of_mm_gpio_chip *mm_gc) } EXPORT_SYMBOL(of_mm_gpiochip_remove); +static void of_gpiochip_init_valid_mask(struct gpio_chip *chip) +{ + int len, i; + u32 start, count; + struct device_node *np = chip->of_node; + + len = of_property_count_u32_elems(np, "gpio-reserved-ranges"); + if (len < 0 || len % 2 != 0) + return; + + for (i = 0; i < len; i += 2) { + of_property_read_u32_index(np, "gpio-reserved-ranges", + i, &start); + of_property_read_u32_index(np, "gpio-reserved-ranges", + i + 1, &count); + if (start >= chip->ngpio || start + count >= chip->ngpio) + continue; + + bitmap_clear(chip->valid_mask, start, count); + } +}; + #ifdef CONFIG_PINCTRL static int of_gpiochip_add_pin_range(struct gpio_chip *chip) { @@ -615,6 +637,8 @@ int of_gpiochip_add(struct gpio_chip *chip) if (chip->of_gpio_n_cells > MAX_PHANDLE_ARGS) return -EINVAL; + of_gpiochip_init_valid_mask(chip); + status = of_gpiochip_add_pin_range(chip); if (status) return status; diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index db3788d17ba0..fecbb553e8a4 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -351,6 +351,43 @@ static unsigned long *gpiochip_allocate_mask(struct gpio_chip *chip) return p; } +static int gpiochip_init_valid_mask(struct gpio_chip *gpiochip) +{ +#ifdef CONFIG_OF_GPIO + int size; + struct device_node *np = gpiochip->of_node; + + size = of_property_count_u32_elems(np, "gpio-reserved-ranges"); + if (size > 0 && size % 2 == 0) + gpiochip->need_valid_mask = true; +#endif + + if (!gpiochip->need_valid_mask) + return 0; + + gpiochip->valid_mask = gpiochip_allocate_mask(gpiochip); + if (!gpiochip->valid_mask) + return -ENOMEM; + + return 0; +} + +static void gpiochip_free_valid_mask(struct gpio_chip *gpiochip) +{ + kfree(gpiochip->valid_mask); + gpiochip->valid_mask = NULL; +} + +bool gpiochip_line_is_valid(const struct gpio_chip *gpiochip, + unsigned int offset) +{ + /* No mask means all valid */ + if (likely(!gpiochip->valid_mask)) + return true; + return test_bit(offset, gpiochip->valid_mask); +} +EXPORT_SYMBOL_GPL(gpiochip_line_is_valid); + /* * GPIO line handle management */ @@ -1275,6 +1312,10 @@ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data, if (status) goto err_remove_from_list; + status = gpiochip_init_valid_mask(chip); + if (status) + goto err_remove_irqchip_mask; + status = gpiochip_add_irqchip(chip, lock_key, request_key); if (status) goto err_remove_chip; @@ -1304,6 +1345,8 @@ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data, acpi_gpiochip_remove(chip); gpiochip_free_hogs(chip); of_gpiochip_remove(chip); + gpiochip_free_valid_mask(chip); +err_remove_irqchip_mask: gpiochip_irqchip_free_valid_mask(chip); err_remove_from_list: spin_lock_irqsave(&gpio_lock, flags); @@ -1360,6 +1403,7 @@ void gpiochip_remove(struct gpio_chip *chip) acpi_gpiochip_remove(chip); gpiochip_remove_pin_ranges(chip); of_gpiochip_remove(chip); + gpiochip_free_valid_mask(chip); /* * We accept no more calls into the driver from this point, so * NULL the driver data pointer @@ -1536,6 +1580,8 @@ static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip) bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip, unsigned int offset) { + if (!gpiochip_line_is_valid(gpiochip, offset)) + return false; /* No mask means all valid */ if (likely(!gpiochip->irq.valid_mask)) return true; diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 1ba9a331ec51..5382b5183b7e 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -288,6 +288,21 @@ struct gpio_chip { struct gpio_irq_chip irq; #endif + /** + * @need_valid_mask: + * + * If set core allocates @valid_mask with all bits set to one. + */ + bool need_valid_mask; + + /** + * @valid_mask: + * + * If not %NULL holds bitmask of GPIOs which are valid to be used + * from the chip. + */ + unsigned long *valid_mask; + #if defined(CONFIG_OF_GPIO) /* * If CONFIG_OF is enabled, then all GPIO controllers described in the @@ -384,6 +399,7 @@ bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset); /* Sleep persistence inquiry for drivers */ bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset); +bool gpiochip_line_is_valid(const struct gpio_chip *chip, unsigned int offset); /* get driver data */ void *gpiochip_get_data(struct gpio_chip *chip); From patchwork Fri Mar 23 16:34:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 890050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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Fri, 23 Mar 2018 09:35:00 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id s78sm19131294pfa.161.2018.03.23.09.34.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Mar 2018 09:35:00 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Timur Tabi , Bjorn Andersson , Grant Likely , linux-gpio@vger.kernel.org, Andy Shevchenko Subject: [PATCH v4 5/5] pinctrl: qcom: Don't allow protected pins to be requested Date: Fri, 23 Mar 2018 09:34:53 -0700 Message-Id: <20180323163453.96495-6-swboyd@chromium.org> X-Mailer: git-send-email 2.17.0.rc0.231.g781580f067-goog In-Reply-To: <20180323163453.96495-1-swboyd@chromium.org> References: <20180323163453.96495-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Stephen Boyd Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues and reset the device. With a DT/ACPI property to describe the set of pins that are available for use, parse the available pins and set the irq valid bits for gpiolib to know what to consider 'valid'. This should avoid any issues with gpiolib. Furthermore, implement the pinmux_ops::request function so that pinmux can also make sure to not use pins that are unavailable. Signed-off-by: Stephen Boyd Signed-off-by: Stephen Boyd --- drivers/pinctrl/qcom/pinctrl-msm.c | 65 ++++++++++++++++++++++++++++-- 1 file changed, 62 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 495432f3341b..e7abc8ba222b 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -105,6 +105,14 @@ static const struct pinctrl_ops msm_pinctrl_ops = { .dt_free_map = pinctrl_utils_free_map, }; +static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *chip = &pctrl->chip; + + return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; +} + static int msm_get_functions_count(struct pinctrl_dev *pctldev) { struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -166,6 +174,7 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, } static const struct pinmux_ops msm_pinmux_ops = { + .request = msm_pinmux_request, .get_functions_count = msm_get_functions_count, .get_function_name = msm_get_function_name, .get_function_groups = msm_get_function_groups, @@ -506,6 +515,9 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, "pull up" }; + if (!gpiochip_line_is_valid(chip, offset)) + return; + g = &pctrl->soc->groups[offset]; ctl_reg = readl(pctrl->regs + g->ctl_reg); @@ -517,6 +529,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); seq_printf(s, " %dmA", msm_regval_to_drive(drive)); seq_printf(s, " %s", pulls[pull]); + seq_puts(s, "\n"); } static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) @@ -524,10 +537,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) unsigned gpio = chip->base; unsigned i; - for (i = 0; i < chip->ngpio; i++, gpio++) { + for (i = 0; i < chip->ngpio; i++, gpio++) msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); - seq_puts(s, "\n"); - } } #else @@ -808,6 +819,46 @@ static void msm_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static int msm_gpio_init_valid_mask(struct gpio_chip *chip, + struct msm_pinctrl *pctrl) +{ + int ret; + unsigned int len, i; + unsigned int max_gpios = pctrl->soc->ngpios; + u16 *tmp; + + /* The number of GPIOs in the ACPI tables */ + len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0); + if (ret < 0) + return 0; + + if (ret > max_gpios) + return -EINVAL; + + tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); + if (ret < 0) { + dev_err(pctrl->dev, "could not read list of GPIOs\n"); + goto out; + } + + bitmap_zero(chip->valid_mask, max_gpios); + for (i = 0; i < len; i++) + set_bit(tmp[i], chip->valid_mask); + +out: + kfree(tmp); + return ret; +} + +static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) +{ + return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; +} + static int msm_gpio_init(struct msm_pinctrl *pctrl) { struct gpio_chip *chip; @@ -824,6 +875,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) chip->parent = pctrl->dev; chip->owner = THIS_MODULE; chip->of_node = pctrl->dev->of_node; + chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl); ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { @@ -831,6 +883,13 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) return ret; } + ret = msm_gpio_init_valid_mask(chip, pctrl); + if (ret) { + dev_err(pctrl->dev, "Failed to setup irq valid bits\n"); + gpiochip_remove(&pctrl->chip); + return ret; + } + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); if (ret) { dev_err(pctrl->dev, "Failed to add pin range\n");