From patchwork Sun Sep 17 17:15:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 814669 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xwG5t0ngmz9sPr for ; Mon, 18 Sep 2017 03:17:04 +1000 (AEST) Received: from localhost ([::1]:33091 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdBm-00067D-20 for incoming@patchwork.ozlabs.org; Sun, 17 Sep 2017 13:17:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45674) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdAy-00065O-MT for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtdAt-0006AC-NS for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:12 -0400 Received: from chuckie.co.uk ([82.165.15.123]:39954 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dtdAt-00069H-GJ; Sun, 17 Sep 2017 13:16:07 -0400 Received: from host109-151-159-252.range109-151.btcentralplus.com ([109.151.159.252] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dtdAt-0005RD-Ju; Sun, 17 Sep 2017 18:16:08 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Sun, 17 Sep 2017 18:15:43 +0100 Message-Id: <1505668548-16616-4-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.159.252 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 3/8] ppc/ide/macio: Add missing registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Benjamin Herrenschmidt The timing register exists on all variants of MacIO IDE, we just store and return its value. The interrupts register only exists on KeyLargo but it doesn't hurt to have it. The lack of this register causes MacOS X to hangs under some circumstances. Both are 32-bit only. The HW might support smaller access sizes but no known OS uses them. Because the core IDE subsystem doesn't provide us with a way to query the main (level) interrupt state, nor do we have a way to know that DBDMA issued a (edge) interrupt, we reflect both through a private pair of qirq's in order to maintain the register state. Signed-off-by: Benjamin Herrenschmidt --- hw/ide/macio.c | 44 +++++++++++++++++++++++++++++++++++++++++--- hw/ppc/mac.h | 6 +++++- 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 9742c00..db5db39 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -331,6 +331,12 @@ static void pmac_ide_writel (void *opaque, val = bswap32(val); if (addr == 0) { ide_data_writel(&d->bus, 0, val); + } else if (addr == 0x20) { + d->timing_reg = val; + } else if (addr == 0x30) { + if (val & 0x80000000u) { + d->irq_reg &= 0x7fffffff; + } } } @@ -342,6 +348,17 @@ static uint32_t pmac_ide_readl (void *opaque,hwaddr addr) addr = (addr & 0xFFF) >> 4; if (addr == 0) { retval = ide_data_readl(&d->bus, 0); + } else if (addr == 0x20) { + retval = d->timing_reg; + } else if (addr == 0x30) { + /* This is an interrupt state register that only exists + * in the KeyLargo and later variants. Bit 0x8000_0000 + * latches the DMA interrupt and has to be written to + * clear. Bit 0x4000_0000 is an image of the disk + * interrupt. MacOS X relies on this and will hang if + * we don't provide at least the disk interrupt + */ + retval = d->irq_reg; } else { retval = 0xFFFFFFFF; } @@ -426,13 +443,32 @@ static void macio_ide_realizefn(DeviceState *dev, Error **errp) { MACIOIDEState *s = MACIO_IDE(dev); - ide_init2(&s->bus, s->irq); + ide_init2(&s->bus, s->ide_irq); /* Register DMA callbacks */ s->dma.ops = &dbdma_ops; s->bus.dma = &s->dma; } +static void pmac_ide_irq(void *opaque, int n, int level) +{ + MACIOIDEState *s = opaque; + uint32_t mask = 0x80000000u >> n; + + /* We need to reflect the IRQ state in the irq register */ + if (level) { + s->irq_reg |= mask; + } else { + s->irq_reg &= ~mask; + } + + if (n) { + qemu_set_irq(s->real_ide_irq, level); + } else { + qemu_set_irq(s->real_dma_irq, level); + } +} + static void macio_ide_initfn(Object *obj) { SysBusDevice *d = SYS_BUS_DEVICE(obj); @@ -441,8 +477,10 @@ static void macio_ide_initfn(Object *obj) ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000); sysbus_init_mmio(d, &s->mem); - sysbus_init_irq(d, &s->irq); - sysbus_init_irq(d, &s->dma_irq); + sysbus_init_irq(d, &s->real_ide_irq); + sysbus_init_irq(d, &s->real_dma_irq); + s->dma_irq = qemu_allocate_irq(pmac_ide_irq, s, 0); + s->ide_irq = qemu_allocate_irq(pmac_ide_irq, s, 1); } static void macio_ide_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 20cbddb..300fc8a 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -132,7 +132,9 @@ typedef struct MACIOIDEState { SysBusDevice parent_obj; /*< public >*/ - qemu_irq irq; + qemu_irq real_ide_irq; + qemu_irq real_dma_irq; + qemu_irq ide_irq; qemu_irq dma_irq; MemoryRegion mem; @@ -140,6 +142,8 @@ typedef struct MACIOIDEState { IDEDMA dma; void *dbdma; bool dma_active; + uint32_t timing_reg; + uint32_t irq_reg; } MACIOIDEState; void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table);