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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:31 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 01/42] x86: Allow listing MTRRs in SPL Date: Wed, 19 Apr 2023 16:02:33 +1200 Message-ID: <20230419040314.160352-2-sjg@chromium.org> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Move MTRR-listing code into a common file so it can be used from SPL. Update the 'mtrr' command to call it. Use this in SPL just before adjusting the MTRRs, so we can see the state set up by the board. Only show it when debug is enabled. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/cpu/mtrr.c | 61 +++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/mtrr.h | 20 ++++++++++++ arch/x86/lib/spl.c | 7 +++++ cmd/x86/mtrr.c | 60 +++--------------------------------- 4 files changed, 92 insertions(+), 56 deletions(-) diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index c174dd9b3ad2..cf17e72f0974 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -30,6 +30,16 @@ DECLARE_GLOBAL_DATA_PTR; +const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { + "Uncacheable", + "Combine", + "2", + "3", + "Through", + "Protect", + "Back", +}; + /* Prepare to adjust MTRRs */ void mtrr_open(struct mtrr_state *state, bool do_caches) { @@ -324,3 +334,54 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask) return mtrr_start_op(cpu_select, &oper); } + +static void read_mtrrs_(void *arg) +{ + struct mtrr_info *info = arg; + + mtrr_read_all(info); +} + +int mtrr_list(int reg_count, int cpu_select) +{ + struct mtrr_info info; + int ret; + int i; + + printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", + "Mask ||", "Size ||"); + memset(&info, '\0', sizeof(info)); + ret = mp_run_on_cpus(cpu_select, read_mtrrs_, &info); + if (ret) + return log_msg_ret("run", ret); + for (i = 0; i < reg_count; i++) { + const char *type = "Invalid"; + uint64_t base, mask, size; + bool valid; + + base = info.mtrr[i].base; + mask = info.mtrr[i].mask; + size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); + size |= (1 << 12) - 1; + size += 1; + valid = mask & MTRR_PHYS_MASK_VALID; + type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; + printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, + valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK, + mask & ~MTRR_PHYS_MASK_VALID, size); + } + + return 0; +} + +int mtrr_get_type_by_name(const char *typename) +{ + int i; + + for (i = 0; i < MTRR_TYPE_COUNT; i++) { + if (*typename == *mtrr_type_name[i]) + return i; + } + + return -EINVAL; +}; diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index ca2edc7878f7..2e995f540616 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -190,6 +190,26 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask); */ int mtrr_get_var_count(void); +/** + * mtrr_list() - List the MTRRs + * + * Shows a list of all the MTRRs including their values + * + * @reg_count: Number of registers to show. You can use mtrr_get_var_count() for + * this + * @cpu_select: CPU to use. Use MP_SELECT_BSP for the boot CPU + * Returns: 0 if OK, -ve if the CPU was not found + */ +int mtrr_list(int reg_count, int cpu_select); + +/** + * mtrr_get_type_by_name() - Get the type of an MTRR given its type name + * + * @typename: Name to check + * Returns: MTRR type (MTRR_TYPE_...) or -EINVAL if invalid + */ +int mtrr_get_type_by_name(const char *typename); + #endif #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index f0b74d04252a..7cf14f682da1 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -139,6 +140,12 @@ static int x86_spl_init(void) arch_setup_gd(gd->new_gd); gd->start_addr_sp = (ulong)ptr; + if (_LOG_DEBUG) { + ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP); + if (ret) + printf("mtrr_list failed\n"); + } + /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */ ret = mtrr_add_request(MTRR_TYPE_WRBACK, (1ULL << 32) - CONFIG_XIP_ROM_SIZE, diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c index b1691d8b65ab..6ad7a123a447 100644 --- a/cmd/x86/mtrr.c +++ b/cmd/x86/mtrr.c @@ -10,71 +10,19 @@ #include #include -static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { - "Uncacheable", - "Combine", - "2", - "3", - "Through", - "Protect", - "Back", -}; - -static void read_mtrrs(void *arg) -{ - struct mtrr_info *info = arg; - - mtrr_read_all(info); -} - -static int do_mtrr_list(int reg_count, int cpu_select) -{ - struct mtrr_info info; - int ret; - int i; - - printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", - "Mask ||", "Size ||"); - memset(&info, '\0', sizeof(info)); - ret = mp_run_on_cpus(cpu_select, read_mtrrs, &info); - if (ret) - return log_msg_ret("run", ret); - for (i = 0; i < reg_count; i++) { - const char *type = "Invalid"; - uint64_t base, mask, size; - bool valid; - - base = info.mtrr[i].base; - mask = info.mtrr[i].mask; - size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); - size |= (1 << 12) - 1; - size += 1; - valid = mask & MTRR_PHYS_MASK_VALID; - type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; - printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, - valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK, - mask & ~MTRR_PHYS_MASK_VALID, size); - } - - return 0; -} - static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[]) { const char *typename = argv[0]; uint32_t start, size; uint64_t base, mask; - int i, type = -1; + int type = -1; bool valid; int ret; if (argc < 3) return CMD_RET_USAGE; - for (i = 0; i < MTRR_TYPE_COUNT; i++) { - if (*typename == *mtrr_type_name[i]) - type = i; - } - if (type == -1) { + type = mtrr_get_type_by_name(typename); + if (type < 0) { printf("Invalid type name %s\n", typename); return CMD_RET_USAGE; } @@ -146,7 +94,7 @@ static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc, if (!first) printf("\n"); printf("CPU %d:\n", i); - ret = do_mtrr_list(reg_count, i); + ret = mtrr_list(reg_count, i); if (ret) { printf("Failed to read CPU %s (err=%d)\n", i < MP_SELECT_ALL ? simple_itoa(i) : "", From patchwork Wed Apr 19 04:02:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770496 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:32 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 02/42] x86: mtrr: Add documentation Date: Wed, 19 Apr 2023 16:02:34 +1200 Message-ID: <20230419040314.160352-3-sjg@chromium.org> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add documention for the x86 'mtrr' command. Signed-off-by: Simon Glass Suggested-by: Heinrich Schuchardt --- Changes in v2: - Add new patch with docs for mtrr command doc/usage/cmd/mtrr.rst | 151 +++++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + 2 files changed, 152 insertions(+) create mode 100644 doc/usage/cmd/mtrr.rst diff --git a/doc/usage/cmd/mtrr.rst b/doc/usage/cmd/mtrr.rst new file mode 100644 index 000000000000..1b79424112d7 --- /dev/null +++ b/doc/usage/cmd/mtrr.rst @@ -0,0 +1,151 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +mtrr command +============ + +Synopis +------- + + mtrr [list] + mtrr set + mtrr disable + mtrr enable + + +Description +----------- + +The *mtrr* command is used to dump the Memory Type Range Registers (MTRRs) on +an x86 machine. These register control cache behaviour in selected memory +ranges. + +Note that the number of registers can vary between CPUs. + + +mtrr [list] +~~~~~~~~~~~ + +List the MTRRs. The table shows the following information: + +Reg + Register number (the first is register 0) + +Valid + Shows Y if the register is valid (has bit 11 set), N if not + +Write-type + Shows the behaviour when writing to the memory region. The types are + abrievated to fit a reasonable line length. Valid types shown below. + + ====== ============== ==================================================== + Value Type Meaning + ====== ============== ==================================================== + 0 Uncacheable Skip cache and write directly to memory + 1 Combine Multiple writes can be combined into one transaction + 4 Through Update cache and also write to memory + 5 Protect Writes are prohibited + 6 Back Update cache but don't write to memory + ====== ============== ==================================================== + +Base + Base memory address from which the register controls behaviour + +Mask + Mask value, which also indicates the size + +Size + Length of memory region within which the register controls behaviour + + +mtrr set +~~~~~~~~ + +This sets the value of a particular MTRR. Parameters are: + +reg + Register number to set, with 0 being the first + +type + Access type to set. See Write-type above for valid types. This uses the name + rather than its numeric value. + +start + Base memory address from which the register should control behaviour + +size + Length of memory region within which the register controls behaviour + + +mtrr disable +~~~~~~~~~~~~ + +This disables a particular register, by clearing its `valid` bit (11). + + +mtrr enable +~~~~~~~~~~~ + +This enables a particular register, by setting its `valid` bit (11). + + +Example +------- + +This shows disabling and enabling an MTRR, as well as setting its type:: + + => mtrr + CPU 0: + Reg Valid Write-type Base || Mask || Size || + 0 Y Back 0000000000000000 0000000f80000000 0000000080000000 + 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000 + 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000 + 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000 + 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000 + 5 Y Combine 00000000d0000000 0000000ff0000000 0000000010000000 + 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + => mtrr d 5 + => mtrr + CPU 0: + Reg Valid Write-type Base || Mask || Size || + 0 Y Back 0000000000000000 0000000f80000000 0000000080000000 + 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000 + 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000 + 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000 + 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000 + 5 N Combine 00000000d0000000 0000000ff0000000 0000000010000000 + 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + => mtrr e 5 + => mtrr + CPU 0: + Reg Valid Write-type Base || Mask || Size || + 0 Y Back 0000000000000000 0000000f80000000 0000000080000000 + 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000 + 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000 + 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000 + 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000 + 5 Y Combine 00000000d0000000 0000000ff0000000 0000000010000000 + 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + => mtrr set 5 Uncacheable d0000000 10000000 + => mtrr + CPU 0: + Reg Valid Write-type Base || Mask || Size || + 0 Y Back 0000000000000000 0000000f80000000 0000000080000000 + 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000 + 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000 + 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000 + 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000 + 5 Y Uncacheable 00000000d0000000 0000000ff0000000 0000000010000000 + 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000 + => diff --git a/doc/usage/index.rst b/doc/usage/index.rst index cdf710919a20..cb6876bb7150 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -68,6 +68,7 @@ Shell commands cmd/md cmd/mmc cmd/mtest + cmd/mtrr cmd/panic cmd/part cmd/pause From patchwork Wed Apr 19 04:02:35 2023 Content-Type: text/plain; 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Move it into the correct place and allow use in SPL, so that video can be used there if needed. Signed-off-by: Simon Glass --- (no changes since v1) board/google/Kconfig | 7 ------- drivers/Kconfig | 2 ++ drivers/Makefile | 2 +- drivers/bios_emulator/Kconfig | 10 ++++++++++ 4 files changed, 13 insertions(+), 8 deletions(-) create mode 100644 drivers/bios_emulator/Kconfig diff --git a/board/google/Kconfig b/board/google/Kconfig index a0f1a6097641..e4f9b5b68aab 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -4,13 +4,6 @@ if VENDOR_GOOGLE -config BIOSEMU - bool - select X86EMU_RAW_IO - -config X86EMU_RAW_IO - bool - choice prompt "Mainboard model" optional diff --git a/drivers/Kconfig b/drivers/Kconfig index 9101e538b097..b5d21e8e6c90 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -10,6 +10,8 @@ source "drivers/ata/Kconfig" source "drivers/axi/Kconfig" +source "drivers/bios_emulator/Kconfig" + source "drivers/bus/Kconfig" source "drivers/block/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 928a8b0e9db3..9fbf1211e84c 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/ obj-$(CONFIG_$(SPL_TPL_)BLK) += block/ obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ @@ -78,7 +79,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-y += adc/ obj-y += ata/ obj-$(CONFIG_DM_DEMO) += demo/ -obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ obj-y += cache/ obj-$(CONFIG_CPU) += cpu/ diff --git a/drivers/bios_emulator/Kconfig b/drivers/bios_emulator/Kconfig new file mode 100644 index 000000000000..3660576772d1 --- /dev/null +++ b/drivers/bios_emulator/Kconfig @@ -0,0 +1,10 @@ +config BIOSEMU + bool + select X86EMU_RAW_IO + +config SPL_BIOSEMU + bool + select X86EMU_RAW_IO + +config X86EMU_RAW_IO + bool From patchwork Wed Apr 19 04:02:36 2023 Content-Type: text/plain; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:33 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 04/42] bios_emulator: Drop VIDEO_IO_OFFSET Date: Wed, 19 Apr 2023 16:02:36 +1200 Message-ID: <20230419160308.v2.4.I54016e13134e2f8d074dc06cced339510c8b281b@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This is always zero in the source tree, so drop it. While we are here, add a comment to _X86EMU_env since it the symbol is actually defined twice, which can cause confusion when building. Signed-off-by: Simon Glass --- (no changes since v1) drivers/bios_emulator/biosemui.h | 18 +++++++++--------- drivers/bios_emulator/x86emu/sys.c | 1 + include/configs/conga-qeval20-qa3-e3845.h | 2 -- include/configs/dfi-bt700.h | 2 -- include/configs/minnowmax.h | 2 -- include/configs/som-db5800-som-6867.h | 2 -- include/configs/theadorable-x86-common.h | 2 -- include/configs/x86-chromebook.h | 2 -- 8 files changed, 10 insertions(+), 21 deletions(-) diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h index 7853015c1e2e..954cd883158c 100644 --- a/drivers/bios_emulator/biosemui.h +++ b/drivers/bios_emulator/biosemui.h @@ -128,19 +128,19 @@ typedef struct { u32 finalVal; } BE_portInfo; -#define PM_inpb(port) inb(port+VIDEO_IO_OFFSET) -#define PM_inpw(port) inw(port+VIDEO_IO_OFFSET) -#define PM_inpd(port) inl(port+VIDEO_IO_OFFSET) -#define PM_outpb(port,val) outb(val,port+VIDEO_IO_OFFSET) -#define PM_outpw(port,val) outw(val,port+VIDEO_IO_OFFSET) -#define PM_outpd(port,val) outl(val,port+VIDEO_IO_OFFSET) +#define PM_inpb(port) inb(port) +#define PM_inpw(port) inw(port) +#define PM_inpd(port) inl(port) +#define PM_outpb(port, val) outb(val, port) +#define PM_outpw(port, val) outw(val, port) +#define PM_outpd(port, val) outl(val, port) #define LOG_inpb(port) PM_inpb(port) #define LOG_inpw(port) PM_inpw(port) #define LOG_inpd(port) PM_inpd(port) -#define LOG_outpb(port,val) PM_outpb(port,val) -#define LOG_outpw(port,val) PM_outpw(port,val) -#define LOG_outpd(port,val) PM_outpd(port,val) +#define LOG_outpb(port, val) PM_outpb(port, val) +#define LOG_outpw(port, val) PM_outpw(port, val) +#define LOG_outpd(port, val) PM_outpd(port, val) /*-------------------------- Function Prototypes --------------------------*/ diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index c2db1213fe66..882a8a34cc3e 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -44,6 +44,7 @@ /*------------------------- Global Variables ------------------------------*/ +/* Note: bios.c defines this if the emulator is not enabled */ X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ X86EMU_intrFuncs _X86EMU_intrTab[256]; diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index 60617e6fec25..03c364f29fb3 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -16,8 +16,6 @@ "stdout=serial\0" \ "stderr=serial\0" -#define VIDEO_IO_OFFSET 0 - #undef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ "kernel-ver=4.4.0-22\0" \ diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 05389a435bee..be095e28a1b4 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -20,8 +20,6 @@ "stdout=serial\0" \ "stderr=serial\0" -#define VIDEO_IO_OFFSET 0 - #undef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ "kernel-ver=4.4.0-24\0" \ diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 4a12c2f72c62..842672d55751 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -17,6 +17,4 @@ "stderr=vidconsole,serial\0" \ "usb_pgood_delay=40\0" -#define VIDEO_IO_OFFSET 0 - #endif /* __CONFIG_H */ diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h index b2e7aa1514c0..5f7eabd3fc64 100644 --- a/include/configs/som-db5800-som-6867.h +++ b/include/configs/som-db5800-som-6867.h @@ -16,6 +16,4 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#define VIDEO_IO_OFFSET 0 - #endif /* __CONFIG_H */ diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index b23b8783076b..46aef238213a 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -15,8 +15,6 @@ "stdout=serial\0" \ "stderr=serial\0" -#define VIDEO_IO_OFFSET 0 - /* Environment settings */ #undef CFG_EXTRA_ENV_SETTINGS diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 98abb00927ad..6bf90c7de432 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -10,8 +10,6 @@ #define CFG_X86_REFCODE_ADDR 0xffea0000 #define CFG_X86_REFCODE_RUN_ADDR 0 -#define VIDEO_IO_OFFSET 0 - #define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" From patchwork Wed Apr 19 04:02:37 2023 Content-Type: text/plain; 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Drop it. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/cpu/i386/interrupt.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index fae2544c456f..f3f3527237f2 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -266,6 +266,10 @@ int interrupt_init(void) struct udevice *dev; int ret; + /* + * When running as an EFI application we are not in control of + * interrupts and should leave them alone. + */ if (!ll_boot_init()) return 0; @@ -274,11 +278,6 @@ int interrupt_init(void) if (ret && ret != -ENODEV) return ret; - /* - * When running as an EFI application we are not in control of - * interrupts and should leave them alone. - */ -#ifndef CONFIG_EFI_APP /* Just in case... */ disable_interrupts(); @@ -294,14 +293,8 @@ int interrupt_init(void) /* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts(); - /* - * It is now safe to enable interrupts. - * - * TODO(sjg@chromium.org): But we don't handle these correctly when - * booted from EFI. - */ + /* It is now safe to enable interrupts */ enable_interrupts(); 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:35 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 06/42] x86: Add a comment for board_init_f_r_trampoline() Date: Wed, 19 Apr 2023 16:02:38 +1200 Message-ID: <20230419160308.v2.6.Ib334710a2abe24e384e2f9f01feac0aa1fadd045@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add a comment for this function in the header. Change the function (and the one after) to use __noreturn to keep checkpatch happy. Add docs to board_init_f_r() while we are here. Signed-off-by: Simon Glass --- Changes in v2: - Add docs to board_init_f_r() too arch/x86/include/asm/u-boot-x86.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 8f38c2d1c601..1d8aa320f535 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -102,8 +102,20 @@ int video_bios_init(void); */ int fsp_save_s3_stack(void); -void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); -void board_init_f_r(void) __attribute__ ((noreturn)); +/** + * board_init_f_r_trampoline() - jump to relocated address with new stack + * + * @sp: New stack pointer to use + */ +void __noreturn board_init_f_r_trampoline(ulong sp); + +/** + * board_init_f_r() - jump to relocated U-Boot + * + * This is used to jump from pre-relocation to post-relocation U-Boot. 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Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/lib/bdinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c index 15390070fe85..0970efa4726f 100644 --- a/arch/x86/lib/bdinfo.c +++ b/arch/x86/lib/bdinfo.c @@ -22,6 +22,7 @@ void arch_print_bdinfo(void) bdinfo_print_num_l("vendor", gd->arch.x86_vendor); bdinfo_print_str(" name", cpu_vendor_name(gd->arch.x86_vendor)); bdinfo_print_num_l("model", gd->arch.x86_model); + bdinfo_print_num_l("phys_addr", cpu_phys_address_size()); if (IS_ENABLED(CONFIG_EFI_STUB)) efi_show_bdinfo(); From patchwork Wed Apr 19 04:02:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770536 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=TOy7Vb/F; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S7f4Gtqz1yZk for ; Wed, 19 Apr 2023 14:13:02 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7A902861D3; Wed, 19 Apr 2023 06:11:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="TOy7Vb/F"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 54927861D3; Wed, 19 Apr 2023 06:11:37 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x12c.google.com (mail-il1-x12c.google.com [IPv6:2607:f8b0:4864:20::12c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CB423861D3 for ; Wed, 19 Apr 2023 06:03:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x12c.google.com with SMTP id e9e14a558f8ab-329560b1994so10386955ab.3 for ; Tue, 18 Apr 2023 21:03:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877017; x=1684469017; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4d4AHouGIjM290QiAmx5CwpA9gDeP41HJ7z3IbO2r+Y=; b=TOy7Vb/F4be8GTUy4RIgCaxm+tTanK98YccuCqTfSxT4XcrrIjGNeOLp4vnfCGXXin 9uGwNtO/ov/cMdzhhbqczec0avyJbHo2gKsYr3LYRTrGSZMVPZeUsQJUWFmSjUTJxiUp e6KzmCFlqoDy5QAytgZTBqhooHAG3ghYSZDtQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877017; x=1684469017; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4d4AHouGIjM290QiAmx5CwpA9gDeP41HJ7z3IbO2r+Y=; b=IUiKZspduHz4TppGMZPk1WJc1fVHy5LycDdgoPG3gMyNba8Ggveeh3Ti5Jv5CCEh9W 9XDPj5TbJzRpVO0OypBOuPWM+XOWOyi3r5sY73Eq9YE1Zv4c+vYyhcl74dZf0pb7bsCS y7pPm9m1EEOPoCWMNI4lwIyxsMfL3M+m+ZJGFYDyRr1wkAWZeE+KdcXVfZ6WTRNjPtVV RQMSEUQFCb8XFRVFsVsr3uO0biahGYNas0YQiDXRTK5ks7YK/OnPQSFGGQbqbeL4D7c6 2lH+vKTM8YWc3Hj4SWaROMkbxhiSPbYl9RT7h32bYeEBQeBXzLNpIPsqRIcQYoNQTWEP hbMA== X-Gm-Message-State: AAQBX9fdcyKeilUNONn5zZ3/is4UqUcSBsCYBtrbduv2PCMvC4QlbwxE Cx1I3JIWbA4hC2Wet22Yxevpyrngejc9Poxy3iI= X-Google-Smtp-Source: AKy350YioWkn7tdVocykhpIjVQ5L7QRsV0yAPRUan9I3p58PoGeQ41sQzwi0BEMj+a12t4WY6Ux9mw== X-Received: by 2002:a92:2c08:0:b0:32b:12a3:f950 with SMTP id t8-20020a922c08000000b0032b12a3f950mr4642822ile.8.1681877017226; Tue, 18 Apr 2023 21:03:37 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. 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Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 61cb7bc61168..3196f9ddc2c8 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -258,7 +258,7 @@ static ulong get_sp(void) ulong ret; #if CONFIG_IS_ENABLED(X86_64) - ret = gd->start_addr_sp; + asm("mov %%rsp, %0" : "=r"(ret) : ); #else asm("mov %%esp, %0" : "=r"(ret) : ); #endif From patchwork Wed Apr 19 04:02:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770499 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=C4Aemkw9; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1RyK5TC6z1ybF for ; Wed, 19 Apr 2023 14:04:57 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E1152861BF; Wed, 19 Apr 2023 06:03:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="C4Aemkw9"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A7B0A861D5; Wed, 19 Apr 2023 06:03:43 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x136.google.com (mail-il1-x136.google.com [IPv6:2607:f8b0:4864:20::136]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 88E74861D9 for ; Wed, 19 Apr 2023 06:03:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x136.google.com with SMTP id e9e14a558f8ab-329673008e3so34170875ab.2 for ; Tue, 18 Apr 2023 21:03:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877018; x=1684469018; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xxx7az1vtvdM76kD/cxrWoaMRAEVMN1v5maJ7rAJDxw=; b=C4Aemkw9K1J1Kwr5Fflm/isKYi7NIjkR5x6DISb3Fdc+MUOt/5vqt1OUDufwga/fDh nMbvRJSI1/0Q5P21TYhQYmWQdWp5tcp5afrm60BUiko/oIAg4QdEX81XJ1bPQVBINeSB zlp1SozAM2Qqh9egZcaPp6xEw+iTYS8rJQekc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877018; x=1684469018; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xxx7az1vtvdM76kD/cxrWoaMRAEVMN1v5maJ7rAJDxw=; b=kiYij+UbMU7vnhJjV04+OawtlsoRbbaF+yHDg0wUcGs5UZmmp/Tg/7nOdF/AWEYQBH VFqIxrKEbodq7KgyfUn9Q8mLlZm6qLG24trm3xs+FHkj/RK1gUfsRDQet+8l0+7BEN1c tCT1bwh+AkucWZNzevy1+3r14V3zHqUtrFeySHqP5yaXTvPZxD0ns9BxZ750kaeq5B7H i5crq76HXMBYJwLsLsCKEZ1sqvCy3bzuXag9YDLFQ14Z1E4IMPceSSR06ePP6Fc5Vmwj ywdNe6biZWxpsrT2NFDw99gbTvnDh+qQL7iNtGf1UmWMVQDQOhkbBy1n39N1ZvpTj3QY d8qg== X-Gm-Message-State: AAQBX9cHZ5/PShYGmVnpkq2+ckd9I1UDbb6bbHBZRS/IGGq9ROFPwSmH OJD0mnSS4cwiBSTBXVyRHTUdgtbs3x7LDChKoXw= X-Google-Smtp-Source: AKy350YZpj4RC5bXrqFyZPTEcSPczs5K6eaySZuVfx/3MYSxpvBLPbIjmo8xGuCSv6/dZU1hoPpDaQ== X-Received: by 2002:a92:d6d2:0:b0:328:e3db:80a5 with SMTP id z18-20020a92d6d2000000b00328e3db80a5mr15100516ilp.20.1681877018026; Tue, 18 Apr 2023 21:03:38 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:37 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 09/42] x86: Show an error when a BIOS exception occurs Date: Wed, 19 Apr 2023 16:02:41 +1200 Message-ID: <20230419160308.v2.9.I76dffbd644a8af409f3be94419ace7ef642d9ee4@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Rather than silently hanging, show an error first. This can happen when there is something wrong with the video BIOS. Signed-off-by: Simon Glass --- Changes in v2: - Fix BINS typo - Drop the Ooops string arch/x86/lib/bios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 94349ba8073d..8cc686fd146b 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -78,7 +78,7 @@ static int int_exception_handler(void) }; struct eregs *regs = ®_info; - debug("Oops, exception %d while executing option rom\n", regs->vector); + log_err("Exception %d while executing option rom\n", regs->vector); cpu_hlt(); return 0; From patchwork Wed Apr 19 04:02:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770503 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=bxvjrX/0; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1RzM1cCyz1ybC for ; Wed, 19 Apr 2023 14:05:51 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CAF46861FC; Wed, 19 Apr 2023 06:04:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="bxvjrX/0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B6144861BF; Wed, 19 Apr 2023 06:03:46 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x129.google.com (mail-il1-x129.google.com [IPv6:2607:f8b0:4864:20::129]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 798D5861C6 for ; Wed, 19 Apr 2023 06:03:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x129.google.com with SMTP id e9e14a558f8ab-329673008e3so34170985ab.2 for ; Tue, 18 Apr 2023 21:03:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877019; x=1684469019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bkD+s8P6gibJ2TvOPAdAi7wcdxMWF0TzHzIuLsyxHWI=; b=bxvjrX/0+dXdSeYM9RPYSwvbE6hq5f71TzblsVYanZFn7MHfu3f2oAP+CfaHCbp/ah lm2u4klwbdY2ykjfpBoE2r+q89imVInglz+bJHvh7BWAMiiMvzO00TavzSFOr/4pLboi GYdivbPKaIklil8T7nw9Dbb+uGo+vntP2c8jo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877019; x=1684469019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bkD+s8P6gibJ2TvOPAdAi7wcdxMWF0TzHzIuLsyxHWI=; b=lg2nMImMGN7c/mUwLikUpKWc3rp1n0+xhem210FXRm00oObW6tmBN+FyywAvoyUg68 YgHRzxWfK/TL6+aPqcmhHVHucIvb4dfd41aym6SfLJ+acNrGFyNmee+yeKzOSveI9Bd8 b/yUEdO6zsdyDhhGGiHOolTGqmSXDpzH1mqz1HJhhORVwf/OrCgibJRd88qV5J84XtUb qiYRrDRIiwyWWARxWb4AjJW0f+AgZqmZTlDCnH2aaujFjniU25zcl6v4Ci/YDfFzhYBq tGe1dYT1CCuh7aeY3WsGUm0pmNeQL+WW5ye0hR2dr5sMdndBUUfbVxEbmjBGIxG9VPwQ Kv6Q== X-Gm-Message-State: AAQBX9e/h3U2ugrngW5IMP8y+4vx5Eimx+fEdROxMfT9jYLrQesWUPw2 15Rx/RFr0w25odIr5n58ZSAIPn1zNnPFTi9LL7Y= X-Google-Smtp-Source: AKy350Z+LUgPb/+wrHGh2VbSTafrpKBut5HngfO9swobWCuqa78eG0n8mcxVWaXaEa6r5wlhNLvxWA== X-Received: by 2002:a92:cd0f:0:b0:32b:26aa:ce3c with SMTP id z15-20020a92cd0f000000b0032b26aace3cmr7016238iln.10.1681877018853; Tue, 18 Apr 2023 21:03:38 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:38 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 10/42] acpi: Add a comment to set the acpi tables Date: Wed, 19 Apr 2023 16:02:42 +1200 Message-ID: <20230419160308.v2.10.I5c3b0506bc7def0d7bbae87f7841a7e0107bee35@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Sometimes a previous bootloader has written ACPI tables. It is useful to be able to find and list these. Add an 'acpi set' command to set the address for these tables. Signed-off-by: Simon Glass --- (no changes since v1) cmd/acpi.c | 24 +++++++++++++++++++++--- doc/usage/cmd/acpi.rst | 29 +++++++++++++++++++++++++++-- test/dm/acpi.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+), 5 deletions(-) diff --git a/cmd/acpi.c b/cmd/acpi.c index e70913e40bfe..ede9c8c7dcb4 100644 --- a/cmd/acpi.c +++ b/cmd/acpi.c @@ -118,6 +118,22 @@ static int do_acpi_list(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } +static int do_acpi_set(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong val; + + if (argc < 2) { + printf("ACPI pointer: %lx\n", gd_acpi_start()); + } else { + val = hextoul(argv[1], NULL); + printf("Setting ACPI pointer to %lx\n", val); + gd_set_acpi_start(val); + } + + return 0; +} + static int do_acpi_items(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -157,12 +173,14 @@ static int do_acpi_dump(struct cmd_tbl *cmdtp, int flag, int argc, #ifdef CONFIG_SYS_LONGHELP static char acpi_help_text[] = - "list - list ACPI tables\n" - "acpi items [-d] - List/dump each piece of ACPI data from devices\n" - "acpi dump - Dump ACPI table"; + "list - list ACPI tables\n" + "acpi items [-d] - List/dump each piece of ACPI data from devices\n" + "acpi set [] - Set or show address of ACPI tables\n" + "acpi dump - Dump ACPI table"; #endif U_BOOT_CMD_WITH_SUBCMDS(acpi, "ACPI tables", acpi_help_text, U_BOOT_SUBCMD_MKENT(list, 1, 1, do_acpi_list), U_BOOT_SUBCMD_MKENT(items, 2, 1, do_acpi_items), + U_BOOT_SUBCMD_MKENT(set, 2, 1, do_acpi_set), U_BOOT_SUBCMD_MKENT(dump, 2, 1, do_acpi_dump)); diff --git a/doc/usage/cmd/acpi.rst b/doc/usage/cmd/acpi.rst index 14bafc8e3524..5aeb4f4b77bf 100644 --- a/doc/usage/cmd/acpi.rst +++ b/doc/usage/cmd/acpi.rst @@ -11,12 +11,14 @@ Synopis acpi list acpi items [-d] acpi dump + acpi set
Description ----------- -The *acpi* command is used to dump the ACPI tables generated by U-Boot for passing -to the operating systems. +The *acpi* command is used to dump the ACPI tables generated by U-Boot for +passing to the operating systems. It allow allows manually setting the address +to take a look at existing ACPI tables. ACPI tables can be generated by various output functions and even devices can output material to include in the Differentiated System Description Table (DSDT) @@ -231,5 +233,28 @@ Example 00000000: 44 53 44 54 ea 32 00 00 02 eb 55 2d 42 4f 4f 54 DSDT.2....U-BOOT 00000010: 55 2d 42 4f 4f 54 42 4c 25 07 11 20 49 4e 54 4c U-BOOTBL%.. INTL +This shows searching for tables in a known area of memory, then setting the +pointer:: + + => acpi list + No ACPI tables present + => ms.s bff00000 80000 "RSD PTR" + bff75000: 52 53 44 20 50 54 52 20 cf 42 4f 43 48 53 20 00 RSD PTR .BOCHS . + 1 match + => acpi set bff75000 + Setting ACPI pointer to bff75000 + => acpi list + Name Base Size Detail + ---- -------- ----- ------ + RSDP bff75000 0 v00 BOCHS + RSDT bff76a63 38 v01 BOCHS BXPC 1 BXPC 1 + FACP bff768ff 74 v01 BOCHS BXPC 1 BXPC 1 + DSDT bff75080 187f v01 BOCHS BXPC 1 BXPC 1 + FACS bff75040 40 + APIC bff76973 90 v01 BOCHS BXPC 1 BXPC 1 + HPET bff76a03 38 v01 BOCHS BXPC 1 BXPC 1 + WAET bff76a3b 28 v01 BOCHS BXPC 1 BXPC 1 + SSDT bff95040 c5 v02 COREv4 COREBOOT 2a CORE 20221020 + .. _`ACPI specification`: https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 9634fc2e9002..1511336a5ebc 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -611,3 +611,41 @@ static int dm_test_acpi_cmd_items(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_cmd_items, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +/* Test 'acpi set' command */ +static int dm_test_acpi_cmd_set(struct unit_test_state *uts) +{ + struct acpi_ctx ctx; + ulong addr; + void *buf; + + gd_set_acpi_start(0); + + console_record_reset(); + ut_asserteq(0, gd_acpi_start()); + ut_assertok(run_command("acpi set", 0)); + ut_assert_nextline("ACPI pointer: 0"); + + buf = memalign(16, BUF_SIZE); + ut_assertnonnull(buf); + addr = map_to_sysmem(buf); + ut_assertok(setup_ctx_and_base_tables(uts, &ctx, addr)); + + ut_assertok(acpi_write_dev_tables(&ctx)); + + ut_assertok(run_command("acpi set", 0)); + ut_assert_nextline("ACPI pointer: %lx", addr); + + ut_assertok(run_command("acpi set 0", 0)); + ut_assert_nextline("Setting ACPI pointer to 0"); + ut_asserteq(0, gd_acpi_start()); + + ut_assertok(run_commandf("acpi set %lx", addr)); + ut_assert_nextline("Setting ACPI pointer to %lx", addr); + ut_asserteq(addr, gd_acpi_start()); + + ut_assert_console_end(); + + return 0; +} +DM_TEST(dm_test_acpi_cmd_set, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); From patchwork Wed Apr 19 04:02:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770504 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=hV44dgGs; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1Rzc0VbBz1ybC for ; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:39 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 11/42] bdinfo: Show the RAM top and approximate stack pointer Date: Wed, 19 Apr 2023 16:02:43 +1200 Message-ID: <20230419160308.v2.11.Ib35b8f5950b2eceb28aaf39b527c3463cc5c394f@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean These are useful pieces of information when debugging. The RAM top shows where U-Boot started allocating memory from, before it relocated. The stack pointer can be checked to ensure it is in the correct region. Signed-off-by: Simon Glass --- (no changes since v1) cmd/Kconfig | 8 ++++++++ cmd/bdinfo.c | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 56f5ab02239b..26ad696c6a6e 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -135,6 +135,14 @@ config CMD_BDI help Print board info +config CMD_BDINFO_EXTRA + bool "bdinfo extra features" + default y if SANDBOX || X86 + help + Show additional information about the board. This uses a little more + code space but provides more options, particularly those useful for + bringup, development and debugging. + config CMD_CONFIG bool "config" default SANDBOX diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index f709904c5167..4e0c763a7096 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -145,6 +145,11 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) printf("devicetree = %s\n", fdtdec_get_srcname()); } + if (IS_ENABLED(CONFIG_CMD_BDINFO_EXTRA)) { + bdinfo_print_num_ll("stack ptr", (ulong)&bd); + bdinfo_print_num_ll("ram_top ptr", (ulong)gd->ram_top); + } + arch_print_bdinfo(); return 0; From patchwork Wed Apr 19 04:02:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770505 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=Nk/m2e/e; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1Rzr4RnGz1ybC for ; Wed, 19 Apr 2023 14:06:16 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4C8E686218; Wed, 19 Apr 2023 06:04:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Nk/m2e/e"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B1512861F0; Wed, 19 Apr 2023 06:03:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-io1-xd30.google.com (mail-io1-xd30.google.com [IPv6:2607:f8b0:4864:20::d30]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 23C03861A5 for ; Wed, 19 Apr 2023 06:03:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-io1-xd30.google.com with SMTP id ca18e2360f4ac-7606df33c42so77073839f.2 for ; Tue, 18 Apr 2023 21:03:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877020; x=1684469020; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eF5ws/WNq2RZxnjnaVVdZnDpj5LQkmzu7XkUMjodeG0=; b=Nk/m2e/em5SMyL5cXVXT41UqGvNdZBhrasTn9J3W16cv71YDGrEVC1YCdZ0b/PpFig WTQK0DIfggfqhZB1/k62Qt8vG+SOChpdNyy9w+QQrPl/vNvIUFDZLUocXJWJ1DChTlqo YV2jyS5gZGWCQDAp79utEQP+ttEfD0pZZNUJY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877020; x=1684469020; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eF5ws/WNq2RZxnjnaVVdZnDpj5LQkmzu7XkUMjodeG0=; b=dZy/J+FaWiYVEZCpA1eFJXvbYjQb/n7SKwuGubkSk4fwCIzwusdRREIgmXHDt63O2e S03WpjnKT9Lu5ppNWYMaTt3JBS5AXIvjwM71PV1MmdIfacaVLssr5hTM3UmiBvgxs6qe KME2H00++/GA0AVdhwDnM7qqgUo677tQZAHATCMTwSs/y+gDteJsdMV2I6yXtlyw4D8N gQ8xiIDji8eAdtZL9l6nx5tBHT2q80c2NRV03Tr1WWIn1Ihe533jVsPcU13U+tKCKxlc OhEKB4fgSShQZDPE8+jD/5jWlticVWj8VXX/NgcctwNGK+c+9bIIE2OCdyReUHpTibzF X3VA== X-Gm-Message-State: AAQBX9cxPsZ7EU02al9l0rndox9NvuHL1gE90MmTuqBwoZIWR5GxpiTq tWCzFk8tsPyJCTyc7ZBJuxUO/NBeDtj668t81Oc= X-Google-Smtp-Source: AKy350YjKtJXkgoZAg0c+NG2ZMX6f4nDrfwkJ02ayWIwYpqsSXUqQ/EXqtTfYirSg2rnIWIo5YIvew== X-Received: by 2002:a5d:94ce:0:b0:760:f780:104c with SMTP id y14-20020a5d94ce000000b00760f780104cmr3594557ior.7.1681877020388; Tue, 18 Apr 2023 21:03:40 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:40 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 12/42] part: Allow setting the partition-table type Date: Wed, 19 Apr 2023 16:02:44 +1200 Message-ID: <20230419160308.v2.12.I6e17ea4b4d63a646093f13ef1ff52385b0078bec@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some devices have multiple partition types available on the same media. It is sometimes useful to see these to check that everything is working correctly. Provide a way to manually set the partition-table type, avoiding the auto-detection process. Signed-off-by: Simon Glass --- (no changes since v1) cmd/part.c | 34 +++++++++++++++++++ disk/part.c | 16 +++++++++ doc/usage/cmd/part.rst | 74 ++++++++++++++++++++++++++++++++++++++++++ include/part.h | 9 +++++ 4 files changed, 133 insertions(+) diff --git a/cmd/part.c b/cmd/part.c index 28f2b7ff9bbe..0ce190005d32 100644 --- a/cmd/part.c +++ b/cmd/part.c @@ -182,6 +182,36 @@ static int do_part_number(int argc, char *const argv[]) return do_part_info(argc, argv, CMD_PART_INFO_NUMBER); } +static int do_part_set(int argc, char *const argv[]) +{ + const char *devname, *partstr, *typestr; + struct blk_desc *desc; + int dev; + + if (argc < 3) + return CMD_RET_USAGE; + + /* Look up the device */ + devname = argv[0]; + partstr = argv[1]; + typestr = argv[2]; + dev = blk_get_device_by_str(devname, partstr, &desc); + if (dev < 0) { + printf("** Bad device specification %s %s **\n", devname, + partstr); + return CMD_RET_FAILURE; + } + + desc->part_type = part_get_type_by_name(typestr); + if (!desc->part_type) { + printf("Unknown partition type '%s'\n", typestr); + return CMD_RET_FAILURE; + } + part_print(desc); + + return 0; +} + #ifdef CONFIG_PARTITION_TYPE_GUID static int do_part_type(int argc, char *const argv[]) { @@ -245,6 +275,8 @@ static int do_part(struct cmd_tbl *cmdtp, int flag, int argc, return do_part_number(argc - 2, argv + 2); else if (!strcmp(argv[1], "types")) return do_part_types(argc - 2, argv + 2); + else if (!strcmp(argv[1], "set")) + return do_part_set(argc - 2, argv + 2); #ifdef CONFIG_PARTITION_TYPE_GUID else if (!strcmp(argv[1], "type")) return do_part_type(argc - 2, argv + 2); @@ -279,6 +311,8 @@ U_BOOT_CMD( #endif "part type : \n" " - set environment variable to partition type\n" + "part set type\n" + " - set partition type for a device\n" "part types\n" " - list supported partition table types" ); diff --git a/disk/part.c b/disk/part.c index 35300df59039..1d2117ab71ee 100644 --- a/disk/part.c +++ b/disk/part.c @@ -54,6 +54,22 @@ static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc) return NULL; } +int part_get_type_by_name(const char *name) +{ + struct part_driver *drv = + ll_entry_start(struct part_driver, part_driver); + const int n_ents = ll_entry_count(struct part_driver, part_driver); + struct part_driver *entry; + + for (entry = drv; entry != drv + n_ents; entry++) { + if (!strcasecmp(name, entry->name)) + return entry->part_type; + } + + /* Not found */ + return PART_TYPE_UNKNOWN; +} + static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart) { struct blk_desc *dev_desc; diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst index 8d2a2803912d..8a594aaff27e 100644 --- a/doc/usage/cmd/part.rst +++ b/doc/usage/cmd/part.rst @@ -13,6 +13,7 @@ Synopis part start part size part number + part set part type : [varname] part types @@ -82,6 +83,18 @@ part must be specified as partition name. varname a variable to store the current partition number value into +The 'part set' command sets the type of a partition. This is useful when +autodetection fails or does not do the correct thing: + + interface + interface for accessing the block device (mmc, sata, scsi, usb, ....) + dev + device number + part + partition number + type + partition type to use (see 'part types') to check available types + The 'part type' command prints or sets an environment variable to the partition type UUID. interface @@ -147,6 +160,67 @@ Examples => part types Supported partition tables: EFI, AMIGA, DOS, ISO, MAC +This shows looking at a device with multiple partition tables:: + + => virtio scan + => part list virtio 0 + + Partition Map for VirtIO device 0 -- Partition Type: EFI + + Part Start LBA End LBA Name + Attributes + Type GUID + Partition GUID + 1 0x00000040 0x0092b093 "ISO9660" + attrs: 0x1000000000000001 + type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 + guid: a0891d7e-b930-4513-94d8-f629dbd637b2 + 2 0x0092b094 0x0092d7e7 "Appended2" + attrs: 0x0000000000000000 + type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b + guid: a0891d7e-b930-4513-94db-f629dbd637b2 + 3 0x0092d7e8 0x0092da3f "Gap1" + attrs: 0x1000000000000001 + type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 + guid: a0891d7e-b930-4513-94da-f629dbd637b2 + => ls virtio 0:3 + => part types + Supported partition tables: EFI, DOS, ISO + => part set virtio 0 dos + + Partition Map for VirtIO device 0 -- Partition Type: DOS + + Part Start Sector Num Sectors UUID Type + 1 1 9624191 00000000-01 ee + => part set virtio 0 iso + + Partition Map for VirtIO device 0 -- Partition Type: ISO + + Part Start Sect x Size Type + 1 3020 4 512 U-Boot + 2 9613460 10068 512 U-Boot + => part set virtio 0 efi + + Partition Map for VirtIO device 0 -- Partition Type: EFI + + Part Start LBA End LBA Name + Attributes + Type GUID + Partition GUID + 1 0x00000040 0x0092b093 "ISO9660" + attrs: 0x1000000000000001 + type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 + guid: a0891d7e-b930-4513-94d8-f629dbd637b2 + 2 0x0092b094 0x0092d7e7 "Appended2" + attrs: 0x0000000000000000 + type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b + guid: a0891d7e-b930-4513-94db-f629dbd637b2 + 3 0x0092d7e8 0x0092da3f "Gap1" + attrs: 0x1000000000000001 + type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 + guid: a0891d7e-b930-4513-94da-f629dbd637b2 + => + Return value ------------ diff --git a/include/part.h b/include/part.h index be75c7354955..3b1b5398699c 100644 --- a/include/part.h +++ b/include/part.h @@ -598,6 +598,15 @@ static inline struct part_driver *part_driver_get_first(void) return ll_entry_start(struct part_driver, part_driver); } +/** + * part_get_type_by_name() - Get partition type by name + * + * @name: Name of partition type to look up (not case-sensitive) + * Returns: Corresponding partition type (PART_TYPE_...) or PART_TYPE_UNKNOWN if + * not known + */ +int part_get_type_by_name(const char *name); + #else static inline int part_driver_get_count(void) { return 0; } From patchwork Wed Apr 19 04:02:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770507 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=WmQTJ5WS; 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Show this with the 'qfw list' command so that it is possible to dump the data. Signed-off-by: Simon Glass --- (no changes since v1) cmd/qfw.c | 2 +- doc/usage/cmd/qfw.rst | 28 ++++++++++++++++------------ 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/cmd/qfw.c b/cmd/qfw.c index ae3c6a7a84e9..d6ecfa60d5a7 100644 --- a/cmd/qfw.c +++ b/cmd/qfw.c @@ -26,7 +26,7 @@ static int qemu_fwcfg_cmd_list_firmware(void) for (file = qfw_file_iter_init(qfw_dev, &iter); !qfw_file_iter_end(&iter); file = qfw_file_iter_next(&iter)) { - printf("%-56s\n", file->cfg.name); + printf("%08lx %-56s\n", file->addr, file->cfg.name); } return 0; diff --git a/doc/usage/cmd/qfw.rst b/doc/usage/cmd/qfw.rst index cc0e27c27790..76d74278a213 100644 --- a/doc/usage/cmd/qfw.rst +++ b/doc/usage/cmd/qfw.rst @@ -11,6 +11,7 @@ Synopsis qfw list qfw cpus qfw load [kernel_addr [initrd_addr]] + qfw list Description ----------- @@ -41,18 +42,21 @@ QEMU firmware files are listed via the *qfw list* command: :: => qfw list - etc/boot-fail-wait - etc/smbios/smbios-tables - etc/smbios/smbios-anchor - etc/e820 - genroms/kvmvapic.bin - genroms/linuxboot.bin - etc/system-states - etc/acpi/tables - etc/table-loader - etc/tpm/log - etc/acpi/rsdp - bootorder + 00000000 bios-geometry + 00000000 bootorder + 000f0060 etc/acpi/rsdp + bed14040 etc/acpi/tables + 00000000 etc/boot-fail-wait + 00000000 etc/e820 + 00000000 etc/smbios/smbios-anchor + 00000000 etc/smbios/smbios-tables + 00000000 etc/system-states + 00000000 etc/table-loader + 00000000 etc/tpm/log + 00000000 genroms/kvmvapic.bin + +Where an address is shown, it indicates where the data is available for +inspection, e.g. using the :doc:`md`. The available CPUs can be shown via the *qfw cpus* command: From patchwork Wed Apr 19 04:02:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770506 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=a6K9mzOQ; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S046M6yz1ybC for ; Wed, 19 Apr 2023 14:06:28 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 527018621B; Wed, 19 Apr 2023 06:04:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="a6K9mzOQ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 76469861B3; Wed, 19 Apr 2023 06:03:49 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x135.google.com (mail-il1-x135.google.com [IPv6:2607:f8b0:4864:20::135]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A7C08861EF for ; Wed, 19 Apr 2023 06:03:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x135.google.com with SMTP id e9e14a558f8ab-3293e4b2d32so6925415ab.1 for ; Tue, 18 Apr 2023 21:03:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877022; x=1684469022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nkYNnMjBPdn9a8SSS1mtztDVGhH2DNxaBWWvL076OJ0=; b=a6K9mzOQs5mat4OPDXEpNBXvjl3PErWe3da1o3JRFESedA9Sqcwhi/0dcWMgH9Hj7Y aVw1a6DCnnOx+3fO+RjhOF2emyrVDybLX/hhdA6CT02GrgX956yXPcW7biKoKwmlTGwq VmADwl/r4L0Lge1APSrSBiKnbppf2HiQnhu88= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877022; x=1684469022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nkYNnMjBPdn9a8SSS1mtztDVGhH2DNxaBWWvL076OJ0=; b=PKs+fpblsueQtKEJg0ymhYlxDb7rrgZunaYjCPsIL1K8AMSZuIJN0BEf0kMhYk1YkR c2J10mvaEWB0NiZLfbrpY9yBanETJSbYIra4f4dOfIg77ruWVSk0BXwv+OpmtmiGMlSW 2UaHNy5MRqIY6yz91fJy8t29dkxhEv/tjgzbP2iW/Vp2JHtndJrOt8S674JN+5SGScX/ ChIFxzWbltWrGl0yKUnoFLzE3bFaE7zWL2GkZGkUPSezqTk+U8BFTnUfIb5V4ycs8j3u cG6M7n8QjfdDamo1wSua7wXZlSESZHyS8QB4kHxq8hZ6G0piko4HDgbslCnjxA7UWBnq Rvow== X-Gm-Message-State: AAQBX9fVgxynYIIQpQ+UB/ojjbe3eqXz2Zbim0XYKNF1PYPoTXMLtRik EEt0WY3CLfOiUr7PhnnN1g5MtuYgr9qqCytrSt0= X-Google-Smtp-Source: AKy350bUopNQ2RzgllZFdsaECp1oRRFoTCRGaViFF15mvwpoBvH4tZoeg8uGuapd25qaD5yWH2ip9w== X-Received: by 2002:a92:cf10:0:b0:32a:b312:7a96 with SMTP id c16-20020a92cf10000000b0032ab3127a96mr11360384ilo.1.1681877022023; Tue, 18 Apr 2023 21:03:42 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:41 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 14/42] log: Tidy up an ambiguous comment. Date: Wed, 19 Apr 2023 16:02:46 +1200 Message-ID: <20230419160308.v2.14.I85d34b53b3d0b7357458e0a6f85eff95e4b1b26b@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add a a bit more detail so it is clear that multiple devices are supported, but only one per driver. Signed-off-by: Simon Glass --- (no changes since v1) common/log.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/log.c b/common/log.c index 7cfc49bc28a5..ec33b62e8a6f 100644 --- a/common/log.c +++ b/common/log.c @@ -436,7 +436,7 @@ int log_init(void) /* * We cannot add runtime data to the driver since it is likely stored * in rodata. Instead, set up a 'device' corresponding to each driver. - * We only support having a single device. + * We only support having a single device for each driver. */ INIT_LIST_HEAD((struct list_head *)&gd->log_head); while (drv < end) { From patchwork Wed Apr 19 04:02:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770510 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=fMBnBgSQ; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S190cSsz1ybC for ; Wed, 19 Apr 2023 14:07:25 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3AFE186227; Wed, 19 Apr 2023 06:04:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="fMBnBgSQ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 47CC8861CD; Wed, 19 Apr 2023 06:03:55 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x132.google.com (mail-il1-x132.google.com [IPv6:2607:f8b0:4864:20::132]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7D10F861D5 for ; Wed, 19 Apr 2023 06:03:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x132.google.com with SMTP id e9e14a558f8ab-3294fd17f1cso10374485ab.1 for ; Tue, 18 Apr 2023 21:03:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877023; x=1684469023; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TcjVODfbxF/HTC0hEqEh4i2juinA3OsaBGLciciMEts=; b=fMBnBgSQ7FFyVfAj3utAOnuVWrlbFQbvRZyHyGquP8tECHDdGylGbqldN8hxBBS1BV nNZnMvLLFpXh3Fbki3MAjgZapxOfbWtZn6Tb2LPD10k7MZPUy9yNUAgpERMRl9b1Cyni sFGBtG62fUZLE4Z6PB0aKiygzOdNJK+Ks2iqM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877023; x=1684469023; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TcjVODfbxF/HTC0hEqEh4i2juinA3OsaBGLciciMEts=; b=DEAdvzvmQ0pLd+vnKXKmk104QXGGGUDzbtltEaG5RAlSxc74qIg5b9hz2gpfljRNTC gx5e2Gb4LcNYrGpH/1jz8ic0gUE+pdhKCm0PRosHGx0zgzieZHTbSvw5/bf3WeRP0erF FgpjKnlE+7IpA6FlWaIwWTGQIVK3/bO/LTq7apjpwxNFv7vGkwk4f3U++KfJYrAJEyBi J+bVb/07AIFwwJ0zVOCVvhNGYZuB8MCAWCO0hpjOvsXbQREv3POXbe8f/XMkumNZLose niQWaab7A2vQrBGKiZcL/YIPBYwPmORVq9+1ESc0oI+wh3ETYZtQsRRVYy7zy39gUjdG 5E2A== X-Gm-Message-State: AAQBX9fUK1nytLiWlJOxN9Y/hVzKvrCPSPOy9MegzKDtGcX96dIkGadH rWWxUoqDERF9oum2mXrYx2L3UhRQ6xOnUm/YzQI= X-Google-Smtp-Source: AKy350ZRJeF/4ibMcvCcpw1SwA/zfdrvGFGjGQ4jKnIFet0XFPHfb/o1x7s+oSlJO5R9ehvfX+3NDA== X-Received: by 2002:a92:c049:0:b0:31f:9b6e:2f4d with SMTP id o9-20020a92c049000000b0031f9b6e2f4dmr13523956ilf.0.1681877022932; Tue, 18 Apr 2023 21:03:42 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:42 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass , Anatolij Gustschin Subject: [PATCH v2 15/42] video: Allow building video drivers for SPL Date: Wed, 19 Apr 2023 16:02:47 +1200 Message-ID: <20230419160308.v2.15.Ib05405d92db5e10a3a58353c985bfbb49186a499@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Update the Makefile rules to allow video drivers in SPL. This is useful for 64-bit QEMU on x86, since the video BIOS can only be run from 32-bit mode (i.e. in SPL). Signed-off-by: Simon Glass --- (no changes since v1) drivers/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/Makefile b/drivers/Makefile index 9fbf1211e84c..5a2792307929 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -37,6 +37,8 @@ obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ obj-$(CONFIG_XEN) += xen/ obj-$(CONFIG_$(SPL_)FPGA) += fpga/ +obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video/ + obj-y += bus/ ifndef CONFIG_TPL_BUILD @@ -97,7 +99,6 @@ obj-y += rtc/ obj-y += scsi/ obj-y += sound/ obj-y += spmi/ -obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ obj-$(CONFIG_U_QE) += qe/ From patchwork Wed Apr 19 04:02:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770508 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=kHiljD30; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S0d23MGz1ybC for ; Wed, 19 Apr 2023 14:06:57 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AF47986224; Wed, 19 Apr 2023 06:04:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="kHiljD30"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 111FB861BF; Wed, 19 Apr 2023 06:03:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x135.google.com (mail-il1-x135.google.com [IPv6:2607:f8b0:4864:20::135]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 79A368619C for ; Wed, 19 Apr 2023 06:03:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x135.google.com with SMTP id e9e14a558f8ab-329326b4f10so8295325ab.2 for ; Tue, 18 Apr 2023 21:03:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877024; x=1684469024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HVBWrlaFwv3pdKRjN2FvpHYhLXxBtEtUdX96gdUZWxs=; b=kHiljD304XkrjUPOMMQ1TKB5XmuyGtZdQrqjq8P+L04lvz/dtkn0SRBCgyP8fNkWFh kDYB7Ue3jBsMlHrjm1avtUNvZzrpAOXuECPOx4WKYJfKhJOfMxkJcV4rf1GQkhKCmFJz NU51QOCP+rcmThOe4KalXL10Vm+wbW7DkvD3U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877024; x=1684469024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HVBWrlaFwv3pdKRjN2FvpHYhLXxBtEtUdX96gdUZWxs=; b=HlYAoO8lL4P3ua4SuQnkENF3rtk316psotYseq2Z7clTmifAgCWvm0FctcTmnMTa5b GQkvkjDb5bVi9L2M7DQ+3BhWUv4Y5HHW9L1ToWZ7uu9ly1zal5eZBEcBpSE9HXNTL3Xs TSZNbha7iYTSNndaWUTzD3S/n6Wwx3h4cy/f1eJIzbCl2424Q6tjqBAOZXdS+UVWI2HL fr3xZjJ3ObkXVvdFoc4pJZA3XnbGSm9I8WRkvEOx5rOi1z+5la97Rm6pSBoRhdhaUyqL hi54NjBKtiNSY2mijW1v4dHqdcr0SPFWPRLio+TeMvgSwyf3t2Q/KmzSDsZj0NtjRwqv tCKw== X-Gm-Message-State: AAQBX9fChrTRFnT4/yqELO7O4WRPauDFqwq2GVMlmJbBx2FxJBny4CVh JxQqxF2rL3liTfL7smgZVsD1kfAgUXmZy3KLgNs= X-Google-Smtp-Source: AKy350ZvTLA2Aku6GBalONbgyeeYqhbMjy72vwqr4o6dH4ggoYAfJlzp21OqWH3tX9ItCaG8Hr47vQ== X-Received: by 2002:a92:d80f:0:b0:329:5a6e:3a18 with SMTP id y15-20020a92d80f000000b003295a6e3a18mr13779676ilm.4.1681877023780; Tue, 18 Apr 2023 21:03:43 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:43 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 16/42] qfw: Set the address of the ACPI tables Date: Wed, 19 Apr 2023 16:02:48 +1200 Message-ID: <20230419160308.v2.16.Iaa779cbac7951e7c45f111b8d8324d659104639a@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Once the ACPI tables have been set up, record their address so that it is possible to list them with 'acpi list'. Signed-off-by: Simon Glass --- (no changes since v1) drivers/misc/qfw.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index 9ef95caa8956..0a93feeb4b2e 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -18,6 +18,7 @@ #include #include #include +#include #if defined(CONFIG_GENERATE_ACPI_TABLE) && !defined(CONFIG_SANDBOX) /* @@ -227,6 +228,9 @@ out: } free(table_loader); + + gd_set_acpi_start(acpi_get_rsdp_addr()); + return addr; } From patchwork Wed Apr 19 04:02:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770509 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=amO/YzdM; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S0v1xTKz1ybC for ; Wed, 19 Apr 2023 14:07:11 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 816AB8623D; Wed, 19 Apr 2023 06:04:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="amO/YzdM"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C78B78619C; Wed, 19 Apr 2023 06:03:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x12d.google.com (mail-il1-x12d.google.com [IPv6:2607:f8b0:4864:20::12d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 32F19861B4 for ; Wed, 19 Apr 2023 06:03:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x12d.google.com with SMTP id e9e14a558f8ab-32a8e9173c0so6842115ab.0 for ; Tue, 18 Apr 2023 21:03:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877024; x=1684469024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AvWKKuSGaYoL0/jFCjVO37AwSp+CicHe+W3RYdN09Go=; b=amO/YzdM3R70alxQCxfnoTNguV5ZCNsNypyoNCcuazCrBZVJHPhltSpPXWw4FtiJxx w8ogCQwXttcZ/OccO2kadc4sctFkwI2KreR57V3RJwMU/1KWnWAaCR/7YJNeT4c5Fzt2 VnGXEL59mRWWmVBlIJfgVyDw3D5v7c5TruDwA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877024; x=1684469024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AvWKKuSGaYoL0/jFCjVO37AwSp+CicHe+W3RYdN09Go=; b=ik6eY7kq6GAKUh41NOfGdIpYboCGRcfAkt9pLgR62r6cuCR6NTvUlu99Zz5/Qp2byr M4HUmm1BQufMyK5Av7VhQFccVgJia33kfJswx2BiG9q4Qb1BJEXWyyeoMJzLM/YHMOVo H0HsGEnSE+CtcuAWiPjsJ7tE6PWTPcZ3JQEVocagCYS5ZlQDiYyjizq1MHUzlkTG+mX0 OHpg3xZJnFkBk3WAnIBQTn73sG13iBmWcWMDSNh2OhifH7ft06f/JrAgxuytANJwJd6c J9ZR2awPZN0APEI2ysddWQQLMLJV5IwG6GPWNqo479CR2IUMOjEnKDMM7rqS5ttH/MAb JIsA== X-Gm-Message-State: AAQBX9caGcFdAJtdE0EKVmMBj+MlMPHkYGELP5yLZ70vhfhmE8IE/ibs xEnYEzeHrWcNjkDPlacAPu8DdAb2/5vjNH9iRPA= X-Google-Smtp-Source: AKy350bZz9jtB4CiV99NCeEBQb3N2s917B6eqvcVWKnC7bkQmnBs2HhQTv9j5he2ctvBtsPwFBwBAQ== X-Received: by 2002:a92:908:0:b0:328:ba14:5b38 with SMTP id y8-20020a920908000000b00328ba145b38mr16571182ilg.6.1681877024634; Tue, 18 Apr 2023 21:03:44 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:44 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 17/42] efi: Show all known UUIDs with CONFIG_CMD_EFIDEBUG Date: Wed, 19 Apr 2023 16:02:49 +1200 Message-ID: <20230419160308.v2.17.I8b1d3f1a3ffca2880596902c87d794f4ea59a53a@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The CMD_EFIDEBUG option enables debugging so it is reasonable to assume that all effects should be made to decode the dreaded UUIDs favoured by UEFI. Update the table to show them all when CONFIG_CMD_EFIDEBUG is enabled. Signed-off-by: Simon Glass --- (no changes since v1) lib/uuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/uuid.c b/lib/uuid.c index 96e1af3c8b00..ab30fbf9152f 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -255,7 +255,7 @@ static const struct { EFI_CERT_TYPE_PKCS7_GUID, }, #endif -#ifdef CONFIG_EFI +#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI) { "EFI_LZMA_COMPRESSED", EFI_LZMA_COMPRESSED }, { "EFI_DXE_SERVICES", EFI_DXE_SERVICES }, { "EFI_HOB_LIST", EFI_HOB_LIST }, From patchwork Wed Apr 19 04:02:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770511 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=ac80xH2L; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S1Q50rCz1ybC for ; Wed, 19 Apr 2023 14:07:38 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8DABD86242; Wed, 19 Apr 2023 06:04:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="ac80xH2L"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0A0F4861B8; Wed, 19 Apr 2023 06:03:55 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-io1-xd29.google.com (mail-io1-xd29.google.com [IPv6:2607:f8b0:4864:20::d29]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8488D861CD for ; Wed, 19 Apr 2023 06:03:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-io1-xd29.google.com with SMTP id ca18e2360f4ac-7606d6bb669so99473039f.2 for ; Tue, 18 Apr 2023 21:03:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877026; x=1684469026; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FCS+tLDaMxiAPNyrpbFlHVNTc4OPjWr9f80OOlj1+n4=; b=ac80xH2LlQLqjAfpI+/WHZtANFbkvtGy4Ya6D94/4HF+W92NUArDNwgevcybO0trJX 7Uqs4BGzSEZCpYuvjQcrIIyXCZxJ7hNR+/21n8ITS9iL+Ao9a5XBUXRZvX8M3h+INScM wp/5b927lQq1p7dc5aWJ9Y4jPp+ABxf0/ZMgA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877026; x=1684469026; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FCS+tLDaMxiAPNyrpbFlHVNTc4OPjWr9f80OOlj1+n4=; b=Gd4sl5tjBD5KiqzmalELtHEObGOAK5lS206gdBqtvoAZarQDyQ+XWurHFgVL73FJQr xxesaPY88ss7vdErFsCpRGZoR6X0ElCz2xIs9aK8IJ5CMdSRpifCH7j1A6GcEHHqwJCt ybO2F7d+fFLBNKM+x5HNwImFrqVPjbFXJcuCduvT43ycqd3/Q9TWGL3utVtpEdNLRNYE MiYgb9XK4udopQUKQLg32fzsSJmPmwKO1wI7ZZWYsOG8Rth+QIIJeVaI+ItkhdtG9iQO wdGAbjDMra6LoTjvfBK3C42OqfemJbt0xjYy32/SBId3X/F3kaYaYbMnZrKKQLMMnHQI SR5w== X-Gm-Message-State: AAQBX9eI/rA5VZ7jaN6CjzyixC9XxUp3q9gfZ3HRQ27iiSxj/s3ZBIt1 TO0H8+ROvyYkJtN5Twmc2yztIrqOnfCbwx2t1qw= X-Google-Smtp-Source: AKy350YFZ/VyMspE6eaxNzYcu6P/erCKnUlE+5NcSfyc8fO4yXghLziR9AYgxqjpbO84kQECgeg6Ww== X-Received: by 2002:a92:d80f:0:b0:329:5a6e:3a18 with SMTP id y15-20020a92d80f000000b003295a6e3a18mr13779754ilm.4.1681877025827; Tue, 18 Apr 2023 21:03:45 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:45 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 18/42] x86: Improve the trampoline in 64-bit mode Date: Wed, 19 Apr 2023 16:02:50 +1200 Message-ID: <20230419160308.v2.18.Id9b0fb3198dfc1b7aa6ed0380f4b8f77edc473d6@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean At present this leaves the stack at the pre-relocation value. This is not ideal since we want to have U-Boot running entirely from the top of memory. In addition, the new global_data pointer is not actually used, since the global_data pointer itself is relocated, then the pre-relocation value is changed, so the effective value (after relocation) does not update. Adjust the implementation to follow the 32-bit code more closely, with a trampoline function which is passed the new stack and global_data pointer. This ensures that the correct values come through even when relocating. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/cpu/start64.S | 19 +++++++++++++++++++ arch/x86/include/asm/u-boot-x86.h | 11 +++++++++++ common/board_f.c | 12 +++++++----- 3 files changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S index 7be834788b9f..78e894d2a21a 100644 --- a/arch/x86/cpu/start64.S +++ b/arch/x86/cpu/start64.S @@ -26,3 +26,22 @@ _start: /* Should not return here */ jmp . + +.globl board_init_f_r_trampoline64 +.type board_init_f_r_trampoline64, @function +board_init_f_r_trampoline64: + /* + * SDRAM has been initialised, U-Boot code has been copied into + * RAM, BSS has been cleared and relocation adjustments have been + * made. It is now time to jump into the in-RAM copy of U-Boot + * + * %eax = Address of top of new stack + */ + + /* Stack grows down from top of SDRAM */ + movq %rsi, %rsp + + /* New gd is in rdi */ + + /* Re-enter U-Boot by calling board_init_f_r() */ + call board_init_f_r diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 1d8aa320f535..02a8b0f15270 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -117,6 +117,17 @@ void __noreturn board_init_f_r_trampoline(ulong sp); */ void __noreturn board_init_f_r(void); +/* + * board_init_f_r_trampoline64() - jump to relocated address with new stack + * + * This is the 64-bit version + * + * @new_gd: New global_data pointer to use + * @sp: New stack pointer to pass on to board_init_r() + */ +void __noreturn board_init_f_r_trampoline64(struct global_data *new_gd, + ulong sp); + int arch_misc_init(void); /* Read the time stamp counter */ diff --git a/common/board_f.c b/common/board_f.c index 1688e27071fc..abd589c9c996 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -731,8 +731,7 @@ static int fix_fdt(void) #endif /* ARM calls relocate_code from its crt0.S */ -#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ - !CONFIG_IS_ENABLED(X86_64) +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) static int jump_to_copy(void) { @@ -754,7 +753,11 @@ static int jump_to_copy(void) * (CPU cache) */ arch_setup_gd(gd->new_gd); - board_init_f_r_trampoline(gd->start_addr_sp); +# if CONFIG_IS_ENABLED(X86_64) + board_init_f_r_trampoline64(gd->new_gd, gd->start_addr_sp); +# else + board_init_f_r_trampoline(gd->start_addr_sp); +# endif #else relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); #endif @@ -969,8 +972,7 @@ static const init_fnc_t init_sequence_f[] = { * watchdog device is not serviced is as small as possible. */ cyclic_unregister_all, -#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ - !CONFIG_IS_ENABLED(X86_64) +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) jump_to_copy, #endif NULL, From patchwork Wed Apr 19 04:02:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770512 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:46 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 19/42] Show the malloc base with the bdinfo command Date: Wed, 19 Apr 2023 16:02:51 +1200 Message-ID: <20230419160308.v2.19.Ifeceb389ca067768037fa89ba27000a62fe8c64d@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean It is useful to see the base of the malloc region. This is visible when debugging but not in normal usage. Add it to the global data so that it can be shown. Signed-off-by: Simon Glass --- (no changes since v1) cmd/bdinfo.c | 1 + common/board_r.c | 7 ++++--- include/asm-generic/global_data.h | 11 +++++++++++ 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 4e0c763a7096..f1f8d59673fb 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -148,6 +148,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (IS_ENABLED(CONFIG_CMD_BDINFO_EXTRA)) { bdinfo_print_num_ll("stack ptr", (ulong)&bd); bdinfo_print_num_ll("ram_top ptr", (ulong)gd->ram_top); + bdinfo_print_num_l("malloc base", gd_malloc_start()); } arch_print_bdinfo(); diff --git a/common/board_r.c b/common/board_r.c index d798c00a80a5..4aaa89403117 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -196,7 +196,7 @@ static int initr_barrier(void) static int initr_malloc(void) { - ulong malloc_start; + ulong start; #if CONFIG_VAL(SYS_MALLOC_F_LEN) debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr, @@ -207,8 +207,9 @@ static int initr_malloc(void) * This value MUST match the value of gd->start_addr_sp in board_f.c: * reserve_noncached(). */ - malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN; - mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN), + start = gd->relocaddr - TOTAL_MALLOC_LEN; + gd_set_malloc_start(start); + mem_malloc_init((ulong)map_sysmem(start, TOTAL_MALLOC_LEN), TOTAL_MALLOC_LEN); return 0; } diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index a1e1b9d64005..a5cf87f86b37 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -301,6 +301,10 @@ struct global_data { * @timebase_l: low 32 bits of timer */ unsigned int timebase_l; + /** + * @malloc_start: start of malloc() region + */ + CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA, (ulong malloc_start;)) #if CONFIG_VAL(SYS_MALLOC_F_LEN) /** * @malloc_base: base address of early malloc() @@ -560,6 +564,13 @@ static_assert(sizeof(struct global_data) == GD_SIZE); #define gd_event_state() NULL #endif +#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA) +#define gd_malloc_start() gd->malloc_start +#define gd_set_malloc_start(_val) gd->malloc_start = (_val) +#else +#define gd_malloc_start() 0 +#define gd_set_malloc_start(val) +#endif /** * enum gd_flags - global data flags * From patchwork Wed Apr 19 04:02:52 2023 Content-Type: text/plain; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:47 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 20/42] nvme: Provide more useful debugging messages Date: Wed, 19 Apr 2023 16:02:52 +1200 Message-ID: <20230419160308.v2.20.I60cf14612aa3596f3c00761d66055794f9208995@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When scanning fails it is useful to be able to decode what went wrong. Add some debugging for this. Signed-off-by: Simon Glass --- (no changes since v1) drivers/nvme/nvme.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 74e7a5b01109..a7add66ab4d1 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -578,17 +578,22 @@ static int nvme_set_queue_count(struct nvme_dev *dev, int count) return min(result & 0xffff, result >> 16) + 1; } -static void nvme_create_io_queues(struct nvme_dev *dev) +static int nvme_create_io_queues(struct nvme_dev *dev) { unsigned int i; + int ret; for (i = dev->queue_count; i <= dev->max_qid; i++) if (!nvme_alloc_queue(dev, i, dev->q_depth)) - break; + return log_msg_ret("all", -ENOMEM); - for (i = dev->online_queues; i <= dev->queue_count - 1; i++) - if (nvme_create_queue(dev->queues[i], i)) - break; + for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { + ret = nvme_create_queue(dev->queues[i], i); + if (ret) + return log_msg_ret("cre", ret); + } + + return 0; } static int nvme_setup_io_queues(struct nvme_dev *dev) @@ -598,14 +603,18 @@ static int nvme_setup_io_queues(struct nvme_dev *dev) nr_io_queues = 1; result = nvme_set_queue_count(dev, nr_io_queues); - if (result <= 0) + if (result <= 0) { + log_debug("Cannot set queue count (err=%dE)\n", result); return result; + } dev->max_qid = nr_io_queues; /* Free previously allocated queues */ nvme_free_queues(dev, nr_io_queues + 1); - nvme_create_io_queues(dev); + result = nvme_create_io_queues(dev); + if (result) + return result; return 0; } @@ -683,8 +692,11 @@ int nvme_scan_namespace(void) uclass_foreach_dev(dev, uc) { ret = device_probe(dev); - if (ret) + if (ret) { + log_err("Failed to probe '%s': err=%dE\n", dev->name, + ret); return ret; + } } return 0; @@ -842,8 +854,10 @@ int nvme_init(struct udevice *udev) ndev->dbs = ((void __iomem *)ndev->bar) + 4096; ret = nvme_configure_admin_queue(ndev); - if (ret) + if (ret) { + log_debug("Unable to configure admin queue (err=%dE)\n", ret); goto free_queue; + } /* Allocate after the page size is known */ ndev->prp_pool = memalign(ndev->page_size, MAX_PRP_POOL); @@ -855,8 +869,10 @@ int nvme_init(struct udevice *udev) ndev->prp_entry_num = MAX_PRP_POOL >> 3; ret = nvme_setup_io_queues(ndev); - if (ret) + if (ret) { + log_debug("Unable to setup I/O queues(err=%dE)\n", ret); goto free_queue; + } nvme_get_info_from_identify(ndev); From patchwork Wed Apr 19 04:02:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770514 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:48 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 21/42] pci: Support autoconfig in SPL Date: Wed, 19 Apr 2023 16:02:53 +1200 Message-ID: <20230419160308.v2.21.If68f4c70b5f796494bcaf317d71cf3a322a412f0@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Allow PCI autoconfig to be handled in SPL, so that we can set it up correctly for boards which need to do this before U-Boot proper. This includes qemu-x64_64 which needs to set up the video device while in 32-bit mode. Signed-off-by: Simon Glass --- (no changes since v1) drivers/pci/Kconfig | 8 ++++++++ drivers/pci/pci-uclass.c | 10 +++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index ef328d26525b..165f111a4f5b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -40,6 +40,14 @@ config PCI_PNP help Enable PCI memory and I/O space resource allocation and assignment. +config SPL_PCI_PNP + bool "Enable Plug & Play support for PCI" + help + Enable PCI memory and I/O space resource allocation and assignment. + This is normally not done in SPL, but can be enabled if devices must + be set up in the SPL phase. Often it is enough to manually configure + one device, so this option can be disabled. + config PCI_REGION_MULTI_ENTRY bool "Enable Multiple entries of region type MEMORY in ranges for PCI" help diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 8d27e40338cf..632c1a63cfce 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -722,6 +723,9 @@ static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor, u32 vendev; int index; + if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(PCI_PNP)) + return true; + for (index = 0; !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index, &vendev); @@ -793,7 +797,9 @@ static int pci_find_and_bind_driver(struct udevice *parent, * space is pretty limited (ie: using Cache As RAM). */ if (!(gd->flags & GD_FLG_RELOC) && - !(drv->flags & DM_FLAG_PRE_RELOC)) + !(drv->flags & DM_FLAG_PRE_RELOC) && + (!CONFIG_IS_ENABLED(PCI_PNP) || + spl_phase() != PHASE_SPL)) return log_msg_ret("pre", -EPERM); /* @@ -918,6 +924,8 @@ int pci_bind_bus_devices(struct udevice *bus) } ret = pci_find_and_bind_driver(bus, &find_id, bdf, &dev); + } else { + debug("device: %s\n", dev->name); } if (ret == -EPERM) continue; From patchwork Wed Apr 19 04:02:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770515 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=dtPVol/3; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S2S4QRDz1ybC for ; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:48 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 22/42] pci: Allow the video BIOS to work in SPL with QEMU Date: Wed, 19 Apr 2023 16:02:54 +1200 Message-ID: <20230419160308.v2.22.Ia7bae40a2926dca93050f6c11d753d8f219be1ca@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean QEMU emulates two common machines (Q35 and i440fx) which use mapping to determine whether RAM is present below 1MB. In order to copy the video BIOS to c0000 we need to flip this mapping over to RAM. This does not happen automatically until SPL has finished running. Switch in RAM at these address so that the video BIOS can be loaded and run. This fix was found in the seabios code base. Signed-off-by: Simon Glass --- (no changes since v1) drivers/pci/pci_rom.c | 46 +++++++++++++++++++++++++++++++++++++++++++ include/pci_ids.h | 1 + 2 files changed, 47 insertions(+) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index f0dfe6314907..0f44238bbbc8 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -141,6 +141,49 @@ static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp) return 0; } +#define Q35_HOST_BRIDGE_PAM0 0x90 +#define I440FX_PAM0 0x59 + +/** + * intel_set_writable_ram() - Set RAM to be writable + * + * This is needed for QEMU when using Q35 or I440FX emulation, since otherwise + * there is no RAM available at c0000 + * + * See Intel 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet for + * information about the PAM0-PAM6 registers + */ +static void intel_set_writable_ram(void) +{ + struct udevice *dev; + int pam0 = -1; + int i; + + for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) { + const struct pci_child_plat *pdata = dev_get_parent_plat(dev); + + if (pdata->vendor == PCI_VENDOR_ID_INTEL) { + if (pdata->device == PCI_DEVICE_ID_INTEL_Q35_MCH) { + pam0 = Q35_HOST_BRIDGE_PAM0; + break; + } else if (pdata->device == PCI_DEVICE_ID_INTEL_82441) { + pam0 = I440FX_PAM0; + break; + } + } + } + + if (!dev) + return; + + // Adjust RAM to be writable from c0000 to f0000 + for (i = 1; i <= 6; i++) + dm_pci_write_config8(dev, pam0 + i, 0x33); + + // Also f0000-100000 + dm_pci_write_config8(dev, pam0, 0x30); +} + /** * pci_rom_load() - Load a ROM image and return a pointer to it * @@ -185,6 +228,9 @@ static int pci_rom_load(struct pci_rom_header *rom_header, return -ENOMEM; *allocedp = true; #endif + /* QEMU hacks */ + intel_set_writable_ram(); + if (target != rom_header) { ulong start = get_timer(0); diff --git a/include/pci_ids.h b/include/pci_ids.h index 5ae1b9b7fb6e..33e90c8d2769 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2870,6 +2870,7 @@ #define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916 #define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918 #define PCI_DEVICE_ID_INTEL_ICH9_AHCI 0x2922 +#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 #define PCI_DEVICE_ID_INTEL_I7_MCR 0x2c18 #define PCI_DEVICE_ID_INTEL_I7_MC_TAD 0x2c19 #define PCI_DEVICE_ID_INTEL_I7_MC_RAS 0x2c1a From patchwork Wed Apr 19 04:02:55 2023 Content-Type: text/plain; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:49 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 23/42] pci: Tidy up logging and reporting for video BIOS Date: Wed, 19 Apr 2023 16:02:55 +1200 Message-ID: <20230419160308.v2.23.I45cd86dea07a1d0289d67fd81a4ca9ebd4666220@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When running the ROM the code is not very helpful when something goes wrong. Add a little more debugging and some logging of return values to improve this. Signed-off-by: Simon Glass --- (no changes since v1) drivers/pci/pci_rom.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 0f44238bbbc8..dab0f1979068 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -300,14 +300,16 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), ret = pci_rom_probe(dev, &rom); if (ret) - return ret; + return log_msg_ret("pro", ret); ret = pci_rom_load(rom, &ram, &alloced); - if (ret) + if (ret) { + ret = log_msg_ret("ld", ret); goto err; + } if (!board_should_run_oprom(dev)) { - ret = -ENXIO; + ret = log_msg_ret("run", -ENXIO); goto err; } @@ -345,21 +347,25 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), #ifdef CONFIG_BIOSEMU BE_VGAInfo *info; + log_debug("Running video BIOS with emulator..."); ret = biosemu_setup(dev, &info); if (ret) goto err; biosemu_set_interrupt_handler(0x15, int15_handler); ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true, vesa_mode, &mode_info); + log_debug("done\n"); if (ret) goto err; #endif } else { #if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL) + log_debug("Running video BIOS..."); bios_set_interrupt_handler(0x15, int15_handler); bios_run_on_x86(dev, (unsigned long)ram, vesa_mode, &mode_info); + log_debug("done\n"); #endif } debug("Final vesa mode %#x\n", mode_info.video_mode); From patchwork Wed Apr 19 04:02:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770518 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:50 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 24/42] x86: Allow video-BIOS code to be built for SPL Date: Wed, 19 Apr 2023 16:02:56 +1200 Message-ID: <20230419160308.v2.24.I5d7962e5f9d12c176625cd77882e45ababdb590a@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean With qemu-x86_64 we need to run the video BIOS while in 32-bit mode, i.e. SPL. Add a Kconfig option for this, adjust the Makefile rules and use CONFIG_IS_ENABLED() where needed. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/lib/Makefile | 7 ++++--- arch/x86/lib/bios.c | 2 +- drivers/pci/pci_rom.c | 28 ++++++++++++++-------------- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index b0612ae6dd5f..90a7618ecfde 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -4,16 +4,17 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += bdinfo.o -ifndef CONFIG_X86_64 -ifndef CONFIG_TPL_BUILD + +ifndef CONFIG_$(SPL_TPL_)X86_64 obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o endif -endif + ifndef CONFIG_SPL_BUILD obj-$(CONFIG_X86_32BIT_INIT) += string.o endif + ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_BOOTM) += bootm.o endif diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 8cc686fd146b..e29cae78e509 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -23,7 +23,7 @@ static int (*int_handler[256])(void); /* to have a common register file for interrupt handlers */ -#ifndef CONFIG_BIOSEMU +#if !CONFIG_IS_ENABLED(BIOSEMU) X86EMU_sysEnv _X86EMU_env; #endif diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index dab0f1979068..2d9a2a899ef7 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -344,20 +344,20 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), } if (emulate) { -#ifdef CONFIG_BIOSEMU - BE_VGAInfo *info; - - log_debug("Running video BIOS with emulator..."); - ret = biosemu_setup(dev, &info); - if (ret) - goto err; - biosemu_set_interrupt_handler(0x15, int15_handler); - ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, - true, vesa_mode, &mode_info); - log_debug("done\n"); - if (ret) - goto err; -#endif + if (CONFIG_IS_ENABLED(BIOSEMU)) { + BE_VGAInfo *info; + + log_debug("Running video BIOS with emulator..."); + ret = biosemu_setup(dev, &info); + if (ret) + goto err; + biosemu_set_interrupt_handler(0x15, int15_handler); + ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, + true, vesa_mode, &mode_info); + log_debug("done\n"); + if (ret) + goto err; + } } else { #if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL) log_debug("Running video BIOS..."); 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:58 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 25/42] x86: Pass video settings from SPL to U-Boot proper Date: Wed, 19 Apr 2023 16:02:57 +1200 Message-ID: <20230419160308.v2.25.Ieb0824a81d8ad4109fa501c9497b01b8749f913a@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When video is set up in SPL, U-Boot proper needs to use the correct parameters so it can write to the display. Put these in a bloblist so they are available to U-Boot proper. Signed-off-by: Simon Glass --- (no changes since v1) drivers/pci/pci_rom.c | 78 +++++++++++++++++++++++++++++++------------ include/bloblist.h | 1 + include/video.h | 24 +++++++++++++ 3 files changed, 82 insertions(+), 21 deletions(-) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 2d9a2a899ef7..ecb6da64c5c9 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include @@ -34,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -420,34 +422,68 @@ int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void)) printf("Not available (previous bootloader prevents it)\n"); return -EPERM; } - bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); - ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE | - PCI_ROM_ALLOW_FALLBACK); - bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD); - if (ret) { - debug("failed to run video BIOS: %d\n", ret); - return ret; - } - ret = vesa_setup_video_priv(&mode_info.vesa, - mode_info.vesa.phys_base_ptr, uc_priv, - plat); - if (ret) { - if (ret == -ENFILE) { - /* - * See video-uclass.c for how to set up reserved memory - * in your video driver - */ - log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set up no reserved memory\n", - dev->driver->name); + /* In U-Boot proper, collect the information added by SPL (see below) */ + if (IS_ENABLED(CONFIG_SPL_VIDEO) && spl_phase() > PHASE_SPL && + CONFIG_IS_ENABLED(BLOBLIST)) { + struct video_handoff *ho; + + ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho)); + if (!ho) + return log_msg_ret("blf", -ENOENT); + plat->base = ho->fb; + plat->size = ho->size; + uc_priv->xsize = ho->xsize; + uc_priv->ysize = ho->ysize; + uc_priv->line_length = ho->line_length; + uc_priv->bpix = ho->bpix; + } else { + bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); + ret = dm_pci_run_vga_bios(dev, int15_handler, + PCI_ROM_USE_NATIVE | + PCI_ROM_ALLOW_FALLBACK); + bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD); + if (ret) { + debug("failed to run video BIOS: %d\n", ret); + return ret; } - debug("No video mode configured\n"); - return ret; + ret = vesa_setup_video_priv(&mode_info.vesa, + mode_info.vesa.phys_base_ptr, + uc_priv, plat); + if (ret) { + if (ret == -ENFILE) { + /* + * See video-uclass.c for how to set up reserved + * memory in your video driver + */ + log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set up no reserved memory\n", + dev->driver->name); + } + + debug("No video mode configured\n"); + return ret; + } } printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, mode_info.vesa.bits_per_pixel); + /* In SPL, store the information for use by U-Boot proper */ + if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) { + struct video_handoff *ho; + + ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0); + if (!ho) + return log_msg_ret("blc", -ENOMEM); + + ho->fb = plat->base; + ho->size = plat->size; + ho->xsize = uc_priv->xsize; + ho->ysize = uc_priv->ysize; + ho->line_length = uc_priv->line_length; + ho->bpix = uc_priv->bpix; + } + return 0; } diff --git a/include/bloblist.h b/include/bloblist.h index 2a2f1700eb09..7ea72c6bd46d 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -113,6 +113,7 @@ enum bloblist_tag_t { BLOBLISTT_PROJECT_AREA = 0x8000, BLOBLISTT_U_BOOT_SPL_HANDOFF = 0x8000, /* Hand-off info from SPL */ BLOBLISTT_VBE = 0x8001, /* VBE per-phase state */ + BLOBLISTT_U_BOOT_VIDEO = 0x8002, /* Video information from SPL */ /* * Vendor-specific tags are permitted here. Projects can be open source diff --git a/include/video.h b/include/video.h index 29c4f51efb08..18ed159b8d84 100644 --- a/include/video.h +++ b/include/video.h @@ -133,6 +133,30 @@ struct video_ops { #define video_get_ops(dev) ((struct video_ops *)(dev)->driver->ops) +/** + * struct video_handoff - video information passed from SPL + * + * This is used when video is set up by SPL, to provide the details to U-Boot + * proper. + * + * @fb: Base address of frame buffer, 0 if not yet known + * @size: Frame-buffer size, in bytes + * @xsize: Number of pixel columns (e.g. 1366) + * @ysize: Number of pixels rows (e.g.. 768) + * @line_length: Length of each frame buffer line, in bytes. This can be + * set by the driver, but if not, the uclass will set it after + * probing + * @bpix: Encoded bits per pixel (enum video_log2_bpp) + */ +struct video_handoff { + u64 fb; + u32 size; + ushort xsize; + ushort ysize; + u32 line_length; + u8 bpix; +}; + /** enum colour_idx - the 16 colors supported by consoles */ enum colour_idx { VID_BLACK = 0, From patchwork Wed Apr 19 04:02:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770520 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=SRbjya5J; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S3k31DNz1ybC for ; Wed, 19 Apr 2023 14:09:38 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 10AF586258; Wed, 19 Apr 2023 06:04:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="SRbjya5J"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0034786225; Wed, 19 Apr 2023 06:04:12 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x12c.google.com (mail-il1-x12c.google.com [IPv6:2607:f8b0:4864:20::12c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7AF7A86208 for ; Wed, 19 Apr 2023 06:04:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x12c.google.com with SMTP id e9e14a558f8ab-32a7770f7d1so41688415ab.1 for ; Tue, 18 Apr 2023 21:04:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877040; x=1684469040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SpFVaIyYlJjY7jP+oDWPqYw1o1uBGRnN828g5ggroIM=; b=SRbjya5Jv5e1gkn0esnl+qq2lKqyUmShdo4ASQdHElaSvvNUSYUNXoPOWylMjVwElS GgwspLSX5Pk/SF25y8zcaXKlD2EFmoQFbEo11V7OauXqHGF9+SL94y5pc9crgsvqjGc7 i3TUV8VKb+DqtT24KckFod43dVBifexQKTiRo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877040; x=1684469040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SpFVaIyYlJjY7jP+oDWPqYw1o1uBGRnN828g5ggroIM=; b=JiaLeLdlY8DVG4wMxO7Ja4B01vDhCZBVtVpmQoD0GKQhUPsBYbcOtcp2mKA3OuHNEA NWs5H/5vqdqW3/kDgsRo+RF7yB7JaO8QRmrVsnz1nuHavnv+8NAYFeEiS6q4tfc+1fZz f2fpyxX4YeT9IfCxNHSlwCpoBcj5Mo/W+sO1zUhP0n+JWkR4H1Fb2EO0Fb8be3HPpYFV YLUF6G4ryn6E372WrLGHrsrAYQAh5aATyIhlVNzPSyTXbhRCJBiJtUXxRf8eTrNK/k09 y6cuD/KLUfDrg7WSzodAgHFN6ouv83ubDI/oK+xn0ZocHTbgwKaoAew2xA/yj5Sgc8Yi bOCA== X-Gm-Message-State: AAQBX9c2YLMtmDDUEgpno7ydFd8h+Snq8tUB6PHqq0BZSIPDYv75GG9U TvTGmnKzqytYMtXY3lG/I5Zs63AHj4v7Id/8dr0= X-Google-Smtp-Source: AKy350Z1p256rzItGvv4weD3jKhqcWkdcJ3ruAUEmh1+V46cPzqEgA/HQJ6zFl3Ad3kvfQnaikhQfQ== X-Received: by 2002:a05:6e02:1d11:b0:315:6f9d:e75 with SMTP id i17-20020a056e021d1100b003156f9d0e75mr914681ila.7.1681877039926; Tue, 18 Apr 2023 21:03:59 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:03:59 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 26/42] x86: Init video in SPL if enabled Date: Wed, 19 Apr 2023 16:02:58 +1200 Message-ID: <20230419160308.v2.26.I51e48cfd19ef0c0ff56d7d51c52d789b41112378@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean When video is required in SPL, set this up ready for use. Ignore any problems since it may be that video is not actually available and we still want to continue on to U-Boot proper in that case. Make sure that the SPL banner is only shown once. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/lib/spl.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 7cf14f682da1..fc25771cb1f6 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -97,7 +98,8 @@ static int x86_spl_init(void) return ret; } #endif - preloader_console_init(); + if (!IS_ENABLED(CONFIG_SPL_BOARD_INIT)) + preloader_console_init(); #if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU) ret = print_cpuinfo(); if (ret) { @@ -257,4 +259,12 @@ void spl_board_init(void) #ifndef CONFIG_TPL preloader_console_init(); #endif + + if (CONFIG_IS_ENABLED(VIDEO)) { + struct udevice *dev; + + /* Set up PCI video in SPL if required */ + uclass_first_device_err(UCLASS_PCI, &dev); + uclass_first_device_err(UCLASS_VIDEO, &dev); + } } From patchwork Wed Apr 19 04:02:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770522 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:00 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 27/42] pci: Adjust video BIOS debugging to be SPL-friendly Date: Wed, 19 Apr 2023 16:02:59 +1200 Message-ID: <20230419160308.v2.27.I1836aeeacba0a24343a818c39a7e617cf9a301db@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean A hex value is expected for the VGA mode. Drop the 0x prefix, which is not supported in SPL. Signed-off-by: Simon Glass --- (no changes since v1) drivers/pci/pci_rom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index ecb6da64c5c9..62cfe60c0fb2 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -319,7 +319,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), defined(CONFIG_FRAMEBUFFER_VESA_MODE) vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE; #endif - debug("Selected vesa mode %#x\n", vesa_mode); + debug("Selected vesa mode %x\n", vesa_mode); if (exec_method & PCI_ROM_USE_NATIVE) { #ifdef CONFIG_X86 @@ -370,7 +370,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), log_debug("done\n"); #endif } - debug("Final vesa mode %#x\n", mode_info.video_mode); + debug("Final vesa mode %x\n", mode_info.video_mode); ret = 0; err: From patchwork Wed Apr 19 04:03:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770521 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:01 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 28/42] pci: Mask the ROM address in case it is already enabled Date: Wed, 19 Apr 2023 16:03:00 +1200 Message-ID: <20230419160308.v2.28.I5d4da5b2cfd954fe701b870764873f8beee29328@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean In some cases the video ROM may have been enabled previously, such as by a previous firmware stage. Use the correct address in that case. Signed-off-by: Simon Glass --- (no changes since v1) drivers/pci/pci_rom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 62cfe60c0fb2..ba2cf18d53eb 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -93,6 +93,7 @@ static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp) debug("%s: rom_address=%x\n", __func__, rom_address); return -ENOENT; } + rom_address &= PCI_ROM_ADDRESS_MASK; /* Enable expansion ROM address decoding. */ dm_pci_write_config32(dev, PCI_ROM_ADDRESS, From patchwork Wed Apr 19 04:03:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770523 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=CmqqW0u/; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S4T2JQnz1yZk for ; Wed, 19 Apr 2023 14:10:17 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 707C086262; Wed, 19 Apr 2023 06:04:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="CmqqW0u/"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9865686232; Wed, 19 Apr 2023 06:04:16 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-io1-xd32.google.com (mail-io1-xd32.google.com [IPv6:2607:f8b0:4864:20::d32]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9515E86215 for ; Wed, 19 Apr 2023 06:04:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-io1-xd32.google.com with SMTP id ca18e2360f4ac-7606d44e074so77090939f.1 for ; Tue, 18 Apr 2023 21:04:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877042; x=1684469042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FywEGnP5jjtU2R4M7CgbNRrCHhRNDUu5cy7tOOEz85w=; b=CmqqW0u/vyCtZ7NutL06oqAP/tRP50ngl1FA8L1/gcI0HYsFaA4O+rTvQu5GFFIKgQ JkCsp9C8xPqyB9Sbqyyx5qf9YTgn0gi4B0rki8VvxDyInnNSLG6Io1+eKCxethUtUbsB 8YZEczbhd1TeQ+vgpNRwYwSg8cPSFNGLhjp/E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877042; x=1684469042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FywEGnP5jjtU2R4M7CgbNRrCHhRNDUu5cy7tOOEz85w=; b=NnH9tINrJX2x9x/GK/8GqMoX7zMti1+hrSYvMZsaytYSDqJd8LrTiSQBM+b1l4kWNq jAhtRL/1NvbFyV1MIzZZ38kVk/E+OnvdhRT9NMhvJtaqBah3lHkyfAl3ahQPMfjlxC/t xN+XiTIe6/zKyhNCPoVk7Jjs7Yl2UB72fOnCcXpUFDBYPXVdRsvrh3eiAZ3UykFPigph pQYH/S8K7BX2M/8jqWbv6lPmDWGW6fKau1+YQE8oaU24mZyFm4D/aZhxLSYK+K2T/zMt VqwnxlzbA/RAl/15CYdvMUtvZHOX0NxOao4kHA5Zth/N5ejBgFsY/gy+xi6nXvq6Urwi unqA== X-Gm-Message-State: AAQBX9cucvVO9a5v1ewbpkBK9paTcMBQrWUDwW75FnxuMZ7VebmIr1s9 HkSDaA7LYmrbsxcGkmedIv8n7LZNDnXOqFEkJpA= X-Google-Smtp-Source: AKy350bbrpG8vvaPnEyUjiKfJLXUizvfSNbyYXFggUDPQrGg+aGHMRZbc3zaL3CjJQzo/x4Jwk9Lyg== X-Received: by 2002:a05:6602:328d:b0:760:e9b6:e6ca with SMTP id d13-20020a056602328d00b00760e9b6e6camr3580707ioz.2.1681877042608; Tue, 18 Apr 2023 21:04:02 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:02 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 29/42] x86: Enable display for QEMU 64-bit Date: Wed, 19 Apr 2023 16:03:01 +1200 Message-ID: <20230419160308.v2.29.I28405fcd995a3bf63b2ad6f650d6fc5210953925@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Enable the various options needed for display to work on the qemu-x86_64 board. This includes expanding the available malloc() memory in SPL, since the PCI bus must be enumerated in order to find the video device. It also includes enabling a bloblist, so that the video parameters can be passed. This is placed at address 10000 but is not needed after U-Boot proper reads the information there. Signed-off-by: Simon Glass --- (no changes since v1) configs/qemu-x86_64_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index f29a5aa0f813..371ca9de8429 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -7,6 +7,7 @@ CONFIG_MAX_CPUS=2 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" CONFIG_SPL_TEXT_BASE=0xfffd0000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_X86_RUN_64BIT=y @@ -29,7 +30,10 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_ADDR=0x10000 CONFIG_SPL_NO_BSS_LIMIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_CPU=y CONFIG_SPL_ENV_SUPPORT=y @@ -69,10 +73,12 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y +CONFIG_SPL_PCI_PNP=y CONFIG_SPL_DM_RTC=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y +CONFIG_SPL_VIDEO=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_USER=y CONFIG_FRAMEBUFFER_VESA_MODE=0x144 From patchwork Wed Apr 19 04:03:02 2023 Content-Type: text/plain; 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Disable logging when making the change, then reenable it afterwards, so that logging works normally. Signed-off-by: Simon Glass --- (no changes since v1) arch/x86/lib/spl.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index fc25771cb1f6..6d2291ba65f4 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -139,9 +139,22 @@ static int x86_spl_init(void) */ gd->new_gd = (struct global_data *)ptr; memcpy(gd->new_gd, gd, sizeof(*gd)); + + /* + * Make sure logging is disabled when we switch, since the log system + * list head will move + */ + gd->new_gd->flags &= ~GD_FLG_LOG_READY; arch_setup_gd(gd->new_gd); gd->start_addr_sp = (ulong)ptr; + /* start up logging again, with the new list-head location */ + ret = log_init(); + if (ret) { + log_debug("Log setup failed (err=%d)\n", ret); + return ret; + } + if (_LOG_DEBUG) { ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP); if (ret) From patchwork Wed Apr 19 04:03:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770526 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:04 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass , =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= Subject: [PATCH v2 31/42] fs: fat: Shrink the size of a few strings Date: Wed, 19 Apr 2023 16:03:03 +1200 Message-ID: <20230419160308.v2.31.If2eea014ebc68815d68f373640c80a761a082f83@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean To save a few bytes, replace Error with ** and try to use the same string for multiple messages where possible. Signed-off-by: Simon Glass --- Changes in v2: - Drop ** in strings and use log_err() for messages fs/fat/fat.c | 20 +++++++++++--------- fs/fat/fat_write.c | 14 ++++---------- 2 files changed, 15 insertions(+), 19 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 2da93dae3cf3..d1476aa433d6 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -8,6 +8,8 @@ * 2003-03-10 - kharris@nexus-tech.net - ported to uboot */ +#define LOG_CATEGORY LOGC_FS + #include #include #include @@ -97,8 +99,8 @@ int fat_register_device(struct blk_desc *dev_desc, int part_no) /* Read the partition table, if present */ if (part_get_info(dev_desc, part_no, &info)) { if (part_no != 0) { - printf("** Partition %d not valid on device %d **\n", - part_no, dev_desc->devnum); + log_err("Partition %d invalid on device %d\n", part_no, + dev_desc->devnum); return -1; } @@ -168,7 +170,7 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry) __u32 ret = 0x00; if (CHECK_CLUST(entry, mydata->fatsize)) { - printf("Error: Invalid FAT entry: 0x%08x\n", entry); + log_err("Invalid FAT entry: %#08x\n", entry); return ret; } @@ -586,19 +588,19 @@ static int get_fs_info(fsdata *mydata) mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0]; mydata->clust_size = bs.cluster_size; if (mydata->sect_size != cur_part_info.blksz) { - printf("Error: FAT sector size mismatch (fs=%hu, dev=%lu)\n", - mydata->sect_size, cur_part_info.blksz); + log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n", + mydata->sect_size, cur_part_info.blksz); return -1; } if (mydata->clust_size == 0) { - printf("Error: FAT cluster size not set\n"); + log_err("FAT cluster size not set\n"); return -1; } if ((unsigned int)mydata->clust_size * mydata->sect_size > MAX_CLUSTSIZE) { - printf("Error: FAT cluster size too big (cs=%u, max=%u)\n", - (unsigned int)mydata->clust_size * mydata->sect_size, - MAX_CLUSTSIZE); + log_err("FAT cluster size too big (cs=%u, max=%u)\n", + (uint)mydata->clust_size * mydata->sect_size, + MAX_CLUSTSIZE); return -1; } diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 413fc432ebed..e2a9913f807a 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -1571,8 +1571,9 @@ int fat_unlink(const char *filename) char *filename_copy, *dirname, *basename; filename_copy = strdup(filename); - if (!filename_copy) { - printf("Error: allocating memory\n"); + itr = malloc_cache_aligned(sizeof(fat_itr)); + if (!itr || !filename_copy) { + printf("Error: out of memory\n"); ret = -ENOMEM; goto exit; } @@ -1584,13 +1585,6 @@ int fat_unlink(const char *filename) goto exit; } - itr = malloc_cache_aligned(sizeof(fat_itr)); - if (!itr) { - printf("Error: allocating memory\n"); - ret = -ENOMEM; - goto exit; - } - ret = fat_itr_root(itr, &fsdata); if (ret) goto exit; @@ -1605,7 +1599,7 @@ int fat_unlink(const char *filename) } if (!find_directory_entry(itr, basename)) { - printf("%s: doesn't exist\n", basename); + log_err("%s: doesn't exist (%d)\n", basename, -ENOENT); ret = -ENOENT; goto exit; } From patchwork Wed Apr 19 04:03:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770527 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:04 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass , =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= Subject: [PATCH v2 32/42] fs: fat: Support reading from a larger block size Date: Wed, 19 Apr 2023 16:03:04 +1200 Message-ID: <20230419160308.v2.32.Ia13846500fab3d5a1d5573db11a040d233994fa6@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean At present it is not possible to read from some CDROM drives since the FAT sector size does not match the media's block size. Add a conversion option for this, so that reading is possible. This does increase SPL size for read-only FAT support by 25 bytes but all but 6 are covered by the previous patch. We could reduce the overhead of this feature to 0 bytes by making the code uglier (using a static variable). Signed-off-by: Simon Glass --- Changes in v2: - Use log_warning() for the warning fs/fat/Kconfig | 13 ++++++ fs/fat/fat.c | 107 ++++++++++++++++++++++++++++++++++++++++----- fs/fat/fat_write.c | 8 ++-- 3 files changed, 114 insertions(+), 14 deletions(-) diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig index 9bb11eac9f7a..b0aa888c6cc4 100644 --- a/fs/fat/Kconfig +++ b/fs/fat/Kconfig @@ -22,3 +22,16 @@ config FS_FAT_MAX_CLUSTSIZE is the smallest amount of disk space that can be used to hold a file. Unless you have an extremely tight memory memory constraints, leave the default. + +config FAT_BLK_XLATE + bool "Enable FAT filesystem on a device with a larger block size" + depends on FS_FAT + help + This provides a simple translation mechanism for reading FAT + filesystems which don't use the same sector size as the underlying + media. For example, the FAT filesystem may use 512 bytes but the + media uses 2048, e.g. on a CDROM drive. + + This only supports the case where the FAT filesystem's sector size is + smaller than the media's block size. It does not support creating or + writing files. diff --git a/fs/fat/fat.c b/fs/fat/fat.c index d1476aa433d6..686b321163fb 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -45,13 +45,93 @@ static struct disk_partition cur_part_info; #define DOS_FS_TYPE_OFFSET 0x36 #define DOS_FS32_TYPE_OFFSET 0x52 -static int disk_read(__u32 block, __u32 nr_blocks, void *buf) +/** + * disk_read_conv() - Read blocks and break them into smaller ones + * + * This is used when the FAT filesystem is hosted on a block device with a + * block size greated than 512 bytes, e.g. the 2048 bytes of a CDROM drive. It + * reads the blocks into a buffer and pulls out what is requested by the calling + * function. + * + * It uses an internal 2KB buffer on the stack. + * + * @mydata: Filesystem information + * @block: Block number to read, in terms of mydata->sect_size + * @nr_blocks: Number of blocks to read, in terms of mydata->sect_size + * @buf: Buffer for data + */ +static int disk_read_conv(fsdata *mydata, __u32 block, __u32 nr_blocks, + void *buf) +{ + uint factor, whole, remain, upto; + ulong base, index; + uint to_copy; + u8 tbuf[2048]; + int ret; + + log_debug("mydata %x, cur_dev %lx, block %x, nr_block %x\n", + mydata->sect_size, cur_dev->blksz, block, nr_blocks); + if (mydata->sect_size > cur_dev->blksz || + cur_dev->blksz > sizeof(tbuf)) { + log_err("Block size %lx not supported\n", cur_dev->blksz); + return -EIO; + } + factor = cur_dev->blksz / mydata->sect_size; + + /* get the first partial block */ + base = cur_part_info.start + block / factor; + index = block % factor; + log_debug("cur_part_info.start %llx, block %x, base %lx, index %lx\n", + (unsigned long long)cur_part_info.start, block, base, index); + ret = blk_dread(cur_dev, base, 1, tbuf); + if (ret != 1) + return -EIO; + + to_copy = min((ulong)nr_blocks, factor - index); + log_debug("to_copy %x\n", to_copy); + memcpy(buf, tbuf + index * mydata->sect_size, + to_copy * mydata->sect_size); + upto = to_copy; + + /* load any whole blocks */ + remain = nr_blocks - upto; + whole = remain / factor; + log_debug("factor %x, whole %x, remain %x\n", factor, whole, remain); + if (whole) { + ret = blk_dread(cur_dev, base + 1, whole, + buf + upto * mydata->sect_size); + if (ret != whole) + return -EIO; + upto += whole * factor; + remain = nr_blocks - upto; + } + + /* load any blocks at the end */ + log_debug("end: remain %x\n", remain); + if (remain) { + ret = blk_dread(cur_dev, base + 1 + whole, 1, tbuf); + if (ret != 1) + return -EIO; + memcpy(buf + upto * mydata->sect_size, tbuf, + remain * mydata->sect_size); + upto += remain; + } + + return upto; +} + +static int disk_read(fsdata *mydata, __u32 block, __u32 nr_blocks, void *buf) { ulong ret; if (!cur_dev) return -1; + /* support converting from a larger block size */ + if (IS_ENABLED(CONFIG_FAT_BLK_XLATE) && mydata && + mydata->sect_size != cur_dev->blksz) + return disk_read_conv(mydata, block, nr_blocks, buf); + ret = blk_dread(cur_dev, cur_part_info.start + block, nr_blocks, buf); if (ret != nr_blocks) @@ -68,7 +148,7 @@ int fat_set_blk_dev(struct blk_desc *dev_desc, struct disk_partition *info) cur_part_info = *info; /* Make sure it has a valid FAT header */ - if (disk_read(0, 1, buffer) != 1) { + if (disk_read(NULL, 0, 1, buffer) != 1) { cur_dev = NULL; return -1; } @@ -213,7 +293,7 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry) if (flush_dirty_fat_buffer(mydata) < 0) return -1; - if (disk_read(startblock, getsize, bufptr) < 0) { + if (disk_read(mydata, startblock, getsize, bufptr) < 0) { debug("Error reading FAT blocks\n"); return ret; } @@ -267,7 +347,7 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) debug("FAT: Misaligned buffer address (%p)\n", buffer); while (size >= mydata->sect_size) { - ret = disk_read(startsect++, 1, tmpbuf); + ret = disk_read(mydata, startsect++, 1, tmpbuf); if (ret != 1) { debug("Error reading data (got %d)\n", ret); return -1; @@ -281,7 +361,7 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) __u32 bytes_read; __u32 sect_count = size / mydata->sect_size; - ret = disk_read(startsect, sect_count, buffer); + ret = disk_read(mydata, startsect, sect_count, buffer); if (ret != sect_count) { debug("Error reading data (got %d)\n", ret); return -1; @@ -294,7 +374,7 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) if (size) { ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size); - ret = disk_read(startsect, 1, tmpbuf); + ret = disk_read(mydata, startsect, 1, tmpbuf); if (ret != 1) { debug("Error reading data (got %d)\n", ret); return -1; @@ -506,7 +586,7 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) return -1; } - if (disk_read(0, 1, block) < 0) { + if (disk_read(NULL, 0, 1, block) < 0) { debug("Error: reading block\n"); goto fail; } @@ -588,9 +668,14 @@ static int get_fs_info(fsdata *mydata) mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0]; mydata->clust_size = bs.cluster_size; if (mydata->sect_size != cur_part_info.blksz) { - log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n", - mydata->sect_size, cur_part_info.blksz); - return -1; + if (IS_ENABLED(CONFIG_FAT_BLK_XLATE)) { + log_warning("FAT sector size mismatch (fs=%u, dev=%lu): translating for read-only\n", + mydata->sect_size, cur_part_info.blksz); + } else { + log_err("FAT sector size mismatch (fs=%u, dev=%lu), see CONFIG_FAT_BLK_XLATE\n", + mydata->sect_size, cur_part_info.blksz); + return -1; + } } if (mydata->clust_size == 0) { log_err("FAT cluster size not set\n"); @@ -848,7 +933,7 @@ void *fat_next_cluster(fat_itr *itr, unsigned int *nbytes) * dent at a time and iteratively constructing the vfat long * name. */ - ret = disk_read(sect, read_size, itr->block); + ret = disk_read(itr->fsdata, sect, read_size, itr->block); if (ret < 0) { debug("Error: reading block\n"); return NULL; diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index e2a9913f807a..95f7a60caa2b 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -477,7 +477,7 @@ static int set_fatent_value(fsdata *mydata, __u32 entry, __u32 entry_value) startblock += mydata->fat_sect; - if (disk_read(startblock, getsize, bufptr) < 0) { + if (disk_read(NULL, startblock, getsize, bufptr) < 0) { debug("Error reading FAT blocks\n"); return -1; } @@ -712,7 +712,8 @@ get_set_cluster(fsdata *mydata, __u32 clustnum, loff_t pos, __u8 *buffer, /* partial write at beginning */ if (pos) { wsize = min(bytesperclust - pos, size); - ret = disk_read(startsect, mydata->clust_size, tmpbuf_cluster); + ret = disk_read(NULL, startsect, mydata->clust_size, + tmpbuf_cluster); if (ret != mydata->clust_size) { debug("Error reading data (got %d)\n", ret); return -1; @@ -778,7 +779,8 @@ get_set_cluster(fsdata *mydata, __u32 clustnum, loff_t pos, __u8 *buffer, /* partial write at end */ if (size) { wsize = size; - ret = disk_read(startsect, mydata->clust_size, tmpbuf_cluster); + ret = disk_read(NULL, startsect, mydata->clust_size, + tmpbuf_cluster); if (ret != mydata->clust_size) { debug("Error reading data (got %d)\n", ret); return -1; From patchwork Wed Apr 19 04:03:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770517 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=HwEKxP1Z; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S2x6JTBz23tY for ; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:05 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 33/42] x86: Enable useful options for qemu-86_64 Date: Wed, 19 Apr 2023 16:03:05 +1200 Message-ID: <20230419160308.v2.33.I48a01285a971004cbd1804e7ff67193e5465fea7@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This build can be used to boot standard distro builds, since these are mostly 64-bit these days. Enable some more options, so that all possible EFI UUIDs are decoded, we get a proper printf() in SPL, can search memory for tables, support the full set of standard-boot features, have full logging and can boot from CDROM media. Signed-off-by: Simon Glass --- (no changes since v1) configs/qemu-x86_64_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 371ca9de8429..79ea35918575 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -19,6 +19,7 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_X86_OFFSET_U_BOOT=0xfff00000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y CONFIG_SYS_MONITOR_BASE=0x01110000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y @@ -27,6 +28,9 @@ CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_LOG=y +CONFIG_LOGF_FUNC=y +CONFIG_SPL_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y @@ -46,12 +50,14 @@ CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEM_SEARCH=y CONFIG_CMD_IDE=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_QFW=y CONFIG_CMD_BOOTSTAGE=y @@ -83,5 +89,7 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_USER=y CONFIG_FRAMEBUFFER_VESA_MODE=0x144 CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_FAT_BLK_XLATE=y +# CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_GENERATE_ACPI_TABLE=y # CONFIG_GZIP is not set From patchwork Wed Apr 19 04:03:06 2023 Content-Type: text/plain; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:06 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 34/42] x86: Record the start and end of the tables Date: Wed, 19 Apr 2023 16:03:06 +1200 Message-ID: <20230419160308.v2.34.Ide1869a9d0ecb96f573e5a1a8667450437a3143e@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The ACPI tables are special in that they are passed to EFI as a separate piece, independent of other tables. Also they can be spread over two areas of memory, e.g. with QEMU we end up with tables kept in high memory as well. Add new global_data fields to hold this information and update the bdinfo command to show the table areas. Move the rom_table_end variable into the loop that uses it. Signed-off-by: Simon Glass --- Changes in v2: - Handle the case where the tables are in the bloblist arch/sandbox/include/asm/global_data.h | 4 ++++ arch/x86/include/asm/global_data.h | 4 ++++ arch/x86/lib/bdinfo.c | 4 ++++ arch/x86/lib/tables.c | 16 +++++++++++++++- drivers/misc/qfw.c | 8 ++++++++ 5 files changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index f4ce72d56602..f0ab3ba5c146 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -13,6 +13,10 @@ struct arch_global_data { uint8_t *ram_buf; /* emulated RAM buffer */ void *text_base; /* pointer to base of text region */ + ulong table_start; /* Start address of x86 tables */ + ulong table_end; /* End address of x86 tables */ + ulong table_start_high; /* Start address of high x86 tables */ + ulong table_end_high; /* End address of high x86 tables */ }; #include diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 22d103df4ee8..ea58259ad774 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -123,6 +123,10 @@ struct arch_global_data { #endif void *itss_priv; /* Private ITSS data pointer */ ulong coreboot_table; /* Address of coreboot table */ + ulong table_start; /* Start address of x86 tables */ + ulong table_end; /* End address of x86 tables */ + ulong table_start_high; /* Start address of high x86 tables */ + ulong table_end_high; /* End address of high x86 tables */ }; #endif diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c index 0970efa4726f..9504e7fc293e 100644 --- a/arch/x86/lib/bdinfo.c +++ b/arch/x86/lib/bdinfo.c @@ -23,6 +23,10 @@ void arch_print_bdinfo(void) bdinfo_print_str(" name", cpu_vendor_name(gd->arch.x86_vendor)); bdinfo_print_num_l("model", gd->arch.x86_model); bdinfo_print_num_l("phys_addr", cpu_phys_address_size()); + bdinfo_print_num_l("table start", gd->arch.table_start); + bdinfo_print_num_l("table end", gd->arch.table_end); + bdinfo_print_num_l(" high start", gd->arch.table_start_high); + bdinfo_print_num_l(" high end", gd->arch.table_end_high); if (IS_ENABLED(CONFIG_EFI_STUB)) efi_show_bdinfo(); diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index ea834a5035f5..5815f45edd01 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -54,6 +54,10 @@ static struct table_info table_list[] = { #ifdef CONFIG_GENERATE_MP_TABLE { "mp", write_mp_table, }, #endif + /* + * tables which can go in the bloblist must be last in this list, so + * that the calculation of gd->table_end works properly + */ #ifdef CONFIG_GENERATE_ACPI_TABLE { "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, 0x10000, 0x1000}, #endif @@ -79,23 +83,28 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad) int write_tables(void) { u32 rom_table_start; - u32 rom_table_end; u32 high_table, table_size; struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1]; int i; rom_table_start = ROM_TABLE_ADDR; + gd->arch.table_start = rom_table_start; debug("Writing tables to %x:\n", rom_table_start); for (i = 0; i < ARRAY_SIZE(table_list); i++) { const struct table_info *table = &table_list[i]; int size = table->size ? : CONFIG_ROM_TABLE_SIZE; + u32 rom_table_end; if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) && table->tag) { + if (!gd->arch.table_end) + gd->arch.table_end = rom_table_start; rom_table_start = (ulong)bloblist_add(table->tag, size, table->align); if (!rom_table_start) return log_msg_ret("bloblist", -ENOBUFS); + if (!gd->arch.table_start_high) + gd->arch.table_start_high = rom_table_start; } rom_table_end = table->write(rom_table_start); if (!rom_table_end) { @@ -132,6 +141,11 @@ int write_tables(void) rom_table_start = rom_table_end; } + if (gd->arch.table_start_high) + gd->arch.table_end_high = rom_table_start; + else + gd->arch.table_end = rom_table_start; + if (IS_ENABLED(CONFIG_SEABIOS)) { /* make sure the last item is zero */ cfg_tables[i].size = 0; diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index 0a93feeb4b2e..c0da4bd7359e 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -65,6 +65,11 @@ static int bios_linker_allocate(struct udevice *dev, printf("error: allocating resource\n"); return -ENOMEM; } + if (aligned_addr < gd->arch.table_start_high) + gd->arch.table_start_high = aligned_addr; + if (aligned_addr + size > gd->arch.table_end_high) + gd->arch.table_end_high = aligned_addr + size; + } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) { aligned_addr = ALIGN(*addr, align); } else { @@ -189,6 +194,9 @@ ulong write_acpi_tables(ulong addr) return addr; } + gd->arch.table_start_high = (ulong)table_loader; + gd->arch.table_end_high = (ulong)table_loader; + qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size, table_loader); for (i = 0; i < (size / sizeof(*entry)); i++) { From patchwork Wed Apr 19 04:03:07 2023 Content-Type: text/plain; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:07 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 35/42] x86: Show the number of physical address bits Date: Wed, 19 Apr 2023 16:03:07 +1200 Message-ID: <20230419040314.160352-4-sjg@chromium.org> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add this information to global_data and show it with the 'bdinfo' command. For now we use CONFIG_CPU_ADDR_BITS to control the number of bits, but this could change if needed. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch to show the number of physical address bits arch/x86/cpu/i386/cpu.c | 2 ++ arch/x86/include/asm/global_data.h | 1 + arch/x86/lib/bdinfo.c | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 91cd5d7c9e40..5c17d279092e 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -468,6 +468,7 @@ int x86_cpu_init_f(void) if (ll_boot_init()) setup_cpu_features(); setup_identity(); + gd->arch.phys_bits = cpu_phys_address_size(); setup_mtrr(); setup_pci_ram_top(); @@ -483,6 +484,7 @@ int x86_cpu_reinit_f(void) long addr; setup_identity(); + gd->arch.phys_bits = cpu_phys_address_size(); setup_pci_ram_top(); addr = locate_coreboot_table(); if (addr >= 0) { diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index ea58259ad774..5b802f79d502 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -127,6 +127,7 @@ struct arch_global_data { ulong table_end; /* End address of x86 tables */ ulong table_start_high; /* Start address of high x86 tables */ ulong table_end_high; /* End address of high x86 tables */ + uint phys_bits; /* Number of physical address bits */ }; #endif diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c index 9504e7fc293e..c5fda22679ad 100644 --- a/arch/x86/lib/bdinfo.c +++ b/arch/x86/lib/bdinfo.c @@ -27,6 +27,7 @@ void arch_print_bdinfo(void) bdinfo_print_num_l("table end", gd->arch.table_end); bdinfo_print_num_l(" high start", gd->arch.table_start_high); bdinfo_print_num_l(" high end", gd->arch.table_end_high); + bdinfo_print_num_l("phys bits", gd->arch.phys_bits); if (IS_ENABLED(CONFIG_EFI_STUB)) efi_show_bdinfo(); From patchwork Wed Apr 19 04:03:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770531 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:08 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 36/42] x86: Convert some debug statements to use logging Date: Wed, 19 Apr 2023 16:03:08 +1200 Message-ID: <20230419040314.160352-5-sjg@chromium.org> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Move from using debug() to log_debug() so that we don't have to use the __func__ parameter and can access other logging features. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch to convert some debug statements to use logging arch/x86/cpu/intel_common/mrc.c | 10 +++++----- arch/x86/cpu/ivybridge/sdram.c | 4 +++- arch/x86/lib/mrccache.c | 6 ++++-- arch/x86/lib/spl.c | 22 ++++++++++++++-------- drivers/gpio/intel_ich6_gpio.c | 5 +++-- drivers/pch/pch9.c | 6 ++++-- 6 files changed, 33 insertions(+), 20 deletions(-) diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index 69405d740b47..2819bae02e3c 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -3,6 +3,8 @@ * Copyright (c) 2016 Google, Inc */ +#define LOG_CATEGORY UCLASS_RAM + #include #include #include @@ -144,12 +146,10 @@ int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap) ret = gpio_request_list_by_name(dev, "board-id-gpios", desc, ARRAY_SIZE(desc), GPIOD_IS_IN); - if (ret < 0) { - debug("%s: gpio ret=%d\n", __func__, ret); - return ret; - } + if (ret < 0) + return log_msg_ret("gp", ret); spd_index = dm_gpio_get_values_as_int(desc, ret); - debug("spd index %d\n", spd_index); + log_debug("spd index %d\n", spd_index); node = fdt_first_subnode(blob, dev_of_offset(dev)); if (node < 0) diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 1a0ec433e654..0718aefbb1fe 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -9,6 +9,8 @@ * Copyright (C) 2011 Google Inc. */ +#define LOG_CATEGORY UCLASS_RAM + #include #include #include @@ -213,7 +215,7 @@ static int copy_spd(struct udevice *dev, struct pei_data *peid) ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data); if (ret) { - debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret); + log_debug("Could not locate SPD (err=%d)\n", ret); return ret; } diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 2f6f6880003e..6494b8d26341 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -6,6 +6,8 @@ * Copyright (C) 2015 Bin Meng */ +#define LOG_CATEGORY UCLASS_RAM + #include #include #include @@ -197,8 +199,8 @@ static void mrccache_setup(struct mrc_output *mrc, void *data) cache->signature = MRC_DATA_SIGNATURE; cache->data_size = mrc->len; checksum = compute_ip_checksum(mrc->buf, cache->data_size); - debug("Saving %d bytes for MRC output data, checksum %04x\n", - cache->data_size, checksum); + log_debug("Saving %d bytes for MRC output data, checksum %04x\n", + cache->data_size, checksum); cache->checksum = checksum; cache->reserved = 0; memcpy(cache->data, mrc->buf, cache->data_size); diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 6d2291ba65f4..683454dacac4 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -3,6 +3,8 @@ * Copyright (c) 2016 Google, Inc */ +#define LOG_CATEGORY LOGC_BOOT + #include #include #include @@ -76,25 +78,25 @@ static int x86_spl_init(void) #endif int ret; - debug("%s starting\n", __func__); + log_debug("x86 spl starting\n"); if (IS_ENABLED(TPL)) ret = x86_cpu_reinit_f(); else ret = x86_cpu_init_f(); ret = spl_init(); if (ret) { - debug("%s: spl_init() failed\n", __func__); + log_debug("spl_init() failed (err=%d)\n", ret); return ret; } ret = arch_cpu_init(); if (ret) { - debug("%s: arch_cpu_init() failed\n", __func__); + log_debug("arch_cpu_init() failed (err=%d)\n", ret); return ret; } #ifndef CONFIG_TPL ret = fsp_setup_pinctrl(NULL, NULL); if (ret) { - debug("%s: fsp_setup_pinctrl() failed\n", __func__); + log_debug("fsp_setup_pinctrl() failed (err=%d)\n", ret); return ret; } #endif @@ -103,23 +105,25 @@ static int x86_spl_init(void) #if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU) ret = print_cpuinfo(); if (ret) { - debug("%s: print_cpuinfo() failed\n", __func__); + log_debug("print_cpuinfo() failed (err=%d)\n", ret); return ret; } #endif ret = dram_init(); if (ret) { - debug("%s: dram_init() failed\n", __func__); + log_debug("dram_init() failed (err=%d)\n", ret); return ret; } + log_debug("mrc\n"); if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { ret = mrccache_spl_save(); if (ret) - debug("%s: Failed to write to mrccache (err=%d)\n", - __func__, ret); + log_debug("Failed to write to mrccache (err=%d)\n", + ret); } #ifndef CONFIG_SYS_COREBOOT + log_debug("bss\n"); debug("BSS clear from %lx to %lx len %lx\n", (ulong)&__bss_start, (ulong)&__bss_end, (ulong)&__bss_end - (ulong)&__bss_start); memset(&__bss_start, '\0', (ulong)&__bss_end - (ulong)&__bss_start); @@ -140,6 +144,7 @@ static int x86_spl_init(void) gd->new_gd = (struct global_data *)ptr; memcpy(gd->new_gd, gd, sizeof(*gd)); + log_debug("logging\n"); /* * Make sure logging is disabled when we switch, since the log system * list head will move @@ -179,6 +184,7 @@ static int x86_spl_init(void) debug("Failed to set CPU frequency (err=%d)\n", ret); # endif #endif + log_debug("done\n"); return 0; } diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 63a07b9592a0..2ed0d0bea9a5 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -26,6 +26,8 @@ * reserved or subject to arcane restrictions. */ +#define LOG_CATEGORY UCLASS_GPIO + #include #include #include @@ -155,8 +157,7 @@ static int ich6_gpio_request(struct udevice *dev, unsigned offset, */ tmplong = inl(bank->use_sel); if (!(tmplong & (1UL << offset))) { - debug("%s: gpio %d is reserved for internal use\n", __func__, - offset); + log_debug("gpio %d is reserved for internal use\n", offset); return -EPERM; } diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c index 3bd011518b3a..3137eb2c28f5 100644 --- a/drivers/pch/pch9.c +++ b/drivers/pch/pch9.c @@ -3,6 +3,8 @@ * Copyright (C) 2014 Google, Inc */ +#define LOG_CATEGORY UCLASS_PCH + #include #include #include @@ -38,7 +40,7 @@ static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep) */ dm_pci_read_config32(dev, GPIO_BASE, &base); if (base == 0x00000000 || base == 0xffffffff) { - debug("%s: unexpected BASE value\n", __func__); + log_debug("unexpected BASE value\n"); return -ENODEV; } @@ -59,7 +61,7 @@ static int pch9_get_io_base(struct udevice *dev, u32 *iobasep) dm_pci_read_config32(dev, IO_BASE, &base); if (base == 0x00000000 || base == 0xffffffff) { - debug("%s: unexpected BASE value\n", __func__); + log_debug("unexpected BASE value\n"); return -ENODEV; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:09 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 37/42] x86: link: Support Micron memory Date: Wed, 19 Apr 2023 16:03:09 +1200 Message-ID: <20230419040314.160352-6-sjg@chromium.org> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add the required tag so that micron memory can be set up correctly. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch to support Micron memory arch/x86/dts/chromebook_link.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 36956f40bd70..c904b7d0b69d 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -314,6 +314,7 @@ 00 00 00 00 00 00 00 00]; }; micron_4Gb_1600_1.35v_x16 { + bootph-all; reg = <2>; data = [92 11 0b 03 04 19 02 02 03 11 01 08 0a 00 fe 00 From patchwork Wed Apr 19 04:03:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770532 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=gAL13XPE; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S6g318Cz1yZk for ; Wed, 19 Apr 2023 14:12:11 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E5AFF8627B; Wed, 19 Apr 2023 06:05:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="gAL13XPE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E5F2986238; Wed, 19 Apr 2023 06:04:27 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x12a.google.com (mail-il1-x12a.google.com [IPv6:2607:f8b0:4864:20::12a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 169CB86239 for ; Wed, 19 Apr 2023 06:04:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x12a.google.com with SMTP id e9e14a558f8ab-32ad8ca1e69so23874865ab.3 for ; Tue, 18 Apr 2023 21:04:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877051; x=1684469051; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lg+n//RMDKNfbo4W1e+kZ+yyhi9MhlRXdsqiuyW0u0E=; b=gAL13XPEVRm8jjnA2dcTnuitdwBwFXSUK/1Xfiz5KaiwZ/wi9mZtrU0ZjQFoLBB5re zHF/WKVw3M5QhMNPLhxy6CRZm3rAJvZNbjH2Hdq4EB77QSjPEE84v11LR0Jtph1Cpu6K YiRYK32Bal2cbCzkiZ8iEdtsv2MSsSsjpxg9Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877051; x=1684469051; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lg+n//RMDKNfbo4W1e+kZ+yyhi9MhlRXdsqiuyW0u0E=; b=bDPGiaSUNYVUpTxrAjb5VdoEOJ1vK9HY9DBREYH/3kBmBPmeAgpUKLNmx2ysw+Y3ph yMP/2Syuk/JDCrt08hzGdIi03nx1Mc/DjAChn0YgBw/58IC0K+2m88hUHZjZnkQo0g4q gymzi/FFXJ5+OONbDEO9TccW3Ly7dfIkSPvdyUD8pkgDBLav99qn/TPm7ZOZhsNrZ0Pb 9vEt+xR4GiWbjyJaH0RYwStcjxJ9oBTrpm9GyCojm4LExS7XiC9CPLyNzny6Usvmxwp2 kMucA20gq2VkhTjk3dIO5Jy04KURaiUnEvPdZ81W4dqX8Y012mYqyLPIWVo1ayRMWvct OMDQ== X-Gm-Message-State: AAQBX9dK0wbpRmgVvElaQ0ovQYjyetrMgBz/KmOwcGzyzVSPMjokqxSj 2gZTM4OG8EfCZmTQ+w4C239DL4DZMiDP518hh5M= X-Google-Smtp-Source: AKy350a63wVkDFcrdNhE+IF2rTPxc8SLs35GrYNrmTgZTKDnsdbO1n9Jg3SG/w1+6NUGjlr0pwkNeQ== X-Received: by 2002:a92:d803:0:b0:326:413e:b0ff with SMTP id y3-20020a92d803000000b00326413eb0ffmr14843934ilm.10.1681877050961; Tue, 18 Apr 2023 21:04:10 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:10 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 38/42] x86: Make sure that the LPC is active before SDRAM init Date: Wed, 19 Apr 2023 16:03:10 +1200 Message-ID: <20230419040314.160352-7-sjg@chromium.org> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some boards need to access GPIOs to determine which SDRAM is fitted to the board, for example chromebook_link. Probe this device (if it exists) to make sure that this works as expected. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch to make sure that the LPC is active before SDRAM init arch/x86/lib/spl.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 683454dacac4..08846686858e 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -65,6 +65,8 @@ static int set_max_freq(void) static int x86_spl_init(void) { + struct udevice *dev; + #ifndef CONFIG_TPL /* * TODO(sjg@chromium.org): We use this area of RAM for the stack @@ -109,6 +111,13 @@ static int x86_spl_init(void) return ret; } #endif + /* probe the LPC so we get the GPIO_BASE set up correctly */ + ret = uclass_first_device_err(UCLASS_LPC, &dev); + if (ret && ret != -ENODEV) { + log_debug("lpc probe failed\n"); + return ret; + } + ret = dram_init(); if (ret) { log_debug("dram_init() failed (err=%d)\n", ret); From patchwork Wed Apr 19 04:03:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770530 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:11 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 39/42] log: Support outputing function names in SPL Date: Wed, 19 Apr 2023 16:03:11 +1200 Message-ID: <20230419040314.160352-8-sjg@chromium.org> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The output is garbled when tiny printf() is used. Correct this by adding a special case. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch to support outputing function names in SPL common/log_console.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/common/log_console.c b/common/log_console.c index f1dcc04b97c9..bb091ce21a4a 100644 --- a/common/log_console.c +++ b/common/log_console.c @@ -37,8 +37,14 @@ static int log_console_emit(struct log_device *ldev, struct log_rec *rec) printf("%s:", rec->file); if (fmt & BIT(LOGF_LINE)) printf("%d-", rec->line); - if (fmt & BIT(LOGF_FUNC)) - printf("%*s()", CONFIG_LOGF_FUNC_PAD, rec->func); + if (fmt & BIT(LOGF_FUNC)) { + if (CONFIG_IS_ENABLED(USE_TINY_PRINTF)) { + printf("%s()", rec->func); + } else { + printf("%*s()", CONFIG_LOGF_FUNC_PAD, + rec->func); + } + } } if (fmt & BIT(LOGF_MSG)) printf("%s%s", add_space ? " " : "", rec->msg); From patchwork Wed Apr 19 04:03:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770534 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=VC3hXC+O; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S786dXxz1yZk for ; Wed, 19 Apr 2023 14:12:36 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 86EFF86281; Wed, 19 Apr 2023 06:05:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="VC3hXC+O"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 26F68861AB; Wed, 19 Apr 2023 06:04:28 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x130.google.com (mail-il1-x130.google.com [IPv6:2607:f8b0:4864:20::130]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1FC1B86240 for ; Wed, 19 Apr 2023 06:04:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x130.google.com with SMTP id e9e14a558f8ab-32ab4464280so5809335ab.1 for ; Tue, 18 Apr 2023 21:04:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877053; x=1684469053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vGsBDGuELEz9cgAhkC0hqSsfO1jAQGSXlEdoe/f5gbk=; b=VC3hXC+OiPlFk+Gvz5AYXmEeot61RhNBbYppkMxlOIuWf5xzJL/pIWS/fAxknePXpo GtWuw9mt3+jhlLREmNZk5lUoKF+aLB1JjpnIlk5u5HctTzUzJhCMz7fmvE+OAZQY5WHS y4s397w5dGvOEGWwqesZ+xyeMh4CInjMCoF0g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877053; x=1684469053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vGsBDGuELEz9cgAhkC0hqSsfO1jAQGSXlEdoe/f5gbk=; b=YCjUIs9KkNmZgK5KWsGv3bV07iQCWRGCUpdtY8GFECPSa0l3T9gPE93Z883mjCIF8a QrbT2m3kjOi+ODEslI4khU0EhlRL0XnYqY6n1R1MIzHSTX794X/7/bg2a29VL1c1ZuVr TYx6IbfSiJ10nMXFEcDGswqQqYQn6iAouks3U9eG6coPGGMVUq9XhO/4oZoFar0gteYR BuWIO06xLdeGz30c2GToO594Fj+9rfTtTJB8EZ5Vy+xlXpt1qGZBxrR1KLp+P8zNV32E oIxJMqVjoFhPiSo2D3AeT5jjSMDAkW9RvcKhDEs0VTkl+AQdxI+NRsqwqqo/iL0dhRNH Ar4A== X-Gm-Message-State: AAQBX9eEXMcgghA3urDRoPiKgCObbevJxTpuj+2E3T1H/6Q21UrX+GPS cmv9YT41llEOMFcj8ONBYSkkhJIkU4+sAIprhxI= X-Google-Smtp-Source: AKy350YTOaLTILfXlunsNu6RacQ+jcCgpqEpBhbpPAPCCyLninG26LNvy1jIVdt0swcI5JoXeByqJw== X-Received: by 2002:a92:6807:0:b0:315:3d99:bbd3 with SMTP id d7-20020a926807000000b003153d99bbd3mr13662734ilc.8.1681877052769; Tue, 18 Apr 2023 21:04:12 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:12 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 40/42] sandbox: Correct header order in board file Date: Wed, 19 Apr 2023 16:03:12 +1200 Message-ID: <20230419160308.v2.40.If98bd1d7175ba37c571b3da11e278462397e2421@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Fix the header order in this file. Signed-off-by: Simon Glass --- (no changes since v1) board/sandbox/sandbox.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 2e44bdf0df3e..e72d8164ebf6 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -11,16 +11,16 @@ #include #include #include +#include #include #include +#include #include #include #include #include #include -#include - -#include +#include /* * Pointer to initial global data area From patchwork Wed Apr 19 04:03:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770525 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=jh1YlC6U; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S4x1br6z1yZk for ; Wed, 19 Apr 2023 14:10:41 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C6EA68626F; Wed, 19 Apr 2023 06:05:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="jh1YlC6U"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 30B878623C; Wed, 19 Apr 2023 06:04:19 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x12c.google.com (mail-il1-x12c.google.com [IPv6:2607:f8b0:4864:20::12c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2952A86220 for ; Wed, 19 Apr 2023 06:04:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x12c.google.com with SMTP id e9e14a558f8ab-32a7770f7d1so41689785ab.1 for ; Tue, 18 Apr 2023 21:04:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1681877053; x=1684469053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O6sC5n7toFmh0qqFroOQpY0u8ii2dVYkbSOlJ1qmnY4=; b=jh1YlC6UlwaknQQ3Hd2WqD9gl2gVUXKgA6s1uTXuLGSeA0vKHMEFxIHbJBamjAPWS3 3+n+cGtdZHp3xwkEgoSCDG/LUMYFI0iXRNCOKnQyeODGzmrdfzK8S+hXC2nWn36K/XTl yOEiXLIoyrF5oZf6hQE+r4YrKfFSDTiqu9XC0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681877053; x=1684469053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O6sC5n7toFmh0qqFroOQpY0u8ii2dVYkbSOlJ1qmnY4=; b=by2ad9UQ+1re9+qEvFcUmbq942o0AHjMK1l59B88OaA6rAcgfzaruDATXg1AjdLjvn wM1S5uvnPogg7NU43iFWBWUvTGeWaDutn9LeXvZFP7NolsYwjGhMYfe2HgcmW3Y9Jr89 XUMwdyBjEzXkbNv3rt+syJA+ejBux6Kp5t3FNBoS1seNj/F5IeGBXG6YMuMuKx1na+LE vTCB4/sK/TiG8ObQ7K4w85yXZWOHrHTKySQLixnXkElYmzw76oFnlFW4fj92PuqeOPEZ mUDFeaQYjq5sbHrz6co47JeyyF4UZwhzWFchu5JuKscSGsRSg5KfEjcfnrqIS6B783PI vmtg== X-Gm-Message-State: AAQBX9faAf9bRD+G4AlH1eYlFFn4U6UhKuTmNi94lFLHV+gr7ZwCw6Yw 0T9XG8OK4jr1HM3fT7t+RV+MqZ+4WC55/xV28UY= X-Google-Smtp-Source: AKy350abcOUHekXqTy0IGc49uxIGN1iVtVbCEgNLpb1Xz9mGRPa6eOvGd8+heezURKS0ktyn+/gUVQ== X-Received: by 2002:a05:6602:2c94:b0:760:f293:12d8 with SMTP id i20-20020a0566022c9400b00760f29312d8mr1110664iow.7.1681877053680; Tue, 18 Apr 2023 21:04:13 -0700 (PDT) Received: from sjg1.lan (c-73-14-173-85.hsd1.co.comcast.net. [73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:13 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 41/42] sandbox: Install ACPI tables on startup Date: Wed, 19 Apr 2023 16:03:13 +1200 Message-ID: <20230419160308.v2.41.Iac7708c2705505ade345890cbd4cd83d3bd1c1bf@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean With x86 we set up the ACPI tables on startup so they can be examined. Do the same with sandbox, so it is consistent. Signed-off-by: Simon Glass --- (no changes since v1) board/sandbox/sandbox.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index e72d8164ebf6..2083eaa2dc55 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -15,7 +15,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -154,6 +156,8 @@ int extension_board_scan(struct list_head *extension_list) int board_late_init(void) { struct udevice *dev; + ulong addr, end; + void *ptr; int ret; ret = uclass_first_device_err(UCLASS_CROS_EC, &dev); @@ -166,6 +170,18 @@ int board_late_init(void) panic("Cannot init cros-ec device"); return -1; } + + if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) { + /* Reserve 64K for ACPI tables, aligned to a 4K boundary */ + ptr = memalign(SZ_4K, SZ_64K); + addr = map_to_sysmem(ptr); + + /* Generate ACPI tables */ + end = write_acpi_tables(addr); + gd->arch.table_start = addr; + gd->arch.table_end = addr; + } + return 0; } #endif From patchwork Wed Apr 19 04:03:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1770533 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=Re8ANXBj; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q1S6w3f4gz1yZk for ; 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[73.14.173.85]) by smtp.gmail.com with ESMTPSA id i4-20020a05663815c400b0040f91082a4fsm3261982jat.75.2023.04.18.21.04.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 21:04:14 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Heinrich Schuchardt , Bin Meng , Simon Glass Subject: [PATCH v2 42/42] efi: Use the installed ACPI tables Date: Wed, 19 Apr 2023 16:03:14 +1200 Message-ID: <20230419160308.v2.42.I86db03df16c50b2b03532f99064a26c14704056f@changeid> X-Mailer: git-send-email 2.40.0.634.g4ca3ef3211-goog In-Reply-To: <20230419040314.160352-1-sjg@chromium.org> References: <20230419040314.160352-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean U-Boot sets up the ACPI tables during startup. Rather than creating a new set, install the existing ones. Create a memory-map record to cover the tables. Signed-off-by: Simon Glass --- Changes in v2: - Drop patch to set high bits of the mtrr base register, for now lib/efi_loader/efi_acpi.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c index 2ddc3502b5df..f755af76f866 100644 --- a/lib/efi_loader/efi_acpi.c +++ b/lib/efi_loader/efi_acpi.c @@ -10,6 +10,9 @@ #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID; @@ -20,26 +23,28 @@ static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID; */ efi_status_t efi_acpi_register(void) { - /* Map within the low 32 bits, to allow for 32bit ACPI tables */ - u64 acpi = U32_MAX; + ulong addr, start, end; efi_status_t ret; - ulong addr; - /* Reserve 64kiB page for ACPI */ - ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, - EFI_ACPI_RECLAIM_MEMORY, 16, &acpi); + /* Mark space used for tables */ + start = ALIGN_DOWN(gd->arch.table_start, EFI_PAGE_MASK); + end = ALIGN(gd->arch.table_end, EFI_PAGE_MASK); + ret = efi_add_memory_map(start, end - start, EFI_ACPI_RECLAIM_MEMORY); if (ret != EFI_SUCCESS) return ret; + if (gd->arch.table_start_high) { + start = ALIGN_DOWN(gd->arch.table_start_high, EFI_PAGE_MASK); + end = ALIGN(gd->arch.table_end_high, EFI_PAGE_MASK); + ret = efi_add_memory_map(start, end - start, + EFI_ACPI_RECLAIM_MEMORY); + if (ret != EFI_SUCCESS) + return ret; + } - /* - * Generate ACPI tables - we know that efi_allocate_pages() returns - * a 4k-aligned address, so it is safe to assume that - * write_acpi_tables() will write the table at that address. - */ - addr = map_to_sysmem((void *)(ulong)acpi); - write_acpi_tables(addr); + addr = gd_acpi_start(); + printf("EFI using ACPI tables at %lx\n", addr); /* And expose them to our EFI payload */ return efi_install_configuration_table(&acpi_guid, - (void *)(uintptr_t)acpi); + (void *)(ulong)addr); }