From patchwork Mon Apr 10 07:27:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Chen X-Patchwork-Id: 1767067 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Pw0sT3W8Pz1yZC for ; Mon, 10 Apr 2023 17:26:53 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A093384D0F; Mon, 10 Apr 2023 09:26:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 78F0084D0F; Mon, 10 Apr 2023 09:26:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00,RDNS_DYNAMIC, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 64CAD84D02 for ; Mon, 10 Apr 2023 09:26:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rick@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 33A7QY21062050; Mon, 10 Apr 2023 15:26:34 +0800 (+08) (envelope-from rick@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.158) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 10 Apr 2023 15:26:33 +0800 From: Rick Chen To: CC: , , , , Subject: [PATCH] riscv: Support riscv64 image type Date: Mon, 10 Apr 2023 15:27:18 +0800 Message-ID: <20230410072718.3484-1-rick@andestech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.0.15.158] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 33A7QY21062050 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Allow U-Boot to load 32 or 64 bits RISC-V Kernel Image distinguishly. It helps to avoid someone maybe make a mistake to run 32-bit U-Boot to load 64-bit kernel. Signed-off-by: Rick Chen Reviewed-by: Simon Glass --- The patchset is based on Simon's patch: riscv: Add a 64-bit image type --- --- arch/riscv/include/asm/u-boot.h | 4 ++++ cmd/booti.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/u-boot.h b/arch/riscv/include/asm/u-boot.h index d5e1d5f323..e3b4a0357c 100644 --- a/arch/riscv/include/asm/u-boot.h +++ b/arch/riscv/include/asm/u-boot.h @@ -23,6 +23,10 @@ #include /* For image.h:image_check_target_arch() */ +#ifdef CONFIG_ARCH_RV64I +#define IH_ARCH_DEFAULT IH_ARCH_RISCV64 +#else #define IH_ARCH_DEFAULT IH_ARCH_RISCV +#endif #endif /* _U_BOOT_H_ */ diff --git a/cmd/booti.c b/cmd/booti.c index 6ac39193db..dc0b0ae41c 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -119,7 +119,7 @@ int do_booti(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) images.os.os = IH_OS_LINUX; #ifdef CONFIG_RISCV_SMODE - images.os.arch = IH_ARCH_RISCV; + images.os.arch = IH_ARCH_DEFAULT; #elif CONFIG_ARM64 images.os.arch = IH_ARCH_ARM64; #endif