From patchwork Wed Mar 21 04:40:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajkumar Rampelli X-Patchwork-Id: 888540 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405cZ53dvjz9s12 for ; Wed, 21 Mar 2018 15:41:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751907AbeCUEky (ORCPT ); Wed, 21 Mar 2018 00:40:54 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12169 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751531AbeCUEkv (ORCPT ); Wed, 21 Mar 2018 00:40:51 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 20 Mar 2018 21:40:45 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 20 Mar 2018 21:40:46 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 20 Mar 2018 21:40:46 -0700 Received: from UKMAIL102.nvidia.com (10.26.138.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:40:49 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by UKMAIL102.nvidia.com (10.26.138.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:40:45 +0000 Received: from rrajk-ubuntu.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 21 Mar 2018 04:40:36 +0000 From: Rajkumar Rampelli To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 1/9] pwm: core: Add support for PWM HW driver with pwm capture only Date: Wed, 21 Mar 2018 10:10:36 +0530 Message-ID: <1521607244-29734-2-git-send-email-rrajk@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> References: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add support for pwm HW driver which has only capture functionality. This helps to implement the PWM based Tachometer driver which reads the PWM output signals from electronic fans. PWM Tachometer captures the period and duty cycle of the PWM signal Add conditional checks for callabacks enable(), disable(), config() to check if they are supported by the client driver or not. Skip these callbacks if they are not supported. Signed-off-by: Rajkumar Rampelli --- V2: Added if conditional checks for pwm callbacks since drivers may implements only pwm capture functionality. drivers/pwm/core.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 1581f6a..f70fe68 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -246,6 +246,10 @@ static bool pwm_ops_check(const struct pwm_ops *ops) if (ops->apply) return true; + /* driver supports capture operation */ + if (ops->capture) + return true; + return false; } @@ -495,7 +499,8 @@ int pwm_apply_state(struct pwm_device *pwm, struct pwm_state *state) * ->apply(). */ if (pwm->state.enabled) { - pwm->chip->ops->disable(pwm->chip, pwm); + if (pwm->chip->ops->disable) + pwm->chip->ops->disable(pwm->chip, pwm); pwm->state.enabled = false; } @@ -509,22 +514,26 @@ int pwm_apply_state(struct pwm_device *pwm, struct pwm_state *state) if (state->period != pwm->state.period || state->duty_cycle != pwm->state.duty_cycle) { - err = pwm->chip->ops->config(pwm->chip, pwm, + if (pwm->chip->ops->config) { + err = pwm->chip->ops->config(pwm->chip, pwm, state->duty_cycle, state->period); - if (err) - return err; + if (err) + return err; + } pwm->state.duty_cycle = state->duty_cycle; pwm->state.period = state->period; } if (state->enabled != pwm->state.enabled) { - if (state->enabled) { + if (state->enabled && pwm->chip->ops->enable) { err = pwm->chip->ops->enable(pwm->chip, pwm); if (err) return err; - } else { + } + + if (!state->enabled && pwm->chip->ops->disable) { pwm->chip->ops->disable(pwm->chip, pwm); } From patchwork Wed Mar 21 04:40:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajkumar Rampelli X-Patchwork-Id: 888543 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405cZC6zWZz9ryk for ; Wed, 21 Mar 2018 15:41:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751969AbeCUElH (ORCPT ); Wed, 21 Mar 2018 00:41:07 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6944 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751727AbeCUElD (ORCPT ); Wed, 21 Mar 2018 00:41:03 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 20 Mar 2018 21:41:11 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 20 Mar 2018 21:41:02 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 20 Mar 2018 21:41:02 -0700 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:01 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:40:57 +0000 Received: from rrajk-ubuntu.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 21 Mar 2018 04:40:48 +0000 From: Rajkumar Rampelli To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 2/9] arm64: tegra: Add PWM controller on Tegra186 soc Date: Wed, 21 Mar 2018 10:10:37 +0530 Message-ID: <1521607244-29734-3-git-send-email-rrajk@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> References: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The NVIDIA Tegra186 SoC has a PWM controller which is used in FAN control use case. Signed-off-by: Rajkumar Rampelli --- V2: no changes in this patch arch/arm64/boot/dts/nvidia/tegra186.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b762227..731cd01 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1031,4 +1031,15 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&gic>; }; + + pwm@c340000 { + compatible = "nvidia,tegra186-pwm"; + reg = <0x0 0xc340000 0x0 0x10000>; + clocks = <&bpmp TEGRA186_CLK_PWM4>; + clock-names = "pwm"; + #pwm-cells = <2>; + resets = <&bpmp TEGRA186_RESET_PWM4>; + reset-names = "pwm"; + status = "disabled"; + }; }; From patchwork Wed Mar 21 04:40:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajkumar Rampelli X-Patchwork-Id: 888544 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405cZT0sv8z9ryk for ; Wed, 21 Mar 2018 15:41:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752088AbeCUElT (ORCPT ); Wed, 21 Mar 2018 00:41:19 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12222 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751794AbeCUElO (ORCPT ); Wed, 21 Mar 2018 00:41:14 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 20 Mar 2018 21:41:09 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 20 Mar 2018 21:41:10 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 20 Mar 2018 21:41:10 -0700 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:13 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:09 +0000 Received: from rrajk-ubuntu.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 21 Mar 2018 04:41:00 +0000 From: Rajkumar Rampelli To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 3/9] dt-bindings: Tegra186 tachometer device tree bindings Date: Wed, 21 Mar 2018 10:10:38 +0530 Message-ID: <1521607244-29734-4-git-send-email-rrajk@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> References: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Supply Device tree binding documentation for the NVIDIA Tegra186 SoC's Tachometer Controller Signed-off-by: Rajkumar Rampelli --- V2: Renamed compatible string to "nvidia,tegra186-pwm-tachometer" Renamed dt property values of clock-names and reset-names to "tachometer" from "tach" .../bindings/pwm/pwm-tegra-tachometer.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-tegra-tachometer.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-tegra-tachometer.txt b/Documentation/devicetree/bindings/pwm/pwm-tegra-tachometer.txt new file mode 100644 index 0000000..4a7ead4 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-tegra-tachometer.txt @@ -0,0 +1,31 @@ +Bindings for a PWM based Tachometer driver + +Required properties: +- compatible: Must be "nvidia,tegra186-pwm-tachometer" +- reg: physical base addresses of the controller and length of + memory mapped region. +- #pwm-cells: should be 2. See pwm.txt in this directory for a + description of the cells format. +- clocks: phandle list of tachometer clocks +- clock-names: should be "tachometer". See clock-bindings.txt in documentations +- resets: phandle to the reset controller for the Tachometer IP +- reset-names: should be "tachometer". See reset.txt in documentations +- nvidia,pulse-per-rev: Integer, pulses per revolution of a Fan. This value + obtained from Fan specification document. +- nvidia,capture-window-len: Integer, window of the Fan Tach monitor, it indicates + that how many period of the input fan tach signal will the FAN TACH logic + monitor. Valid values are 1, 2, 4 and 8 only. + +Example: + tegra_tachometer: tachometer@39c0000 { + compatible = "nvidia,tegra186-pwm-tachometer"; + reg = <0x0 0x039c0000 0x0 0x10>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA186_CLK_TACH>; + clock-names = "tachometer"; + resets = <&tegra_car TEGRA186_RESET_TACH>; + reset-names = "tachometer"; + nvidia,pulse-per-rev = <2>; + nvidia,capture-window-len = <2>; + status = "disabled"; + }; From patchwork Wed Mar 21 04:40:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajkumar Rampelli X-Patchwork-Id: 888546 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405cZj1vDyz9s12 for ; Wed, 21 Mar 2018 15:41:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752087AbeCUElb (ORCPT ); Wed, 21 Mar 2018 00:41:31 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:7465 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751963AbeCUEl1 (ORCPT ); Wed, 21 Mar 2018 00:41:27 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 20 Mar 2018 21:40:11 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 20 Mar 2018 21:41:26 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 20 Mar 2018 21:41:26 -0700 Received: from BGMAIL101.nvidia.com (10.25.59.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:25 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by bgmail101.nvidia.com (10.25.59.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:21 +0000 Received: from rrajk-ubuntu.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 21 Mar 2018 04:41:12 +0000 From: Rajkumar Rampelli To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 4/9] arm64: tegra: Add Tachometer Controller on Tegra186 Date: Wed, 21 Mar 2018 10:10:39 +0530 Message-ID: <1521607244-29734-5-git-send-email-rrajk@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> References: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The NVIDIA Tegra186 SoC has a Tachometer Controller that analyzes the PWM signal of a Fan and reports the period value through pwm interface. Signed-off-by: Rajkumar Rampelli --- V2: Renamed clock-names/reset-names dt properties values to "tachometer" Renamed compatible property value to "nvidia-tegra186-pwm-tachometer" arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 5 +++++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index bd5305a..13c3e59 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -172,4 +172,9 @@ vin-supply = <&vdd_5v0_sys>; }; }; + + tachometer@39c0000 { + nvidia,pulse-per-rev = <2>; + nvidia,capture-window-len = <2>; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 731cd01..19e1afc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1042,4 +1042,15 @@ reset-names = "pwm"; status = "disabled"; }; + + tegra_tachometer: tachometer@39c0000 { + compatible = "nvidia,tegra186-pwm-tachometer"; + reg = <0x0 0x039c0000 0x0 0x10>; + #pwm-cells = <2>; + clocks = <&bpmp TEGRA186_CLK_TACH>; + clock-names = "tachometer"; + resets = <&bpmp TEGRA186_RESET_TACH>; + reset-names = "tachometer"; + status = "disabled"; + }; }; From patchwork Wed Mar 21 04:40:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajkumar Rampelli X-Patchwork-Id: 888553 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405ccM23mMz9ryk for ; Wed, 21 Mar 2018 15:42:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752116AbeCUEln (ORCPT ); Wed, 21 Mar 2018 00:41:43 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6992 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751963AbeCUElj (ORCPT ); Wed, 21 Mar 2018 00:41:39 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 20 Mar 2018 21:41:48 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 20 Mar 2018 21:41:38 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 20 Mar 2018 21:41:38 -0700 Received: from BGMAIL104.nvidia.com (10.25.59.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:37 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by bgmail104.nvidia.com (10.25.59.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:33 +0000 Received: from rrajk-ubuntu.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 21 Mar 2018 04:41:23 +0000 From: Rajkumar Rampelli To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 5/9] pwm: tegra: Add PWM based Tachometer driver Date: Wed, 21 Mar 2018 10:10:40 +0530 Message-ID: <1521607244-29734-6-git-send-email-rrajk@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> References: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org PWM Tachometer driver capture the PWM signal which is output of FAN in general and provide the period of PWM signal which is converted to RPM by SW. Add Tegra Tachometer driver which implements the pwm-capture to measure period. Signed-off-by: Rajkumar Rampelli Signed-off-by: Laxman Dewangan --- V2: Renamed compatible string to "nvidia-tegra186-pwm-tachometer" Renamed arguments of reset and clk apis to "tachometer" from "tach" drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-tegra-tachometer.c | 303 +++++++++++++++++++++++++++++++++++++ 3 files changed, 314 insertions(+) create mode 100644 drivers/pwm/pwm-tegra-tachometer.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 763ee50..29aeeeb 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -454,6 +454,16 @@ config PWM_TEGRA To compile this driver as a module, choose M here: the module will be called pwm-tegra. +config PWM_TEGRA_TACHOMETER + tristate "NVIDIA Tegra Tachometer PWM driver" + depends on ARCH_TEGRA + help + NVIDIA Tegra Tachometer reads the PWM signal and reports the PWM + signal periods. This helps in measuring the fan speed where Fan + output for speed is PWM signal. + + This driver support the Tachometer driver in PWM framework. + config PWM_TIECAP tristate "ECAP PWM support" depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX || ARCH_KEYSTONE diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0258a74..14c183e 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o +obj-$(CONFIG_PWM_TEGRA_TACHOMETER) += pwm-tegra-tachometer.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o obj-$(CONFIG_PWM_TIPWMSS) += pwm-tipwmss.o diff --git a/drivers/pwm/pwm-tegra-tachometer.c b/drivers/pwm/pwm-tegra-tachometer.c new file mode 100644 index 0000000..bcc44ce --- /dev/null +++ b/drivers/pwm/pwm-tegra-tachometer.c @@ -0,0 +1,303 @@ +/* + * Tegra Tachometer Pulse-Width-Modulation driver + * + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Since oscillator clock (38.4MHz) serves as a clock source for + * the tach input controller, 1.0105263MHz (i.e. 38.4/38) has to be + * used as a clock value in the RPM calculations + */ +#define TACH_COUNTER_CLK 1010526 + +#define TACH_FAN_TACH0 0x0 +#define TACH_FAN_TACH0_PERIOD_MASK 0x7FFFF +#define TACH_FAN_TACH0_PERIOD_MAX 0x7FFFF +#define TACH_FAN_TACH0_PERIOD_MIN 0x0 +#define TACH_FAN_TACH0_WIN_LENGTH_SHIFT 25 +#define TACH_FAN_TACH0_WIN_LENGTH_MASK 0x3 +#define TACH_FAN_TACH0_OVERFLOW_MASK BIT(24) + +#define TACH_FAN_TACH1 0x4 +#define TACH_FAN_TACH1_HI_MASK 0x7FFFF +/* + * struct pwm_tegra_tach - Tegra tachometer object + * @dev: device providing the Tachometer + * @pulse_per_rev: Pulses per revolution of a Fan + * @capture_window_len: Defines the window of the FAN TACH monitor + * @regs: physical base addresses of the controller + * @clk: phandle list of tachometer clocks + * @rst: phandle to reset the controller + * @chip: PWM chip providing this PWM device + */ +struct pwm_tegra_tach { + struct device *dev; + void __iomem *regs; + struct clk *clk; + struct reset_control *rst; + u32 pulse_per_rev; + u32 capture_window_len; + struct pwm_chip chip; +}; + +static struct pwm_tegra_tach *to_tegra_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct pwm_tegra_tach, chip); +} + +static u32 tachometer_readl(struct pwm_tegra_tach *ptt, unsigned long reg) +{ + return readl(ptt->regs + reg); +} + +static inline void tachometer_writel(struct pwm_tegra_tach *ptt, u32 val, + unsigned long reg) +{ + writel(val, ptt->regs + reg); +} + +static int pwm_tegra_tach_set_wlen(struct pwm_tegra_tach *ptt, + u32 window_length) +{ + u32 tach0, wlen; + + /* + * As per FAN Spec, the window length value should be greater than or + * equal to Pulses Per Revolution value to measure the time period + * values accurately. + */ + if (ptt->pulse_per_rev > ptt->capture_window_len) { + dev_err(ptt->dev, + "Window length value < pulses per revolution value\n"); + return -EINVAL; + } + + if (hweight8(window_length) != 1) { + dev_err(ptt->dev, + "Valid value of window length is {1, 2, 4 or 8}\n"); + return -EINVAL; + } + + wlen = ffs(window_length) - 1; + tach0 = tachometer_readl(ptt, TACH_FAN_TACH0); + tach0 &= ~(TACH_FAN_TACH0_WIN_LENGTH_MASK << + TACH_FAN_TACH0_WIN_LENGTH_SHIFT); + tach0 |= wlen << TACH_FAN_TACH0_WIN_LENGTH_SHIFT; + tachometer_writel(ptt, tach0, TACH_FAN_TACH0); + + return 0; +} + +static int pwm_tegra_tach_capture(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_capture *result, + unsigned long timeout) +{ + struct pwm_tegra_tach *ptt = to_tegra_pwm_chip(chip); + unsigned long period; + u32 tach; + + tach = tachometer_readl(ptt, TACH_FAN_TACH1); + result->duty_cycle = tach & TACH_FAN_TACH1_HI_MASK; + + tach = tachometer_readl(ptt, TACH_FAN_TACH0); + if (tach & TACH_FAN_TACH0_OVERFLOW_MASK) { + /* Fan is stalled, clear overflow state by writing 1 */ + dev_dbg(ptt->dev, "Tachometer Overflow is detected\n"); + tachometer_writel(ptt, tach, TACH_FAN_TACH0); + } + + period = tach & TACH_FAN_TACH0_PERIOD_MASK; + if ((period == TACH_FAN_TACH0_PERIOD_MIN) || + (period == TACH_FAN_TACH0_PERIOD_MAX)) { + dev_dbg(ptt->dev, "Period set to min/max 0x%lx, Invalid RPM\n", + period); + result->period = 0; + result->duty_cycle = 0; + return 0; + } + + period = period + 1; + + period = DIV_ROUND_CLOSEST_ULL(period * ptt->pulse_per_rev * 1000000ULL, + ptt->capture_window_len * + TACH_COUNTER_CLK); + + /* + * period & duty cycle values are in units of micro seconds. + * Hence, convert them into nano seconds and store. + */ + result->period = period * 1000; + result->duty_cycle = result->duty_cycle * 1000; + + return 0; +} + +static const struct pwm_ops pwm_tegra_tach_ops = { + .capture = pwm_tegra_tach_capture, + .owner = THIS_MODULE, +}; + +static int pwm_tegra_tach_read_platform_data(struct pwm_tegra_tach *ptt) +{ + struct device_node *np = ptt->dev->of_node; + u32 pval; + int err = 0; + + err = of_property_read_u32(np, "nvidia,pulse-per-rev", &pval); + if (err < 0) { + dev_err(ptt->dev, + "\"nvidia,pulse-per-rev\" property is missing\n"); + return err; + } + ptt->pulse_per_rev = pval; + + err = of_property_read_u32(np, "nvidia,capture-window-len", &pval); + if (err < 0) { + dev_err(ptt->dev, + "\"nvidia,capture-window-len\" property is missing\n"); + return err; + } + ptt->capture_window_len = pval; + + return err; +} + +static int pwm_tegra_tach_probe(struct platform_device *pdev) +{ + struct pwm_tegra_tach *ptt; + struct resource *res; + int err = 0; + + ptt = devm_kzalloc(&pdev->dev, sizeof(*ptt), GFP_KERNEL); + if (!ptt) + return -ENOMEM; + + ptt->dev = &pdev->dev; + + err = pwm_tegra_tach_read_platform_data(ptt); + if (err < 0) + return err; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ptt->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ptt->regs)) { + dev_err(&pdev->dev, "Failed to remap I/O memory\n"); + return PTR_ERR(ptt->regs); + } + + platform_set_drvdata(pdev, ptt); + + ptt->clk = devm_clk_get(&pdev->dev, "tachometer"); + if (IS_ERR(ptt->clk)) { + err = PTR_ERR(ptt->clk); + dev_err(&pdev->dev, "Failed to get Tachometer clk: %d\n", err); + return err; + } + + ptt->rst = devm_reset_control_get(&pdev->dev, "tachometer"); + if (IS_ERR(ptt->rst)) { + err = PTR_ERR(ptt->rst); + dev_err(&pdev->dev, "Failed to get reset handle: %d\n", err); + return err; + } + + err = clk_prepare_enable(ptt->clk); + if (err < 0) { + dev_err(&pdev->dev, "Failed to prepare clock: %d\n", err); + return err; + } + + err = clk_set_rate(ptt->clk, TACH_COUNTER_CLK); + if (err < 0) { + dev_err(&pdev->dev, "Failed to set clock rate %d: %d\n", + TACH_COUNTER_CLK, err); + goto clk_unprep; + } + + reset_control_reset(ptt->rst); + + ptt->chip.dev = &pdev->dev; + ptt->chip.ops = &pwm_tegra_tach_ops; + ptt->chip.base = -1; + ptt->chip.npwm = 1; + + err = pwmchip_add(&ptt->chip); + if (err < 0) { + dev_err(&pdev->dev, "Failed to add tachometer PWM: %d\n", err); + goto reset_assert; + } + + err = pwm_tegra_tach_set_wlen(ptt, ptt->capture_window_len); + if (err < 0) { + dev_err(ptt->dev, "Failed to set window length: %d\n", err); + goto pwm_remove; + } + + return 0; + +pwm_remove: + pwmchip_remove(&ptt->chip); + +reset_assert: + reset_control_assert(ptt->rst); + +clk_unprep: + clk_disable_unprepare(ptt->clk); + + return err; +} + +static int pwm_tegra_tach_remove(struct platform_device *pdev) +{ + struct pwm_tegra_tach *ptt = platform_get_drvdata(pdev); + + reset_control_assert(ptt->rst); + + clk_disable_unprepare(ptt->clk); + + return pwmchip_remove(&ptt->chip); +} + +static const struct of_device_id pwm_tegra_tach_of_match[] = { + { .compatible = "nvidia,tegra186-pwm-tachometer" }, + {} +}; +MODULE_DEVICE_TABLE(of, pwm_tegra_tach_of_match); + +static struct platform_driver tegra_tach_driver = { + .driver = { + .name = "pwm-tegra-tachometer", + .of_match_table = pwm_tegra_tach_of_match, + }, + .probe = pwm_tegra_tach_probe, + .remove = pwm_tegra_tach_remove, +}; + +module_platform_driver(tegra_tach_driver); + +MODULE_DESCRIPTION("PWM based NVIDIA Tegra Tachometer driver"); +MODULE_AUTHOR("Rajkumar Rampelli "); +MODULE_AUTHOR("Laxman Dewangan "); +MODULE_LICENSE("GPL v2"); From patchwork Wed Mar 21 04:40:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajkumar Rampelli X-Patchwork-Id: 888561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405cjN4GZqz9ryk for ; Wed, 21 Mar 2018 15:47:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751834AbeCUErI (ORCPT ); Wed, 21 Mar 2018 00:47:08 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:42867 "EHLO nat-hk.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751524AbeCUErF (ORCPT ); Wed, 21 Mar 2018 00:47:05 -0400 Received: from hkpgpgate101.nvidia.com (Not Verified[10.18.92.9]) by nat-hk.nvidia.com id ; Wed, 21 Mar 2018 12:41:53 +0800 Received: from HKMAIL104.nvidia.com ([10.18.16.13]) by hkpgpgate101.nvidia.com (PGP Universal service); Tue, 20 Mar 2018 21:41:53 -0700 X-PGP-Universal: processed; by hkpgpgate101.nvidia.com on Tue, 20 Mar 2018 21:41:53 -0700 Received: from DRBGMAIL104.nvidia.com (10.18.16.23) by HKMAIL104.nvidia.com (10.18.16.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:52 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by DRBGMAIL104.nvidia.com (10.18.16.23) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:44 +0000 Received: from rrajk-ubuntu.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 21 Mar 2018 04:41:35 +0000 From: Rajkumar Rampelli To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 6/9] arm64: tegra: Add pwm based fan support on Tegra186 Date: Wed, 21 Mar 2018 10:10:41 +0530 Message-ID: <1521607244-29734-7-git-send-email-rrajk@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> References: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add pwm fan driver support on Tegra186 SoC. Signed-off-by: Rajkumar Rampelli --- V2: Removed generic-pwm-tachometer driver dt node and using pwm-fan driver for reading fan speed. arch/arm64/boot/dts/nvidia/tegra186.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 19e1afc..27ae73e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1053,4 +1053,10 @@ reset-names = "tachometer"; status = "disabled"; }; + + pwm_fan { + compatible = "pwm-fan"; + pwms = <&tegra_tachometer 0 1000000>; + status = "disabled"; + }; }; From patchwork Wed Mar 21 04:40:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajkumar Rampelli X-Patchwork-Id: 888551 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405ccB2rlgz9ryk for ; Wed, 21 Mar 2018 15:42:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751938AbeCUEmI (ORCPT ); Wed, 21 Mar 2018 00:42:08 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:7499 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751923AbeCUEmB (ORCPT ); Wed, 21 Mar 2018 00:42:01 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 20 Mar 2018 21:40:45 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 20 Mar 2018 21:42:00 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 20 Mar 2018 21:42:00 -0700 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:59 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:56 +0000 Received: from rrajk-ubuntu.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 21 Mar 2018 04:41:46 +0000 From: Rajkumar Rampelli To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 7/9] hwmon: pwm-fan: add sysfs node to read rpm of fan Date: Wed, 21 Mar 2018 10:10:42 +0530 Message-ID: <1521607244-29734-8-git-send-email-rrajk@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> References: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add fan device attribute fan1_input in pwm-fan driver to read speed of fan in rotations per minute. Signed-off-by: Rajkumar Rampelli --- V2: Removed generic-pwm-tachometer driver and using pwm-fan driver as per suggestions to read fan speed. Added fan device attribute to report speed of fan in rpms through hwmon sysfs. drivers/hwmon/pwm-fan.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/hwmon/pwm-fan.c b/drivers/hwmon/pwm-fan.c index 70cc0d1..8dda209 100644 --- a/drivers/hwmon/pwm-fan.c +++ b/drivers/hwmon/pwm-fan.c @@ -98,11 +98,34 @@ static ssize_t show_pwm(struct device *dev, return sprintf(buf, "%u\n", ctx->pwm_value); } +static ssize_t show_rpm(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct pwm_fan_ctx *ptt = dev_get_drvdata(dev); + struct pwm_device *pwm = ptt->pwm; + struct pwm_capture result; + unsigned int rpm = 0; + int ret; + + ret = pwm_capture(pwm, &result, 0); + if (ret < 0) { + pr_err("Failed to capture PWM: %d\n", ret); + return ret; + } + + if (result.period) + rpm = DIV_ROUND_CLOSEST_ULL(60ULL * NSEC_PER_SEC, + result.period); + + return sprintf(buf, "%u\n", rpm); +} static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0); +static SENSOR_DEVICE_ATTR(fan1_input, 0444, show_rpm, NULL, 0); static struct attribute *pwm_fan_attrs[] = { &sensor_dev_attr_pwm1.dev_attr.attr, + &sensor_dev_attr_fan1_input.dev_attr.attr, NULL, }; From patchwork Wed Mar 21 04:40:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajkumar Rampelli X-Patchwork-Id: 888547 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405cbg0r5nz9s12 for ; Wed, 21 Mar 2018 15:42:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752221AbeCUEmR (ORCPT ); Wed, 21 Mar 2018 00:42:17 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12258 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752041AbeCUEmN (ORCPT ); Wed, 21 Mar 2018 00:42:13 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 20 Mar 2018 21:42:07 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 20 Mar 2018 21:42:12 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 20 Mar 2018 21:42:12 -0700 Received: from UKMAIL102.nvidia.com (10.26.138.15) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:42:11 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by UKMAIL102.nvidia.com (10.26.138.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:42:07 +0000 Received: from rrajk-ubuntu.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 21 Mar 2018 04:41:58 +0000 From: Rajkumar Rampelli To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 8/9] arm64: defconfig: enable Nvidia Tegra Tachometer as a module Date: Wed, 21 Mar 2018 10:10:43 +0530 Message-ID: <1521607244-29734-9-git-send-email-rrajk@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> References: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra Tachometer driver implements PWM capture to measure period. Enable this driver as a module in the ARM64 defconfig. Signed-off-by: Rajkumar Rampelli --- V2: No changes in this patch arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 634b373..8b2bda7 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -550,6 +550,7 @@ CONFIG_PWM_MESON=m CONFIG_PWM_ROCKCHIP=y CONFIG_PWM_SAMSUNG=y CONFIG_PWM_TEGRA=m +CONFIG_PWM_TEGRA_TACHOMETER=m CONFIG_PHY_RCAR_GEN3_USB2=y CONFIG_PHY_HI6220_USB=y CONFIG_PHY_QCOM_USB_HS=y From patchwork Wed Mar 21 04:40:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajkumar Rampelli X-Patchwork-Id: 888550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405cc14ZS1z9s12 for ; Wed, 21 Mar 2018 15:42:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752280AbeCUEme (ORCPT ); Wed, 21 Mar 2018 00:42:34 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:7027 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752251AbeCUEm3 (ORCPT ); Wed, 21 Mar 2018 00:42:29 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 20 Mar 2018 21:42:37 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 20 Mar 2018 21:42:28 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 20 Mar 2018 21:42:28 -0700 Received: from DRUKMAIL101.nvidia.com (10.25.59.19) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:42:24 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by drukmail101.nvidia.com (10.25.59.19) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:42:20 +0000 Received: from rrajk-ubuntu.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 21 Mar 2018 04:42:10 +0000 From: Rajkumar Rampelli To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 9/9] arm64: defconfig: enable pwm-fan as a loadable module Date: Wed, 21 Mar 2018 10:10:44 +0530 Message-ID: <1521607244-29734-10-git-send-email-rrajk@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> References: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable pwm-fan driver to make use of a PWM interface to read speed of a fan in rotations per minute. Signed-off-by: Rajkumar Rampelli --- V2: Added pwm-fan driver support as a loadable module. Removed generic-pwm-tachometer driver support which was added as part of v1 arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8b2bda7..50aa3bce 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -320,6 +320,7 @@ CONFIG_SYSCON_REBOOT_MODE=y CONFIG_BATTERY_BQ27XXX=y CONFIG_SENSORS_ARM_SCPI=y CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_INA2XX=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y