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Mon, 03 Apr 2023 10:29:07 -0700 (PDT) X-Google-Smtp-Source: AKy350Z37SKIctpg/J4qHs5epRsXb7IbD4h4SyJWzFsyhYsjF05gngeciS/43fM9JMfRpiWvq+gjlg== X-Received: by 2002:a05:6402:796:b0:4be:b39b:ea8f with SMTP id d22-20020a056402079600b004beb39bea8fmr53417edy.2.1680542947346; Mon, 03 Apr 2023 10:29:07 -0700 (PDT) Received: from [192.168.10.118] ([2001:b07:6468:f312:9af8:e5f5:7516:fa89]) by smtp.gmail.com with ESMTPSA id k17-20020a50c091000000b004fa99a22c3bsm4837104edf.61.2023.04.03.10.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 10:29:06 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH] target/mips: tcg: detect out-of-bounds accesses to cpu_gpr and cpu_gpr_hi Date: Mon, 3 Apr 2023 19:29:06 +0200 Message-Id: <20230403172906.397188-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In some cases (for example gen_compute_branch_nm in nanomips_translate.c.inc) registers can be unused on some paths and a negative value is passed in that case: gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2, imm << 1); To avoid an out of bounds access in those cases, introduce assertions. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/mips/tcg/translate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 1fb4ef712729..999fbb7cc1c0 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1223,6 +1223,7 @@ static const char regnames_LO[][4] = { /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) { + assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); if (reg == 0) { tcg_gen_movi_tl(t, 0); } else { @@ -1232,6 +1233,7 @@ void gen_load_gpr(TCGv t, int reg) void gen_store_gpr(TCGv t, int reg) { + assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); if (reg != 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); } @@ -1240,6 +1242,7 @@ void gen_store_gpr(TCGv t, int reg) #if defined(TARGET_MIPS64) void gen_load_gpr_hi(TCGv_i64 t, int reg) { + assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi)); if (reg == 0) { tcg_gen_movi_i64(t, 0); } else { @@ -1249,6 +1252,7 @@ void gen_load_gpr_hi(TCGv_i64 t, int reg) void gen_store_gpr_hi(TCGv_i64 t, int reg) { + assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi)); if (reg != 0) { tcg_gen_mov_i64(cpu_gpr_hi[reg], t); }