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[76.229.100.169]) by smtp.gmail.com with ESMTPSA id cp33-20020a05690c0e2100b00545a08184dbsm2283579ywb.107.2023.04.02.21.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Apr 2023 21:42:56 -0700 (PDT) From: Tony Dinh To: =?unknown-8bit?q?U-Boot_Mailing_List_=3Cu-boot=40lists=2Edenx=2Ede=3E=2C?= =?unknown-8bit?q?_Stefan_Roese_=3Csr=40denx=2Ede=3E=2C_Pali_Roh=E1r__=3Cpal?= =?unknown-8bit?q?i=40kernel=2Eorg=3E?= Cc: =?unknown-8bit?q?Jaehoon_Chung_=3Cjh80=2Echung=40samsung=2Ecom=3E=2C_Tom?= =?unknown-8bit?q?_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C_Marek_Beh=FAn__=3Cma?= =?unknown-8bit?q?rek=2Ebehun=40nic=2Ecz=3E=2C_Michael_Trimarchi_=3Cmichael?= =?unknown-8bit?q?=40amarulasolutions=2Ecom=3E=2C_Chris_Packham_=3Cjudge=2Ep?= =?unknown-8bit?q?ackham=40gmail=2Ecom=3E=2C_Mark_Kettenis_=3Ckettenis=40ope?= =?unknown-8bit?q?nbsd=2Eorg=3E=2C_Martin_Rowe_=3Cmartin=2Ep=2Erowe=40gmail?= =?unknown-8bit?q?=2Ecom=3E=2C_Simon_Glass_=3Csjg=40chromium=2Eorg=3E=2C_Ton?= =?unknown-8bit?q?y_Dinh_=3Cmibodhi=40gmail=2Ecom=3E?= Subject: [PATCH] ddr: marvell: a38x: Perform DDR training sequence again for 2nd boot Date: Sun, 2 Apr 2023 21:42:33 -0700 Message-Id: <20230403044233.25863-1-mibodhi@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean - DDR Training sequence happens very fast. The speedup in boot time is negligible by skipping the training sequence during 2nd boot or after. So remove the check and skip. - This change improves the robustness of DDR training. If u-boot crashed during DDR training, the training could be left in a limbo state, where the BootROM has recorded that it is already in a 2nd boot. The training must be repeated in this scenario to get out of this limbo state, but due to the check it cannot be performed. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- drivers/ddr/marvell/a38x/mv_ddr_plat.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 6e7949ac72..8ec9fb0874 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -1363,13 +1363,6 @@ int mv_ddr_pre_training_soc_config(const char *ddr_type) DRAM_RESET_MASK_MASKED << DRAM_RESET_MASK_OFFS); } - /* Check if DRAM is already initialized */ - if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & - (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) { - printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type); - return MV_OK; - } - /* Fix read ready phases for all SOC in reg 0x15c8 */ reg_val = reg_read(TRAINING_DBG_3_REG);