From patchwork Tue Mar 28 08:48:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Botcazou X-Patchwork-Id: 1762211 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=bnDJq/6L; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Pm3Jq4JpXz1yYV for ; Tue, 28 Mar 2023 19:49:31 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F20933858020 for ; Tue, 28 Mar 2023 08:49:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F20933858020 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1679993369; bh=pYXYQN/TJYabFwWChKehwFCSSAU4tgHJyp+WUqI4ukQ=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=bnDJq/6LP+ui2UuYYTfZ7zn9YN/OzlkiKWO+SVY92ahwUWnzynSkMWfxhpDICffqW /h3s+L50kZdmLDQR0d/Fi/LkkaM7f5D3dpmTT75fN8KaRam9BEjCSOY6PqRhML8tA2 oBjnHzb1ZdmOV6VbKYGOgEv72umgCKZCld/ju5+8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by sourceware.org (Postfix) with ESMTPS id 460703858425 for ; Tue, 28 Mar 2023 08:48:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 460703858425 Received: by mail-wm1-x333.google.com with SMTP id n10-20020a05600c4f8a00b003ee93d2c914so8539042wmq.2 for ; Tue, 28 Mar 2023 01:48:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679993325; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=pYXYQN/TJYabFwWChKehwFCSSAU4tgHJyp+WUqI4ukQ=; b=arzeD0PXUUjUVyVzx5Hq2to5GzSAg1Qr4GG7LTZt3b+62Zhab+LQoQOpWjkSOXfbfC d2FJ7bD/4WByg5DLSUvI6K66RSTEJOwjSiDRNl3rKgB2YxA8ExUQD2etaaJ0t1W5iXwR OebD+SKCvlelWDYpGw7XOLEnb7OhmKL7yiJcJVIw4hIjAubS/61Yeezl1Xq2VF5AFRIK b/YT9cVq/Vi2HrWnr2RKojMe4urlEskzuq5PD5QduNaylvX4WqC0QF0p8Flx/4Rdm37o f9h00yUF48WGBu16TzyDZixPDdcNb9JF23tqDX+Vmwrz3diLt3bz8LkMXvc58Eadzd+0 kHHw== X-Gm-Message-State: AO0yUKV9+matiNQy4AgaG2E2kPhoUVmFhanWNcGqDG9RgB89ucRXiBiH 9wFnwQYNtuzAJgr1s3HSb1q8DAm448AomXKTN/A= X-Google-Smtp-Source: AK7set/5xBSbaerWqZ//QBx+R+KCPrhAo88JfQv/dkF9w3DVT1PMijhIGx9SNm9jlkRHNLxHf64wVw== X-Received: by 2002:a7b:c84e:0:b0:3db:8de:6993 with SMTP id c14-20020a7bc84e000000b003db08de6993mr10843822wml.4.1679993324810; Tue, 28 Mar 2023 01:48:44 -0700 (PDT) Received: from fomalhaut.localnet ([2a01:e0a:8d5:d990:e654:e8ff:fe8f:2ce6]) by smtp.gmail.com with ESMTPSA id z5-20020a7bc7c5000000b003ee1b2ab9a0sm16389862wmk.11.2023.03.28.01.48.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 01:48:44 -0700 (PDT) X-Google-Original-From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Fix PR target/109140 Date: Tue, 28 Mar 2023 10:48:43 +0200 Message-ID: <8198261.T7Z3S40VBb@fomalhaut> MIME-Version: 1.0 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Eric Botcazou via Gcc-patches From: Eric Botcazou Reply-To: Eric Botcazou Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This is a regression present on the mainline and 12 branch at -O2, but the issue is related to vectorization so was present at -O3 in earlier versions. The vcondu expander that was added for VIS 3 more than a decade ago does not fully work, because it does not filter out the unsigned condition codes (the instruction is an UNSPEC that accepts only signed condition codes). While I was at it, I also added the missing vcond and vcondu expanders for the new comparison instructions that were added in VIS 4. Tested on SPARC/Solaris, applied on the mainline, 12 and 11 branches. 2023-03-28 Eric Botcazou PR target/109140 * config/sparc/sparc.cc (sparc_expand_vcond): Call signed_condition on operand #3 to get the final condition code. Use std::swap. * config/sparc/sparc.md (vcondv8qiv8qi): New VIS 4 expander. (fucmp8_vis): Move around. (fpcmpu_vis): Likewise. (vcondu): New VIS 4 expander. 2023-03-28 Eric Botcazou * gcc.target/sparc/20230328-1.c: New test. * gcc.target/sparc/20230328-2.c: Likewise. * gcc.target/sparc/20230328-3.c: Likewise. * gcc.target/sparc/20230328-4.c: Likewise. diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc index 644ff9cf594..8c0c9dce971 100644 --- a/gcc/config/sparc/sparc.cc +++ b/gcc/config/sparc/sparc.cc @@ -13662,18 +13662,16 @@ sparc_expand_conditional_move (machine_mode mode, rtx *operands) void sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode) { + enum rtx_code code = signed_condition (GET_CODE (operands[3])); rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr; - enum rtx_code code = GET_CODE (operands[3]); mask = gen_reg_rtx (Pmode); cop0 = operands[4]; cop1 = operands[5]; if (code == LT || code == GE) { - rtx t; - code = swap_condition (code); - t = cop0; cop0 = cop1; cop1 = t; + std::swap (cop0, cop1); } gsr = gen_rtx_REG (DImode, SPARC_GSR_REG); diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 417b588e610..94779c16c63 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -9033,6 +9033,50 @@ visl") DONE; }) +(define_expand "vcondv8qiv8qi" + [(match_operand:V8QI 0 "register_operand" "") + (match_operand:V8QI 1 "register_operand" "") + (match_operand:V8QI 2 "register_operand" "") + (match_operator 3 "" + [(match_operand:V8QI 4 "register_operand" "") + (match_operand:V8QI 5 "register_operand" "")])] + "TARGET_VIS4" +{ + sparc_expand_vcond (V8QImode, operands, UNSPEC_CMASK8, UNSPEC_FCMP); + DONE; +}) + +(define_insn "fucmp8_vis" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") + (match_operand:V8QI 2 "register_operand" "e"))] + UNSPEC_FUCMP))] + "TARGET_VIS3" + "fucmp8\t%1, %2, %0" + [(set_attr "type" "viscmp")]) + +(define_insn "fpcmpu_vis" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e") + (match_operand:GCM 2 "register_operand" "e"))] + UNSPEC_FUCMP))] + "TARGET_VIS4" + "fpcmpu\t%1, %2, %0" + [(set_attr "type" "viscmp")]) + +(define_expand "vcondu" + [(match_operand:GCM 0 "register_operand" "") + (match_operand:GCM 1 "register_operand" "") + (match_operand:GCM 2 "register_operand" "") + (match_operator 3 "" + [(match_operand:GCM 4 "register_operand" "") + (match_operand:GCM 5 "register_operand" "")])] + "TARGET_VIS4" +{ + sparc_expand_vcond (mode, operands, UNSPEC_CMASK, UNSPEC_FUCMP); + DONE; +}) + (define_expand "vconduv8qiv8qi" [(match_operand:V8QI 0 "register_operand" "") (match_operand:V8QI 1 "register_operand" "") @@ -9351,24 +9395,6 @@ visl") [(set_attr "type" "fga") (set_attr "subtype" "other")]) -(define_insn "fucmp8_vis" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") - (match_operand:V8QI 2 "register_operand" "e"))] - UNSPEC_FUCMP))] - "TARGET_VIS3" - "fucmp8\t%1, %2, %0" - [(set_attr "type" "viscmp")]) - -(define_insn "fpcmpu_vis" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e") - (match_operand:GCM 2 "register_operand" "e"))] - UNSPEC_FUCMP))] - "TARGET_VIS4" - "fpcmpu\t%1, %2, %0" - [(set_attr "type" "viscmp")]) - (define_insn "*naddsf3" [(set (match_operand:SF 0 "register_operand" "=f") (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "f")