From patchwork Tue Mar 21 17:25:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1759532 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=mailbox.org header.i=@mailbox.org header.a=rsa-sha256 header.s=mail20150812 header.b=OrzjXluV; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.a=rsa-sha256 header.s=mail20150812 header.b=nkFY0RQ/; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Pgz6n6Pzwz247m for ; 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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1679419573; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=JdTtpFVwjM9NHWkmsM8JkVTt69uLgA7MSSWM723E0vg=; b=nkFY0RQ/NzmPRq/v+rAmW6qwq3df1Wr6Z40Cwk2k6TaDbhG1OyT7hpwf6pW2CVlKcWSrBH WQX7hheLpCY1pWFxGOy6OsSVAJMw8pDXObLSo6/8sDMh4jVfoxaUpJzjzNnyrTLZ7gtXxR sjhGBfbCevRMQ/5o+zbX7q6P+XXp/OVYRZEpoJcHx5nS/IKt/8PqYMiXwAkvgVgqU3/GnZ 4ZjlFM/JJBZVB6U5dulf2Qj78A5yjFipeaksva93ZtbtJZSuoUBSiY4qA7mVf8HqbtGJ3B zEpbk4mBNf+Igmlq7qbietQGNZ4zHJm4etg+sPpKwCYY4fJwpHFzGvBEUGKTjw== To: u-boot@lists.denx.de Cc: Marek Vasut , "Ariel D'Alessandro" , =?utf-8?q?Marek_Beh?= =?utf-8?q?=C3=BAn?= , Joe Hershberger , Ramon Fried , Stefan Roese , Tim Harvey , Vladimir Oltean Subject: [PATCH v2 1/3] net: mvpp2: Drop PHY_INTERFACE_MODE_SGMII_2500 support Date: Tue, 21 Mar 2023 18:25:52 +0100 Message-Id: <20230321172554.7158-1-marek.vasut+renesas@mailbox.org> MIME-Version: 1.0 X-MBO-RS-ID: f71a1927684b586a688 X-MBO-RS-META: wwdosawuhypdf4gx7i6oupfp9twmx8t4 X-Rspamd-Queue-Id: 4Pgz6H5q0rz9sPx X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This mode does not seem to be well defined and used anywhere, remove support for it. Based on discussion: - 1000baseX does c37 AN of duplex+pause - SGMII does AN of duplex+pause+speed, at lower speed bytes are repeated 10x/100x - 2500baseX does not do AN, or does very different c73 AN - SGMII 2500 behavior is unclear Signed-off-by: Marek Vasut Reviewed-by: Ramon Fried --- Cc: "Ariel D'Alessandro" Cc: "Marek Behún" Cc: Joe Hershberger Cc: Marek Vasut Cc: Ramon Fried Cc: Stefan Roese Cc: Tim Harvey Cc: Vladimir Oltean --- V2: Drop SGMII 2500 support, if it becomes required and/or standardized, this patch can be reverted --- drivers/net/mvpp2.c | 53 --------------------------------------------- 1 file changed, 53 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 1bad50d344c..c99d52c85d7 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -2871,7 +2871,6 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port) switch (port->phy_interface) { case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: val |= MVPP2_GMAC_INBAND_AN_MASK; break; case PHY_INTERFACE_MODE_1000BASEX: @@ -2939,7 +2938,6 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port) val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || - port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 || port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) val |= MVPP2_GMAC_PCS_LB_EN_MASK; @@ -3027,48 +3025,6 @@ static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en) return 0; } -static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port) -{ - u32 val, thresh; - - /* - * Configure minimal level of the Tx FIFO before the lower part - * starts to read a packet - */ - thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH; - val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); - val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; - val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh); - writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); - - /* Disable bypass of sync module */ - val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); - val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK; - /* configure DP clock select according to mode */ - val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK; - /* configure QSGMII bypass according to mode */ - val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK; - writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); - - val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); - /* - * Configure GIG MAC to SGMII mode connected to a fiber - * transceiver - */ - val &= ~MVPP2_GMAC_PORT_TYPE_MASK; - writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); - - /* configure AN 0x9268 */ - val = MVPP2_GMAC_EN_PCS_AN | - MVPP2_GMAC_AN_BYPASS_EN | - MVPP2_GMAC_CONFIG_MII_SPEED | - MVPP2_GMAC_CONFIG_GMII_SPEED | - MVPP2_GMAC_FC_ADV_EN | - MVPP2_GMAC_CONFIG_FULL_DUPLEX | - MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG; - writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); -} - static void gop_gmac_sgmii_cfg(struct mvpp2_port *port) { u32 val, thresh; @@ -3239,9 +3195,6 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port) case PHY_INTERFACE_MODE_SGMII: gop_gmac_sgmii_cfg(port); break; - case PHY_INTERFACE_MODE_SGMII_2500: - gop_gmac_sgmii2_5_cfg(port); - break; case PHY_INTERFACE_MODE_1000BASEX: gop_gmac_1000basex_cfg(port); break; @@ -3422,7 +3375,6 @@ static int gop_port_init(struct mvpp2_port *port) break; case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: /* configure PCS */ @@ -3482,7 +3434,6 @@ static void gop_port_enable(struct mvpp2_port *port, int enable) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: if (enable) @@ -3519,7 +3470,6 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type) if (gop_id == 2) { if (phy_type == PHY_INTERFACE_MODE_SGMII || - phy_type == PHY_INTERFACE_MODE_SGMII_2500 || phy_type == PHY_INTERFACE_MODE_1000BASEX || phy_type == PHY_INTERFACE_MODE_2500BASEX) val |= MV_NETC_GE_MAC2_SGMII; @@ -3530,7 +3480,6 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type) if (gop_id == 3) { if (phy_type == PHY_INTERFACE_MODE_SGMII || - phy_type == PHY_INTERFACE_MODE_SGMII_2500 || phy_type == PHY_INTERFACE_MODE_1000BASEX || phy_type == PHY_INTERFACE_MODE_2500BASEX) val |= MV_NETC_GE_MAC3_SGMII; @@ -4529,7 +4478,6 @@ static void mvpp2_start_dev(struct mvpp2_port *port) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: mvpp2_gmac_max_rx_size_set(port); @@ -5263,7 +5211,6 @@ static int mvpp2_start(struct udevice *dev) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: mvpp2_port_power_up(port); From patchwork Tue Mar 21 17:25:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1759534 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1679419575; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=X8TM4+25+MgotwMezhFBEEB4bO5zEoSL4R42/o5o1LE=; b=fBmSUuYfk2TVT+k4DUUsW5HFd5s3baPOQcRZx4UeENOyjXVIxI2yvRhg7BH8KXicg/eWJv W2coMG1PabeZ3RaSRmkI82SCAdGNeZnSijZxCl5S2zqAl9ju/cb0L6DZ3rkOXvRJFMTOST +c7aucd2sKZyJ0tDeuTk0PAZOewOnd3skFqL2AXvyztUbfqSOG9qQIzCm+DfP5nqSmbGaz KXZnWT/UrHivgM/Aqnh6mPPcgS/KFlssVUMn29EtunUaJSnBoYyH/BNsRa6z9CuDPxUst9 k8nyfbZ1Jye0pJ5OoDUkTKr6UsQaKsj8KRXzFc2jDZ4W1yl9q/kESwyIlGR6Ag== To: u-boot@lists.denx.de Cc: Marek Vasut , "Ariel D'Alessandro" , =?utf-8?q?Marek_Beh?= =?utf-8?q?=C3=BAn?= , Joe Hershberger , Ramon Fried , Stefan Roese , Tim Harvey , Vladimir Oltean Subject: [PATCH v2 2/3] net: mvpp2: Replace PHY_INTERFACE_MODE_SFI with 5GBASER/10GBASER/XAUI Date: Tue, 21 Mar 2023 18:25:53 +0100 Message-Id: <20230321172554.7158-2-marek.vasut+renesas@mailbox.org> In-Reply-To: <20230321172554.7158-1-marek.vasut+renesas@mailbox.org> References: <20230321172554.7158-1-marek.vasut+renesas@mailbox.org> MIME-Version: 1.0 X-MBO-RS-ID: cff701777e44c4b73d5 X-MBO-RS-META: epi4c9hcd69z3oepniayq9w8kcashuhw X-Rspamd-Queue-Id: 4Pgz6K1qPNz9spw X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Replace PHY_INTERFACE_MODE_SFI with PHY_INTERFACE_MODE_5GBASER, PHY_INTERFACE_MODE_10GBASER and PHY_INTERFACE_MODE_XAUI to match Linux PHY interface modes. Signed-off-by: Marek Vasut Reviewed-by: Ramon Fried --- Cc: "Ariel D'Alessandro" Cc: "Marek Behún" Cc: Joe Hershberger Cc: Marek Vasut Cc: Ramon Fried Cc: Stefan Roese Cc: Tim Harvey Cc: Vladimir Oltean --- V2: No change --- drivers/net/mvpp2.c | 8 ++++++-- include/phy_interface.h | 2 ++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index c99d52c85d7..f407d8f6a81 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -3391,7 +3391,9 @@ static int gop_port_init(struct mvpp2_port *port) gop_gmac_reset(port, 0); break; - case PHY_INTERFACE_MODE_SFI: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_5GBASER: + case PHY_INTERFACE_MODE_XAUI: num_of_act_lanes = 2; mac_num = 0; /* configure PCS */ @@ -3442,7 +3444,9 @@ static void gop_port_enable(struct mvpp2_port *port, int enable) mvpp2_port_disable(port); break; - case PHY_INTERFACE_MODE_SFI: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_5GBASER: + case PHY_INTERFACE_MODE_XAUI: gop_xlg_mac_port_enable(port, enable); break; diff --git a/include/phy_interface.h b/include/phy_interface.h index fed3357b9a2..52af7e612b6 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -31,6 +31,7 @@ typedef enum { PHY_INTERFACE_MODE_XGMII, PHY_INTERFACE_MODE_XAUI, PHY_INTERFACE_MODE_RXAUI, + PHY_INTERFACE_MODE_5GBASER, PHY_INTERFACE_MODE_SFI, PHY_INTERFACE_MODE_INTERNAL, PHY_INTERFACE_MODE_25G_AUI, @@ -62,6 +63,7 @@ static const char * const phy_interface_strings[] = { [PHY_INTERFACE_MODE_XGMII] = "xgmii", [PHY_INTERFACE_MODE_XAUI] = "xaui", [PHY_INTERFACE_MODE_RXAUI] = "rxaui", + [PHY_INTERFACE_MODE_5GBASER] = "5gbase-r", [PHY_INTERFACE_MODE_SFI] = "sfi", [PHY_INTERFACE_MODE_INTERNAL] = "internal", [PHY_INTERFACE_MODE_25G_AUI] = "25g-aui", From patchwork Tue Mar 21 17:25:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1759533 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1679419576; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zr5qUp+bf2Yw1abB3FjqJqT4tbR8fEBLrZfRhoZ7bH8=; b=hW54FX1gr+bcHDg6jHb2fcpn+Q2ToxZKkQIs4YG9q8j0yjM68vM7koJCpvQFtvTCCScZ5k TwS1Kgqy2I2wbqTqk5UhzsCoWeCiZy6gl1mhZ3IFQVZxxtrdmm/ixn6kSbu0hMAx2JDW1u urUGIfKwcQE15fscjlpZewGsW2xO3T4YcDjq0aYnQKjDIwMK4jniG/M+6m/unnb4FFBuq1 a4K0lKW82KDAi951YLRFIUBgJMhfwon+biKtTZqVQonCDCTSYXzii99Eg+E95EuG+H1RTa O8wo4e7gAM2Ogcg+3xS6R8Aogw/Uux4EOGBve0ieTiTC+NPabbap73ypmfSO3w== To: u-boot@lists.denx.de Cc: Marek Vasut , "Ariel D'Alessandro" , =?utf-8?q?Marek_Beh?= =?utf-8?q?=C3=BAn?= , Joe Hershberger , Ramon Fried , Stefan Roese , Tim Harvey , Vladimir Oltean Subject: [PATCH v2 3/3] net: phy: Synchronize PHY interface modes with Linux Date: Tue, 21 Mar 2023 18:25:54 +0100 Message-Id: <20230321172554.7158-3-marek.vasut+renesas@mailbox.org> In-Reply-To: <20230321172554.7158-1-marek.vasut+renesas@mailbox.org> References: <20230321172554.7158-1-marek.vasut+renesas@mailbox.org> MIME-Version: 1.0 X-MBO-RS-META: b6mi1fm6ur7kh7aox6fqs5k8uuxo7m15 X-MBO-RS-ID: 885cb4063bb49de050c X-Rspamd-Queue-Id: 4Pgz6L2yBZz9scd X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Synchronize PHY interface modes with Linux next 6.2.y commit: 0194b64578e90 ("net: phy: improve phy_read_poll_timeout") Retain LX2160A/LX2162A PHY modes as those are not yet supported by the Linux kernel, but isolate those with ifdeffery. Isolate NCSI which are also not supported by Linux kernel. Note that the ifdeffery cannot be avoided with IS_ENABLED() here due to compilation of the entire conditional, which would fail in case NCSI symbols are not available. Signed-off-by: Marek Vasut Reviewed-by: Ramon Fried --- Cc: "Ariel D'Alessandro" Cc: "Marek Behún" Cc: Joe Hershberger Cc: Marek Vasut Cc: Ramon Fried Cc: Stefan Roese Cc: Tim Harvey Cc: Vladimir Oltean --- V2: No change --- drivers/net/phy/phy.c | 4 +++ include/phy_interface.h | 68 +++++++++++++++++++++++++++++------------ 2 files changed, 53 insertions(+), 19 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 9b0e497f223..f720d0a7920 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -1160,7 +1160,11 @@ int phy_clear_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val bool phy_interface_is_ncsi(void) { +#ifdef CONFIG_PHY_NCSI struct eth_pdata *pdata = dev_get_plat(eth_get_dev()); return pdata->phy_interface == PHY_INTERFACE_MODE_NCSI; +#else + return 0; +#endif } diff --git a/include/phy_interface.h b/include/phy_interface.h index 52af7e612b6..31be3228c7c 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -14,65 +14,95 @@ typedef enum { PHY_INTERFACE_MODE_NA, /* don't touch */ + PHY_INTERFACE_MODE_INTERNAL, PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_SGMII, - PHY_INTERFACE_MODE_SGMII_2500, - PHY_INTERFACE_MODE_QSGMII, PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_REVMII, PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_REVRMII, PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_RGMII_ID, PHY_INTERFACE_MODE_RGMII_RXID, PHY_INTERFACE_MODE_RGMII_TXID, PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_SMII, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_XLGMII, + PHY_INTERFACE_MODE_MOCA, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TRGMII, + PHY_INTERFACE_MODE_100BASEX, PHY_INTERFACE_MODE_1000BASEX, PHY_INTERFACE_MODE_2500BASEX, - PHY_INTERFACE_MODE_XGMII, - PHY_INTERFACE_MODE_XAUI, - PHY_INTERFACE_MODE_RXAUI, PHY_INTERFACE_MODE_5GBASER, - PHY_INTERFACE_MODE_SFI, - PHY_INTERFACE_MODE_INTERNAL, + PHY_INTERFACE_MODE_RXAUI, + PHY_INTERFACE_MODE_XAUI, + /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */ + PHY_INTERFACE_MODE_10GBASER, + PHY_INTERFACE_MODE_25GBASER, + PHY_INTERFACE_MODE_USXGMII, + /* 10GBASE-KR - with Clause 73 AN */ + PHY_INTERFACE_MODE_10GKR, + PHY_INTERFACE_MODE_QUSGMII, + PHY_INTERFACE_MODE_1000BASEKX, +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) + /* LX2160A SERDES modes */ PHY_INTERFACE_MODE_25G_AUI, PHY_INTERFACE_MODE_XLAUI, PHY_INTERFACE_MODE_CAUI2, PHY_INTERFACE_MODE_CAUI4, +#endif +#if defined(CONFIG_PHY_NCSI) PHY_INTERFACE_MODE_NCSI, - PHY_INTERFACE_MODE_10GBASER, - PHY_INTERFACE_MODE_USXGMII, +#endif PHY_INTERFACE_MODE_MAX, } phy_interface_t; static const char * const phy_interface_strings[] = { - [PHY_INTERFACE_MODE_NA] = "", + [PHY_INTERFACE_MODE_NA] = "", + [PHY_INTERFACE_MODE_INTERNAL] = "internal", [PHY_INTERFACE_MODE_MII] = "mii", [PHY_INTERFACE_MODE_GMII] = "gmii", [PHY_INTERFACE_MODE_SGMII] = "sgmii", - [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", - [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", [PHY_INTERFACE_MODE_TBI] = "tbi", + [PHY_INTERFACE_MODE_REVMII] = "rev-mii", [PHY_INTERFACE_MODE_RMII] = "rmii", + [PHY_INTERFACE_MODE_REVRMII] = "rev-rmii", [PHY_INTERFACE_MODE_RGMII] = "rgmii", [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", [PHY_INTERFACE_MODE_RTBI] = "rtbi", + [PHY_INTERFACE_MODE_SMII] = "smii", + [PHY_INTERFACE_MODE_XGMII] = "xgmii", + [PHY_INTERFACE_MODE_XLGMII] = "xlgmii", + [PHY_INTERFACE_MODE_MOCA] = "moca", + [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", + [PHY_INTERFACE_MODE_TRGMII] = "trgmii", [PHY_INTERFACE_MODE_1000BASEX] = "1000base-x", + [PHY_INTERFACE_MODE_1000BASEKX] = "1000base-kx", [PHY_INTERFACE_MODE_2500BASEX] = "2500base-x", - [PHY_INTERFACE_MODE_XGMII] = "xgmii", - [PHY_INTERFACE_MODE_XAUI] = "xaui", - [PHY_INTERFACE_MODE_RXAUI] = "rxaui", [PHY_INTERFACE_MODE_5GBASER] = "5gbase-r", - [PHY_INTERFACE_MODE_SFI] = "sfi", - [PHY_INTERFACE_MODE_INTERNAL] = "internal", + [PHY_INTERFACE_MODE_RXAUI] = "rxaui", + [PHY_INTERFACE_MODE_XAUI] = "xaui", + [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", + [PHY_INTERFACE_MODE_25GBASER] = "25gbase-r", + [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", + [PHY_INTERFACE_MODE_10GKR] = "10gbase-kr", + [PHY_INTERFACE_MODE_100BASEX] = "100base-x", + [PHY_INTERFACE_MODE_QUSGMII] = "qusgmii", +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) + /* LX2160A SERDES modes */ [PHY_INTERFACE_MODE_25G_AUI] = "25g-aui", [PHY_INTERFACE_MODE_XLAUI] = "xlaui4", [PHY_INTERFACE_MODE_CAUI2] = "caui2", [PHY_INTERFACE_MODE_CAUI4] = "caui4", +#endif +#if defined(CONFIG_PHY_NCSI) [PHY_INTERFACE_MODE_NCSI] = "NC-SI", - [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", - [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", +#endif }; /* Backplane modes: