From patchwork Mon Mar 6 09:00:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1752246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4PVXc359t4z246K for ; Mon, 6 Mar 2023 20:00:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229557AbjCFJAv (ORCPT ); Mon, 6 Mar 2023 04:00:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229800AbjCFJAt (ORCPT ); Mon, 6 Mar 2023 04:00:49 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5D1B659E6; Mon, 6 Mar 2023 01:00:45 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.98,236,1673881200"; d="scan'208";a="154992587" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Mar 2023 18:00:43 +0900 Received: from localhost.localdomain (unknown [10.226.93.39]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id A175341C869B; Mon, 6 Mar 2023 18:00:39 +0900 (JST) From: Biju Das To: Linus Walleij , Philipp Zabel Cc: Biju Das , Geert Uytterhoeven , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Chris Paterson , Prabhakar Mahadev Lad Subject: [PATCH v6 06/13] drivers: pinctrl: renesas: Add RZ/G2L POEG driver support Date: Mon, 6 Mar 2023 09:00:07 +0000 Message-Id: <20230306090014.128732-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> References: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The output pins of the RZ/G2L general PWM timer (GPT) can be disabled by using the port output enabling function for the GPT (POEG). Add basic support using s/w control through generic pincontrol sysfs to enable/disable output from GPT by registering with RZ/G2L pincontrol driver. Signed-off-by: Biju Das --- v5->v6: * Dropped sysfs and is handled in generic driver. v4->v5: * Updated kernel version in sysfs doc. v3->v4: * Updated commit description. v2->v3: * Added sysfs documentation for output_disable * PWM_RZG2L_GPT implies ARCH_RZG2L. So removed ARCH_RZG2L dependency * Used dev_get_drvdata to get device data * Replaced sprintf->sysfs_emit in show(). v1->v2: * Renamed the file poeg-rzg2l->rzg2l-poeg * Removed the macro POEGG as there is only single register and updated rzg2l_poeg_write() and rzg2l_poeg_read() * Updated error handling in probe() Ref->v1: * Moved driver files from soc to pincontrol directory * Updated KConfig --- drivers/pinctrl/renesas/Kconfig | 2 + drivers/pinctrl/renesas/Makefile | 2 + drivers/pinctrl/renesas/poeg/Kconfig | 11 + drivers/pinctrl/renesas/poeg/Makefile | 2 + drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 254 ++++++++++++++++++++++ 5 files changed, 271 insertions(+) create mode 100644 drivers/pinctrl/renesas/poeg/Kconfig create mode 100644 drivers/pinctrl/renesas/poeg/Makefile create mode 100644 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 0903a0a41831..92bdc2e1e125 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -308,4 +308,6 @@ config PINCTRL_PFC_SHX3 bool "pin control support for SH-X3" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO +source "drivers/pinctrl/renesas/poeg/Kconfig" + endmenu diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 558b30ce0dec..de1bb592fbf3 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -52,6 +52,8 @@ obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o obj-$(CONFIG_PINCTRL_RZV2M) += pinctrl-rzv2m.o +obj-$(CONFIG_POEG_RZG2L) += poeg/ + ifeq ($(CONFIG_COMPILE_TEST),y) CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a diff --git a/drivers/pinctrl/renesas/poeg/Kconfig b/drivers/pinctrl/renesas/poeg/Kconfig new file mode 100644 index 000000000000..306e8ae81cb2 --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +config POEG_RZG2L + tristate "Renesas RZ/G2L poeg support" + depends on PWM_RZG2L_GPT || COMPILE_TEST + depends on HAS_IOMEM + help + This driver exposes the Port Output Enable for GPT(POEG) found + in Renesas RZ/G2L alike SoCs. + + To compile this driver as a module, choose M here: the module + will be called rzg2l-poeg. diff --git a/drivers/pinctrl/renesas/poeg/Makefile b/drivers/pinctrl/renesas/poeg/Makefile new file mode 100644 index 000000000000..610bdd6182be --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_POEG_RZG2L) += rzg2l-poeg.o diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c new file mode 100644 index 000000000000..30f4352e257d --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2L Port Output Enable for GPT (POEG) driver + * + * Copyright (C) 2022 Renesas Electronics Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define POEGG_SSF BIT(3) + +#define RZG2L_POEG_MAX_INDEX 3 + +#define RZG2L_GPT_MAX_HW_CHANNELS 8 +#define RZG2L_GPT_INVALID_CHANNEL 0xff + +struct rzg2l_poeg_chip { + struct device *gpt_dev; + struct reset_control *rstc; + void __iomem *mmio; + u8 index; + u8 gpt_channels[RZG2L_GPT_MAX_HW_CHANNELS]; +}; + +static const char * const rzg2l_gpt_pins[] = { + "gpt0-pins", + "gpt1-pins", + "gpt2-pins", + "gpt3-pins", + "gpt4-pins", + "gpt5-pins", + "gpt6-pins", + "gpt7-pins", +}; + +static void rzg2l_poeg_write(struct rzg2l_poeg_chip *chip, u32 data) +{ + iowrite32(data, chip->mmio); +} + +static u32 rzg2l_poeg_read(struct rzg2l_poeg_chip *chip) +{ + return ioread32(chip->mmio); +} + +static int rzg2l_poeg_output_disable_user(struct rzg2l_poeg_chip *chip, + bool enable) +{ + u32 reg_val; + + reg_val = rzg2l_poeg_read(chip); + if (enable) + reg_val |= POEGG_SSF; + else + reg_val &= ~POEGG_SSF; + + rzg2l_poeg_write(chip, reg_val); + + return 0; +} + +static int rzg2l_poeg_cb(void *context, const char *fname, const char *gname, + enum pin_output_disable_conf conf, + unsigned int conf_val) +{ + bool pin_match = false; + int ret, i; + + for (i = 0; i < RZG2L_GPT_MAX_HW_CHANNELS; i++) { + if ((!strcmp(rzg2l_gpt_pins[i], fname)) && + (!strcmp(rzg2l_gpt_pins[i], gname))) { + pin_match = true; + break; + } + } + + if (!pin_match) + return -EINVAL; + + switch (conf) { + case PINCTRL_OUTPUT_DISABLE_BY_USER: + ret = rzg2l_poeg_output_disable_user(context, !!conf_val); + break; + case PINCTRL_OUTPUT_DISABLE_BY_SOC_ON_PIN_OUTPUT_HIGH: + case PINCTRL_OUTPUT_DISABLE_BY_SOC_ON_PIN_OUTPUT_LOW: + case PINCTRL_OUTPUT_DISABLE_BY_SOC_ON_DEAD_TIME_ERROR: + default: + return -EINVAL; + } + + return ret; +} + +static bool rzg2l_poeg_get_linked_gpt_channels(struct platform_device *pdev, + struct rzg2l_poeg_chip *chip, + struct device_node *gpt_np, + u8 poeg_id) +{ + struct of_phandle_args of_args; + bool ret = false; + unsigned int i; + u32 poeg_grp; + int cells; + int err; + + cells = of_property_count_u32_elems(gpt_np, "renesas,poegs"); + if (cells == -EINVAL) + return ret; + + for (i = 0 ; i < RZG2L_GPT_MAX_HW_CHANNELS; i++) + chip->gpt_channels[i] = RZG2L_GPT_INVALID_CHANNEL; + + cells >>= 1; + for (i = 0; i < cells; i++) { + err = of_parse_phandle_with_fixed_args(gpt_np, + "renesas,poegs", 1, i, + &of_args); + if (err) { + dev_err(&pdev->dev, + "Failed to parse 'renesas,poegs' property\n"); + break; + } + + if (of_args.args[0] >= RZG2L_GPT_MAX_HW_CHANNELS) { + dev_err(&pdev->dev, "Invalid channel %d >= %d\n", + of_args.args[0], RZG2L_GPT_MAX_HW_CHANNELS); + of_node_put(of_args.np); + break; + } + + if (!of_property_read_u32(of_args.np, "renesas,poeg-id", &poeg_grp)) { + if (poeg_grp == poeg_id) { + chip->gpt_channels[poeg_grp] = poeg_id; + ret = true; + } + } + + of_node_put(of_args.np); + } + + return ret; +} + +static const struct of_device_id rzg2l_poeg_of_table[] = { + { .compatible = "renesas,rzg2l-poeg", }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg2l_poeg_of_table); + +static void rzg2l_poeg_cleanup(void *data) +{ + struct rzg2l_poeg_chip *chip = data; + + put_device(chip->gpt_dev); +} + +static int rzg2l_poeg_probe(struct platform_device *pdev) +{ + struct platform_device *gpt_pdev = NULL; + struct rzg2l_poeg_chip *chip; + bool gpt_linked = false; + struct device_node *np; + u32 val; + int ret; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + if (!of_property_read_u32(pdev->dev.of_node, "renesas,poeg-id", &val)) + chip->index = val; + + if (chip->index > RZG2L_POEG_MAX_INDEX) + return -EINVAL; + + np = of_parse_phandle(pdev->dev.of_node, "renesas,gpt", 0); + if (np) + gpt_pdev = of_find_device_by_node(np); + + gpt_linked = rzg2l_poeg_get_linked_gpt_channels(pdev, chip, np, + chip->index); + of_node_put(np); + if (!gpt_pdev) + return -ENODEV; + + chip->gpt_dev = &gpt_pdev->dev; + ret = devm_add_action_or_reset(&pdev->dev, + rzg2l_poeg_cleanup, chip); + if (ret < 0) + return ret; + + chip->mmio = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(chip->mmio)) + return PTR_ERR(chip->mmio); + + if (gpt_linked) + rzg2l_output_disable_cb_register(chip->gpt_dev, + rzg2l_poeg_cb, chip); + + chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(chip->rstc)) + return dev_err_probe(&pdev->dev, PTR_ERR(chip->rstc), + "get reset failed\n"); + + ret = reset_control_deassert(chip->rstc); + if (ret) + return ret; + + platform_set_drvdata(pdev, chip); + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); + goto err_pm_disable; + } + + return 0; + +err_pm_disable: + pm_runtime_disable(&pdev->dev); + reset_control_assert(chip->rstc); + return ret; +} + +static int rzg2l_poeg_remove(struct platform_device *pdev) +{ + struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev); + + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + reset_control_assert(chip->rstc); + + return 0; +} + +static struct platform_driver rzg2l_poeg_driver = { + .driver = { + .name = "rzg2l-poeg", + .of_match_table = of_match_ptr(rzg2l_poeg_of_table), + }, + .probe = rzg2l_poeg_probe, + .remove = rzg2l_poeg_remove, +}; +module_platform_driver(rzg2l_poeg_driver); + +MODULE_AUTHOR("Biju Das "); +MODULE_DESCRIPTION("Renesas RZ/G2L POEG Driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Mar 6 09:00:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1752248 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4PVXcB1RpJz246K for ; Mon, 6 Mar 2023 20:00:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229800AbjCFJA4 (ORCPT ); Mon, 6 Mar 2023 04:00:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229776AbjCFJAy (ORCPT ); Mon, 6 Mar 2023 04:00:54 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 50EDD222E4; Mon, 6 Mar 2023 01:00:48 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.98,236,1673881200"; d="scan'208";a="154992599" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Mar 2023 18:00:46 +0900 Received: from localhost.localdomain (unknown [10.226.93.39]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8BCB641C9BB5; Mon, 6 Mar 2023 18:00:43 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v6 07/13] pwm: rzg2l-gpt: Add support for output disable request from gpt Date: Mon, 6 Mar 2023 09:00:08 +0000 Message-Id: <20230306090014.128732-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> References: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org When dead time error occurs or the GTIOCA pin output value is the same as the GTIOCB pin output value, output protection is required. GPT detects this condition and generates output disable requests to POEG based on the settings in the output disable request permission bits, such as GTINTAD.GRPDTE, GTINTAD.GRPABH, GTINTAD.GRPABL. After the POEG receives output disable requests from each channel and calculates external input using an OR operation, the POEG generates output disable requests to GPT. This patch adds support for output disable request from gpt, when same time output level is high. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 111 ++++++++++++++++++++++++++++++++++ include/linux/pwm/rzg2l-gpt.h | 32 ++++++++++ 2 files changed, 143 insertions(+) create mode 100644 include/linux/pwm/rzg2l-gpt.h diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 9f3e2f7635a8..2f138e95f752 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -32,6 +33,7 @@ #define RZG2L_GTUDDTYC 0x30 #define RZG2L_GTIOR 0x34 #define RZG2L_GTINTAD 0x38 +#define RZG2L_GTST 0x3c #define RZG2L_GTBER 0x40 #define RZG2L_GTCNT 0x48 #define RZG2L_GTCCRA 0x4c @@ -72,6 +74,12 @@ (FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) | RZG2L_GTIOR_OBE) #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) + +#define RZG2L_GTST_OABHF BIT(29) +#define RZG2L_GTST_OABLF BIT(30) + +#define RZG2L_GTST_POEG_IRQ_MASK GENMASK(30, 28) #define RZG2L_GTCCR(i) (0x4c + 4 * (i)) @@ -431,6 +439,109 @@ static DEFINE_RUNTIME_DEV_PM_OPS(rzg2l_gpt_pm_ops, rzg2l_gpt_pm_runtime_suspend, rzg2l_gpt_pm_runtime_resume, NULL); +u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 val = 0; + u32 offs; + u32 reg; + + rzg2l_gpt = dev_get_drvdata(dev); + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + val <<= 3; + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + reg = rzg2l_gpt_read(rzg2l_gpt, offs + RZG2L_GTST); + val |= FIELD_GET(RZG2L_GTST_POEG_IRQ_MASK, reg); + } + + return val; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_irq_status); + +int rzg2l_gpt_poeg_disable_req_clr(void *dev, u8 grp) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 offs; + u32 reg; + + rzg2l_gpt = dev_get_drvdata(dev); + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + reg = rzg2l_gpt_read(rzg2l_gpt, offs + RZG2L_GTST); + + if (reg & (RZG2L_GTST_OABHF | RZG2L_GTST_OABLF)) + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR, + RZG2L_GTIOR_OBE, 0); + } + + return 0; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_clr); + +int rzg2l_gpt_pin_reenable(void *dev, u8 grp) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 offs; + + rzg2l_gpt = dev_get_drvdata(dev); + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR, + RZG2L_GTIOR_OBE, RZG2L_GTIOR_OBE); + } + return 0; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_pin_reenable); + +static int rzg2l_gpt_poeg_disable_req_endisable(void *dev, u8 grp, int op, bool on) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 offs; + + rzg2l_gpt = dev_get_drvdata(dev); + pm_runtime_get_sync(dev); + + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + if (on) + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD, op, op); + else + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD, op, 0); + } + + pm_runtime_put(dev); + + return 0; +} + +int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8 grp, bool on) +{ + int id = RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high); + static void rzg2l_gpt_reset_assert_pm_disable(void *data) { struct rzg2l_gpt_chip *rzg2l_gpt = data; diff --git a/include/linux/pwm/rzg2l-gpt.h b/include/linux/pwm/rzg2l-gpt.h new file mode 100644 index 000000000000..0fc13ab57420 --- /dev/null +++ b/include/linux/pwm/rzg2l-gpt.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_PWM_RZG2L_GPT_H__ +#define __LINUX_PWM_RZG2L_GPT_H__ + +#if IS_ENABLED(CONFIG_PWM_RZG2L_GPT) +u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp); +int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp); +int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); +int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on); +#else +static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) +{ + return -ENODEV; +} + +static inline int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp) +{ + return -ENODEV; +} + +static inline int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp) +{ + return -ENODEV; +} + +static inline int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on) +{ + return -ENODEV; +} +#endif + +#endif /* __LINUX_PWM_RZG2L_GPT_H__ */ From patchwork Mon Mar 6 09:00:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1752250 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4PVXcC13mNz246K for ; Mon, 6 Mar 2023 20:00:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229712AbjCFJA6 (ORCPT ); Mon, 6 Mar 2023 04:00:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229843AbjCFJAz (ORCPT ); Mon, 6 Mar 2023 04:00:55 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8564F83FA; Mon, 6 Mar 2023 01:00:50 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.98,236,1673881200"; d="scan'208";a="154992617" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Mar 2023 18:00:50 +0900 Received: from localhost.localdomain (unknown [10.226.93.39]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2FD4941C9BA3; Mon, 6 Mar 2023 18:00:46 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v6 08/13] pinctrl: renesas: rzg2l-poeg: Add support for GPT Output-Disable Request Date: Mon, 6 Mar 2023 09:00:09 +0000 Message-Id: <20230306090014.128732-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> References: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch supports output-disable requests from GPT. Added sysfs to enable/disable request from GPT when both outputs are high. When both outputs are high, gpt detects the condition and triggers an interrupt to POEG. POEG handles the interrupt and send notification to userspace. userspace handles the fault and issue a write call to cancel the disable output request. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 206 +++++++++++++++++++++- include/linux/pinctrl/pinctrl-rzg2l.h | 9 + 2 files changed, 212 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c index 30f4352e257d..b6f01065c058 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -4,27 +4,45 @@ * * Copyright (C) 2022 Renesas Electronics Corporation */ +#include +#include #include +#include #include #include #include #include #include #include +#include +#include #include +#include +#define POEGG_IOCE BIT(5) +#define POEGG_PIDE BIT(4) #define POEGG_SSF BIT(3) +#define POEGG_IOCF BIT(1) +#define POEGG_PIDF BIT(0) #define RZG2L_POEG_MAX_INDEX 3 #define RZG2L_GPT_MAX_HW_CHANNELS 8 #define RZG2L_GPT_INVALID_CHANNEL 0xff +static struct class *poeg_class; +static dev_t g_poeg_dev; +static int minor_n; + struct rzg2l_poeg_chip { struct device *gpt_dev; struct reset_control *rstc; void __iomem *mmio; u8 index; + DECLARE_BITMAP(gpt_irq, 3); + struct cdev poeg_cdev; + wait_queue_head_t events_wait; + DECLARE_KFIFO_PTR(events, struct poeg_event); u8 gpt_channels[RZG2L_GPT_MAX_HW_CHANNELS]; }; @@ -65,6 +83,20 @@ static int rzg2l_poeg_output_disable_user(struct rzg2l_poeg_chip *chip, return 0; } +static int rzg2l_poeg_output_disable_both_high(struct rzg2l_poeg_chip *chip, + bool enable) +{ + if (enable) + set_bit(RZG2L_GPT_OABHF, chip->gpt_irq); + else + clear_bit(RZG2L_GPT_OABHF, chip->gpt_irq); + + rzg2l_gpt_poeg_disable_req_both_high(chip->gpt_dev, chip->index, + test_bit(RZG2L_GPT_OABHF, chip->gpt_irq)); + + return 0; +} + static int rzg2l_poeg_cb(void *context, const char *fname, const char *gname, enum pin_output_disable_conf conf, unsigned int conf_val) @@ -88,6 +120,8 @@ static int rzg2l_poeg_cb(void *context, const char *fname, const char *gname, ret = rzg2l_poeg_output_disable_user(context, !!conf_val); break; case PINCTRL_OUTPUT_DISABLE_BY_SOC_ON_PIN_OUTPUT_HIGH: + ret = rzg2l_poeg_output_disable_both_high(context, !!conf_val); + break; case PINCTRL_OUTPUT_DISABLE_BY_SOC_ON_PIN_OUTPUT_LOW: case PINCTRL_OUTPUT_DISABLE_BY_SOC_ON_DEAD_TIME_ERROR: default: @@ -97,6 +131,111 @@ static int rzg2l_poeg_cb(void *context, const char *fname, const char *gname, return ret; } +static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) +{ + struct rzg2l_poeg_chip *chip = ptr; + struct poeg_event ev; + u32 val; + + val = rzg2l_gpt_poeg_disable_req_irq_status(chip->gpt_dev, chip->index); + ev.channel = chip->index; + ev.gpt_disable_irq_status = val; + kfifo_in(&chip->events, &ev, 1); + wake_up_poll(&chip->events_wait, EPOLLIN); + + val = rzg2l_poeg_read(chip); + if (val & POEGG_IOCF) + val &= ~POEGG_IOCF; + + if (val & POEGG_PIDF) + val &= ~POEGG_PIDF; + + rzg2l_poeg_write(chip, val); + rzg2l_gpt_poeg_disable_req_clr(chip->gpt_dev, chip->index); + + return IRQ_HANDLED; +} + +static __poll_t rzg2l_poeg_chrdev_poll(struct file *filp, + struct poll_table_struct *pollt) +{ + struct rzg2l_poeg_chip *const chip = filp->private_data; + __poll_t events = 0; + + poll_wait(filp, &chip->events_wait, pollt); + if (!kfifo_is_empty(&chip->events)) + events = EPOLLIN | EPOLLRDNORM; + + return events; +} + +static ssize_t rzg2l_poeg_chrdev_read(struct file *filp, char __user *buf, + size_t len, loff_t *f_ps) +{ + struct rzg2l_poeg_chip *const chip = filp->private_data; + unsigned int copied; + int err; + + if (len < sizeof(struct poeg_event)) + return -EINVAL; + + do { + if (kfifo_is_empty(&chip->events)) { + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + + err = wait_event_interruptible(chip->events_wait, + !kfifo_is_empty(&chip->events)); + if (err < 0) + return err; + } + + err = kfifo_to_user(&chip->events, buf, len, &copied); + if (err < 0) + return err; + } while (!copied); + + return copied; +} + +static ssize_t rzg2l_poeg_chrdev_write(struct file *filp, + const char __user *buf, + size_t len, loff_t *f_ps) +{ + struct rzg2l_poeg_chip *const chip = filp->private_data; + + rzg2l_gpt_pin_reenable(chip->gpt_dev, chip->index); + + return len; +} + +static int rzg2l_poeg_chrdev_open(struct inode *inode, struct file *filp) +{ + struct rzg2l_poeg_chip *const chip = container_of(inode->i_cdev, + typeof(*chip), + poeg_cdev); + + filp->private_data = chip; + + return nonseekable_open(inode, filp); +} + +static int rzg2l_poeg_chrdev_release(struct inode *inode, struct file *filp) +{ + filp->private_data = NULL; + + return 0; +} + +static const struct file_operations poeg_fops = { + .owner = THIS_MODULE, + .read = rzg2l_poeg_chrdev_read, + .write = rzg2l_poeg_chrdev_write, + .poll = rzg2l_poeg_chrdev_poll, + .open = rzg2l_poeg_chrdev_open, + .release = rzg2l_poeg_chrdev_release, +}; + static bool rzg2l_poeg_get_linked_gpt_channels(struct platform_device *pdev, struct rzg2l_poeg_chip *chip, struct device_node *gpt_np, @@ -168,6 +307,7 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) struct device_node *np; u32 val; int ret; + int irq; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) @@ -199,10 +339,20 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) if (IS_ERR(chip->mmio)) return PTR_ERR(chip->mmio); - if (gpt_linked) + if (gpt_linked) { rzg2l_output_disable_cb_register(chip->gpt_dev, rzg2l_poeg_cb, chip); + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_irq(&pdev->dev, irq, rzg2l_poeg_irq, 0, + dev_name(&pdev->dev), chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "cannot get irq\n"); + } + chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(chip->rstc)) return dev_err_probe(&pdev->dev, PTR_ERR(chip->rstc), @@ -220,8 +370,24 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) goto err_pm_disable; } - return 0; + if (gpt_linked) + rzg2l_poeg_write(chip, POEGG_IOCE | POEGG_PIDE); + + init_waitqueue_head(&chip->events_wait); + cdev_init(&chip->poeg_cdev, &poeg_fops); + chip->poeg_cdev.owner = THIS_MODULE; + ret = cdev_add(&chip->poeg_cdev, MKDEV(MAJOR(g_poeg_dev), minor_n), 1); + if (ret) + goto err_pm; + + device_create(poeg_class, NULL, MKDEV(MAJOR(g_poeg_dev), minor_n), + NULL, "poeg%d", minor_n); + minor_n++; + + return kfifo_alloc(&chip->events, 64, GFP_KERNEL); +err_pm: + pm_runtime_put(&pdev->dev); err_pm_disable: pm_runtime_disable(&pdev->dev); reset_control_assert(chip->rstc); @@ -232,6 +398,10 @@ static int rzg2l_poeg_remove(struct platform_device *pdev) { struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev); + kfifo_free(&chip->events); + device_destroy(poeg_class, + MKDEV(MAJOR(g_poeg_dev), MINOR(chip->poeg_cdev.dev))); + cdev_del(&chip->poeg_cdev); pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); reset_control_assert(chip->rstc); @@ -247,7 +417,37 @@ static struct platform_driver rzg2l_poeg_driver = { .probe = rzg2l_poeg_probe, .remove = rzg2l_poeg_remove, }; -module_platform_driver(rzg2l_poeg_driver); + +static int rzg2l_poeg_device_init(void) +{ + int err; + + err = alloc_chrdev_region(&g_poeg_dev, 0, 1, "poeg"); + if (err) + goto out; + + poeg_class = class_create(THIS_MODULE, "poeg"); + if (IS_ERR(poeg_class)) { + err = PTR_ERR(poeg_class); + goto err_free_chrdev; + } + + return platform_driver_register(&rzg2l_poeg_driver); + +err_free_chrdev: + unregister_chrdev_region(g_poeg_dev, 1); +out: + return err; +} + +static void rzg2l_poeg_device_exit(void) +{ + class_destroy(poeg_class); + unregister_chrdev_region(g_poeg_dev, 1); +} + +module_init(rzg2l_poeg_device_init); +module_exit(rzg2l_poeg_device_exit); MODULE_AUTHOR("Biju Das "); MODULE_DESCRIPTION("Renesas RZ/G2L POEG Driver"); diff --git a/include/linux/pinctrl/pinctrl-rzg2l.h b/include/linux/pinctrl/pinctrl-rzg2l.h index a49b4c5f8908..94d1b12d84c8 100644 --- a/include/linux/pinctrl/pinctrl-rzg2l.h +++ b/include/linux/pinctrl/pinctrl-rzg2l.h @@ -4,6 +4,15 @@ #include +#define RZG2L_GPT_DTEF 0 +#define RZG2L_GPT_OABHF 1 +#define RZG2L_GPT_OABLF 2 + +struct poeg_event { + __u32 gpt_disable_irq_status; + __u8 channel; +}; + typedef int (*output_disable_cb) (void *context, const char *fname, const char *gname, From patchwork Mon Mar 6 09:00:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1752252 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4PVXcD4pWVz246K for ; Mon, 6 Mar 2023 20:01:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229767AbjCFJBA (ORCPT ); Mon, 6 Mar 2023 04:01:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229687AbjCFJA6 (ORCPT ); Mon, 6 Mar 2023 04:00:58 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 280A3222DE; Mon, 6 Mar 2023 01:00:54 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.98,236,1673881200"; d="scan'208";a="151662817" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 06 Mar 2023 18:00:53 +0900 Received: from localhost.localdomain (unknown [10.226.93.39]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id CE2C641C9E84; Mon, 6 Mar 2023 18:00:50 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v6 09/13] pwm: rzg2l-gpt: Add support for output disable when both output low Date: Mon, 6 Mar 2023 09:00:10 +0000 Message-Id: <20230306090014.128732-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> References: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support for output disable request from gpt, when same time output level is low. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 9 +++++++++ include/linux/pwm/rzg2l-gpt.h | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 2f138e95f752..2291cc3cff39 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -75,6 +75,7 @@ #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW BIT(30) #define RZG2L_GTST_OABHF BIT(29) #define RZG2L_GTST_OABLF BIT(30) @@ -542,6 +543,14 @@ int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8 grp, bool on) } EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high); +int rzg2l_gpt_poeg_disable_req_both_low(void *dev, u8 grp, bool on) +{ + int id = RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_low); + static void rzg2l_gpt_reset_assert_pm_disable(void *data) { struct rzg2l_gpt_chip *rzg2l_gpt = data; diff --git a/include/linux/pwm/rzg2l-gpt.h b/include/linux/pwm/rzg2l-gpt.h index 0fc13ab57420..592bc2900c9e 100644 --- a/include/linux/pwm/rzg2l-gpt.h +++ b/include/linux/pwm/rzg2l-gpt.h @@ -7,6 +7,7 @@ u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp); int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp); int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on); +int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on); #else static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) { @@ -27,6 +28,11 @@ static inline int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, { return -ENODEV; } + +static inline int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on) +{ + return -ENODEV; +} #endif #endif /* __LINUX_PWM_RZG2L_GPT_H__ */ From patchwork Mon Mar 6 09:00:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1752254 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4PVXcJ3mvkz246K for ; Mon, 6 Mar 2023 20:01:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229813AbjCFJBE (ORCPT ); Mon, 6 Mar 2023 04:01:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229843AbjCFJBD (ORCPT ); Mon, 6 Mar 2023 04:01:03 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 272BFE077; Mon, 6 Mar 2023 01:00:58 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.98,236,1673881200"; d="scan'208";a="151662829" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 06 Mar 2023 18:00:57 +0900 Received: from localhost.localdomain (unknown [10.226.93.39]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6D3A841C869B; Mon, 6 Mar 2023 18:00:54 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v6 10/13] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT when both outputs are low. Date: Mon, 6 Mar 2023 09:00:11 +0000 Message-Id: <20230306090014.128732-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> References: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support fpr output-disable requests from GPT, when both outputs are low. Added sysfs to enable/disable for configuring GPT output disable request when both outputs are low. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c index b6f01065c058..bbca21557a70 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -97,6 +97,20 @@ static int rzg2l_poeg_output_disable_both_high(struct rzg2l_poeg_chip *chip, return 0; } +static int rzg2l_poeg_output_disable_both_low(struct rzg2l_poeg_chip *chip, + bool enable) +{ + if (enable) + set_bit(RZG2L_GPT_OABLF, chip->gpt_irq); + else + clear_bit(RZG2L_GPT_OABLF, chip->gpt_irq); + + rzg2l_gpt_poeg_disable_req_both_low(chip->gpt_dev, chip->index, + test_bit(RZG2L_GPT_OABLF, chip->gpt_irq)); + + return 0; +} + static int rzg2l_poeg_cb(void *context, const char *fname, const char *gname, enum pin_output_disable_conf conf, unsigned int conf_val) @@ -123,6 +137,8 @@ static int rzg2l_poeg_cb(void *context, const char *fname, const char *gname, ret = rzg2l_poeg_output_disable_both_high(context, !!conf_val); break; case PINCTRL_OUTPUT_DISABLE_BY_SOC_ON_PIN_OUTPUT_LOW: + ret = rzg2l_poeg_output_disable_both_low(context, !!conf_val); + break; case PINCTRL_OUTPUT_DISABLE_BY_SOC_ON_DEAD_TIME_ERROR: default: return -EINVAL; From patchwork Mon Mar 6 09:00:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1752256 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4PVXcT5tw2z246K for ; Mon, 6 Mar 2023 20:01:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229854AbjCFJBM (ORCPT ); Mon, 6 Mar 2023 04:01:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229865AbjCFJBK (ORCPT ); Mon, 6 Mar 2023 04:01:10 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7F0CD222FD; Mon, 6 Mar 2023 01:01:02 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.98,236,1673881200"; d="scan'208";a="154992671" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Mar 2023 18:01:01 +0900 Received: from localhost.localdomain (unknown [10.226.93.39]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 0B6EC41C869B; Mon, 6 Mar 2023 18:00:57 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v6 11/13] pwm: rzg2l-gpt: Add support for output disable on dead time error Date: Mon, 6 Mar 2023 09:00:12 +0000 Message-Id: <20230306090014.128732-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> References: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support for output disable request from gpt, when dead time error occurred. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 9 +++++++++ include/linux/pwm/rzg2l-gpt.h | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 2291cc3cff39..c88a5bf9e31d 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -74,6 +74,7 @@ (FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) | RZG2L_GTIOR_OBE) #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_DEADTIME_ERROR BIT(28) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW BIT(30) @@ -551,6 +552,14 @@ int rzg2l_gpt_poeg_disable_req_both_low(void *dev, u8 grp, bool on) } EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_low); +int rzg2l_gpt_poeg_disable_req_deadtime_error(void *dev, u8 grp, bool on) +{ + int id = RZG2L_GTINTAD_OUTPUT_DISABLE_DEADTIME_ERROR; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_deadtime_error); + static void rzg2l_gpt_reset_assert_pm_disable(void *data) { struct rzg2l_gpt_chip *rzg2l_gpt = data; diff --git a/include/linux/pwm/rzg2l-gpt.h b/include/linux/pwm/rzg2l-gpt.h index 592bc2900c9e..8a004c690c2a 100644 --- a/include/linux/pwm/rzg2l-gpt.h +++ b/include/linux/pwm/rzg2l-gpt.h @@ -8,6 +8,7 @@ int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp); int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on); int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on); +int rzg2l_gpt_poeg_disable_req_deadtime_error(void *gpt_device, u8 grp, bool on); #else static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) { @@ -33,6 +34,11 @@ static inline int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, { return -ENODEV; } + +static inline int rzg2l_gpt_poeg_disable_req_deadtime_err(void *gpt_device, u8 grp, bool on) +{ + return -ENODEV; +} #endif #endif /* __LINUX_PWM_RZG2L_GPT_H__ */ From patchwork Mon Mar 6 09:00:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1752260 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4PVXcg1Mrsz246K for ; Mon, 6 Mar 2023 20:01:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229834AbjCFJBV (ORCPT ); Mon, 6 Mar 2023 04:01:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229650AbjCFJBU (ORCPT ); Mon, 6 Mar 2023 04:01:20 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 04FF7222F6; Mon, 6 Mar 2023 01:01:09 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.98,236,1673881200"; d="scan'208";a="154992695" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Mar 2023 18:01:04 +0900 Received: from localhost.localdomain (unknown [10.226.93.39]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id A7DD041CA0C8; Mon, 6 Mar 2023 18:01:01 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v6 12/13] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT on dead time error Date: Mon, 6 Mar 2023 09:00:13 +0000 Message-Id: <20230306090014.128732-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> References: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support for output-disable requests from GPT, when dead time error occurs. Added sysfs to enable/disable for configuring GPT output disable request for dead time error. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c index bbca21557a70..3d0801d8937a 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -111,6 +111,20 @@ static int rzg2l_poeg_output_disable_both_low(struct rzg2l_poeg_chip *chip, return 0; } +static int rzg2l_poeg_output_disable_deadtime_err(struct rzg2l_poeg_chip *chip, + bool enable) +{ + if (enable) + set_bit(RZG2L_GPT_DTEF, chip->gpt_irq); + else + clear_bit(RZG2L_GPT_DTEF, chip->gpt_irq); + + rzg2l_gpt_poeg_disable_req_deadtime_error(chip->gpt_dev, chip->index, + test_bit(RZG2L_GPT_DTEF, chip->gpt_irq)); + + return 0; +} + static int rzg2l_poeg_cb(void *context, const char *fname, const char *gname, enum pin_output_disable_conf conf, unsigned int conf_val) @@ -140,6 +154,8 @@ static int rzg2l_poeg_cb(void *context, const char *fname, const char *gname, ret = rzg2l_poeg_output_disable_both_low(context, !!conf_val); break; case PINCTRL_OUTPUT_DISABLE_BY_SOC_ON_DEAD_TIME_ERROR: + ret = rzg2l_poeg_output_disable_deadtime_err(context, !!conf_val); + break; default: return -EINVAL; } From patchwork Mon Mar 6 09:00:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1752258 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4PVXcf2XT2z246K for ; Mon, 6 Mar 2023 20:01:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229797AbjCFJBV (ORCPT ); Mon, 6 Mar 2023 04:01:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229619AbjCFJBU (ORCPT ); Mon, 6 Mar 2023 04:01:20 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 51371227A8; Mon, 6 Mar 2023 01:01:09 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.98,236,1673881200"; d="scan'208";a="151662877" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 06 Mar 2023 18:01:08 +0900 Received: from localhost.localdomain (unknown [10.226.93.39]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 775C241C9E84; Mon, 6 Mar 2023 18:01:05 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v6 13/13] tools/poeg: Add test app for poeg Date: Mon, 6 Mar 2023 09:00:14 +0000 Message-Id: <20230306090014.128732-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> References: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add test app for poeg Signed-off-by: Biju Das --- tools/poeg/Build | 1 + tools/poeg/Makefile | 53 ++++++++++++++++++++++++++++++++++++++ tools/poeg/poeg_app.c | 60 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+) create mode 100644 tools/poeg/Build create mode 100644 tools/poeg/Makefile create mode 100644 tools/poeg/poeg_app.c diff --git a/tools/poeg/Build b/tools/poeg/Build new file mode 100644 index 000000000000..f960920a4afb --- /dev/null +++ b/tools/poeg/Build @@ -0,0 +1 @@ +poeg_app-y += poeg_app.o diff --git a/tools/poeg/Makefile b/tools/poeg/Makefile new file mode 100644 index 000000000000..6946e6956215 --- /dev/null +++ b/tools/poeg/Makefile @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +include ../scripts/Makefile.include + +bindir ?= /usr/bin + +ifeq ($(srctree),) +srctree := $(patsubst %/,%,$(dir $(CURDIR))) +srctree := $(patsubst %/,%,$(dir $(srctree))) +endif + +# Do not use make's built-in rules +# (this improves performance and avoids hard-to-debug behaviour); +MAKEFLAGS += -r + +override CFLAGS += -O2 -Wall -g -D_GNU_SOURCE -I$(OUTPUT)include + +ALL_TARGETS := poeg_app +ALL_PROGRAMS := $(patsubst %,$(OUTPUT)%,$(ALL_TARGETS)) + +all: $(ALL_PROGRAMS) + +export srctree OUTPUT CC LD CFLAGS +include $(srctree)/tools/build/Makefile.include + +# +# We need the following to be outside of kernel tree +# +$(OUTPUT)include/linux/poeg.h: ../../include/linux/soc/renesas/rzg2l-poeg.h + mkdir -p $(OUTPUT)include/linux 2>&1 || true + ln -sf $(CURDIR)/../../include/linux/soc/renesas/rzg2l-poeg.h $@ + +prepare: $(OUTPUT)include/linux/poeg.h + +COUNTER_EXAMPLE := $(OUTPUT)poeg_app.o +$(COUNTER_EXAMPLE): prepare FORCE + $(Q)$(MAKE) $(build)=poeg_app +$(OUTPUT)poeg_app: $(COUNTER_EXAMPLE) + $(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) $< -o $@ + +clean: + rm -f $(ALL_PROGRAMS) + rm -rf $(OUTPUT)include/linux/counter.h + find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete + +install: $(ALL_PROGRAMS) + install -d -m 755 $(DESTDIR)$(bindir); \ + for program in $(ALL_PROGRAMS); do \ + install $$program $(DESTDIR)$(bindir); \ + done + +FORCE: + +.PHONY: all install clean FORCE prepare diff --git a/tools/poeg/poeg_app.c b/tools/poeg/poeg_app.c new file mode 100644 index 000000000000..79cacb8c60c5 --- /dev/null +++ b/tools/poeg/poeg_app.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * POEG - example userspace application + * Copyright (C) 2022 Biju Das + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +int main(int argc, char *arg[]) +{ + struct poeg_event event_data; + unsigned int val; + int ret, fd, i; + + fd = open("/dev/poeg3", O_RDWR); + if (fd < 0) + perror("open"); + else + printf("[POEG]open\n"); + + for (;;) { + ret = read(fd, &event_data, sizeof(event_data)); + if (ret == -1) { + perror("Failed to read event data"); + return 1; + } + + val = event_data.gpt_disable_irq_status; + if (val) { + /* emulate fault clearing condition by adding delay */ + sleep(2); + for (i = 0; i < 8; i++) { + if (val & 7) { + printf("gpt ch:%u, irq=%x\n", i, val & 7); + ret = write(fd, &event_data, sizeof(event_data)); + } + val >>= 3; + } + } + } + + if (close(fd) != 0) + perror("close"); + else + printf("[POEG]close\n"); + + return 0; +}