From patchwork Wed Mar 1 23:47:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750260 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=D/SEhmsQ; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrKs4pFgz2460 for ; Thu, 2 Mar 2023 10:39:13 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrKs38JFz3cJY for ; Thu, 2 Mar 2023 10:39:13 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=D/SEhmsQ; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=D/SEhmsQ; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJV2GtCz3c41 for ; Thu, 2 Mar 2023 10:38:00 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713882; x=1709249882; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Lma7M0NQuejLahUyWUzCNBxEauMnVUBUBK0aoIXgw+I=; b=D/SEhmsQvUx0AAfVvwSKzRxOrHzsQ+w/rovYYsjHxmkvlhJOtId9Vd0L n+jDwjFuX7v44m9r+aDeNufR1UFLrW+f3iE/X9zf8psoRoRk5OCo88V3X IpAyYXq0wVwH9v+s6CqZtkDPo3nlzxKOEqKLWb4k+IauPunYfDCESJe1v 2VTG4dypP/HM944VfBCTrSgypl6raOn/P2SLDftYbY366wFne8nl4dtu+ 2serIvs/MFFujrNoL/f+0OeP3aJss00BvptFOsev2t63+TGbrlUa6pFHp xcLOttifxA+PSIFjzGEiuL+MIPSFNPBg2+znoN7ycLMAJBUiW/J6vLv8R A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818675" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818675" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826785" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826785" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:55 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 01/24] x86/apic: Add irq_cfg::delivery_mode Date: Wed, 1 Mar 2023 15:47:30 -0800 Message-Id: <20230301234753.28582-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" There are no restrictions in hardware to configure the delivery mode of each interrupt individually. Also, certain interrupts need to be configured with a specific delivery mode (e.g., non-maskable interrupts). Add a new member, delivery_mode, to struct irq_cfg to this effect. To keep the current behavior, use the delivery mode of the APIC driver when allocating a vector for an interrupt in the root domain (i.e., x86_vector_domain). Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Ashok Raj Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Reworded the commit message to accurately state that the root domain allocates a vector for an interrupt, not an interrupt. (Thomas) * Removed stray newline. (Thomas) * Replaced 'irq' with 'interrupt' in the changelog and in the code. (Thomas). Changes since v5: * Updated indentation of the existing members of struct irq_cfg. * Reworded the commit message. Changes since v4: * Rebased to use new enumeration apic_delivery_modes. Changes since v3: * None Changes since v2: * Reduced scope to only add the interrupt delivery mode in struct irq_alloc_info. Changes since v1: * Introduced this patch. --- arch/x86/include/asm/hw_irq.h | 5 +++-- arch/x86/kernel/apic/vector.c | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h index d465ece58151..5ac5e6c603ee 100644 --- a/arch/x86/include/asm/hw_irq.h +++ b/arch/x86/include/asm/hw_irq.h @@ -88,8 +88,9 @@ struct irq_alloc_info { }; struct irq_cfg { - unsigned int dest_apicid; - unsigned int vector; + unsigned int dest_apicid; + unsigned int vector; + enum apic_delivery_modes delivery_mode; }; extern struct irq_cfg *irq_cfg(unsigned int irq); diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index c1efebd27e6c..633b442c8f84 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -573,6 +573,12 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, /* Don't invoke affinity setter on deactivated interrupts */ irqd_set_affinity_on_activate(irqd); + /* + * A delivery mode may be specified in the interrupt allocation + * info. If not, use the delivery mode of the APIC. + */ + apicd->hw_irq_cfg.delivery_mode = apic->delivery_mode; + /* * Legacy vectors are already assigned when the IOAPIC * takes them over. They stay on the same vector. This is From patchwork Wed Mar 1 23:47:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750259 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=RkqbnzZE; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrJw04GGz2460 for ; Thu, 2 Mar 2023 10:38:23 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrJs0HhLz3cPg for ; Thu, 2 Mar 2023 10:38:21 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=RkqbnzZE; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=RkqbnzZE; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJV4sRNz3c4Y for ; Thu, 2 Mar 2023 10:38:02 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713882; x=1709249882; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=RjtAUFRJrzBKfA0+yFHKXNZopzCyfP9+J4w+QU7OMp8=; b=RkqbnzZEyg8YxkM8895UqwBEuXNsvdIlDe+2tyYWL/FVhUJvjUxG17lm tbmInyvVUP9Mn8pxJIO3Rf4/3xX1J5ZwtfQeenrZFvgP8hvjsXaapTGYY fQZ9CjBTJBN+Oo8aZL5UxmekxS4W101L0WawGJIuOGfrnuJ5oEkZnvMKb LiJjw99293rKACHJFFrKRRFo6y3H2wYgAcRfS5atrwZHEU2O3EZ2pUm60 Fpxx5NuziP8Feke0koHdBTiAOFzuGvCadPRdUwa2gSHZLvewP9BVRhe7l +O7cfAGTnremlnBd2yjwt/1AvRcG6ghegux+nzwrU1aWlYtUHbO6N5DDe w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818681" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818681" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826789" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826789" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:55 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 02/24] x86/apic/msi: Use the delivery mode from irq_cfg for message composition Date: Wed, 1 Mar 2023 15:47:31 -0800 Message-Id: <20230301234753.28582-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" irq_cfg provides a delivery mode for each interrupt. Use it instead of the hardcoded APIC_DELIVERY_MODE_FIXED. This allows to compose messages for NMI delivery mode which is required to implement a HPET- based NMI watchdog. No functional change as the default delivery mode is set to APIC_DELIVERY_MODE_FIXED. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Reworded changelog as per suggestion from Thomas. Changes since v5: * Introduced this patch Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- arch/x86/kernel/apic/apic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 20d9a604da7c..352738238e52 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2562,7 +2562,7 @@ void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical; msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF; - msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED; + msg->arch_data.delivery_mode = cfg->delivery_mode; msg->arch_data.vector = cfg->vector; msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; From patchwork Wed Mar 1 23:47:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750261 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=k3ieLHkQ; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrLs6PHLz1yWw for ; Thu, 2 Mar 2023 10:40:05 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrLs5T33z3cfS for ; Thu, 2 Mar 2023 10:40:05 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=k3ieLHkQ; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=k3ieLHkQ; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJW6QxRz3c4Y for ; Thu, 2 Mar 2023 10:38:03 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713884; x=1709249884; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=q1CqewxYyZYMIT/dLlB5/XAEQ5VVr9wg2syBU+4wkTk=; b=k3ieLHkQtwEVBKt7xXhWMk53+82mwTHoeCdth9dHHnEJ7Gm8fNyCT11I MHzgIhrawHx3kILZ9Ntzr8VsON8uwSct1d2cc97PvGm6Pkrij+QW/V0nR wub+V9WqoTajWLO8KK2ciZ1vG07a1h1Tbyzbb4DhbRDt6+KF6l7XOj+Xg i+iKOR6wP7x3Fl+rzWB/OcuMuUa15y9fr3J+pMnJVF40FBlicSRE1K6RA 1H3HdTUoMQfwDrfeyEmmpG1R1PfK533xFSzXkK5NSdZQ0opcmhJQUodk0 HAVoctyTLHREn3V0ToWVSHxcssppwmHOuQBy04Z9MTlgg0QN3dYHbY+hR Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818686" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818686" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826795" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826795" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:55 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 03/24] x86/apic: Add the X86_IRQ_ALLOC_AS_NMI interrupt allocation flag Date: Wed, 1 Mar 2023 15:47:32 -0800 Message-Id: <20230301234753.28582-4-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" There are cases in which it is necessary to set the delivery mode of an interrupt as NMI. Add a new flag that callers can specify when allocating an interrupt. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch. Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- arch/x86/include/asm/irqdomain.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/irqdomain.h b/arch/x86/include/asm/irqdomain.h index 30c325c235c0..e13f02c6fe95 100644 --- a/arch/x86/include/asm/irqdomain.h +++ b/arch/x86/include/asm/irqdomain.h @@ -8,6 +8,7 @@ #ifdef CONFIG_X86_LOCAL_APIC enum { X86_IRQ_ALLOC_LEGACY = 0x1, + X86_IRQ_ALLOC_AS_NMI = 0x2, }; extern int x86_fwspec_is_ioapic(struct irq_fwspec *fwspec); From patchwork Wed Mar 1 23:47:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750264 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=oBftd8+E; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrPx6R7yz1yXC for ; Thu, 2 Mar 2023 10:42:45 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrPx5JQ0z3f4k for ; Thu, 2 Mar 2023 10:42:45 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=oBftd8+E; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=oBftd8+E; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJX6Rqgz3c41 for ; Thu, 2 Mar 2023 10:38:04 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713885; x=1709249885; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=elKTscyLR7FY5NmvjkmQhnEbe/r3S/2u7x+nfhQMrvU=; b=oBftd8+EqHsO+4HzbaaW455zLifpLQb4QTdOTmOm+ysoEI5zGb9TwMkJ 5ICkcNfCynJQKPecPZC7yb1QUmqGLUFz+bkb3x2n/WZslCmz0c1Gg6Jhh L+BKt+e6y6YVAX7zQu9iFB1F4Z8JiwoMO/RToprHNA1JPDnfIlHRcQAVN 5jjHBPl6nPBfZDzvyrhli6FZhIQpBQZvgTR3p7uNErTlBru2VoRwOnxui gri3230/EYxcvd2muagPOeOzxqYKh7rmzhhbNJLTtHCx1sq7IrrzHfNCr Xwl0O9Y6EazM9kGNnZx1t/7wRj+q/KCC+jWtrGpABjmGU2prUoqdypiUs A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818691" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818691" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826798" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826798" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:56 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 04/24] x86/apic/vector: Implement a local APIC NMI controller Date: Wed, 1 Mar 2023 15:47:33 -0800 Message-Id: <20230301234753.28582-5-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Add a separate local APIC NMI controller to handle NMIs apart from the regular APIC management. This controller will be used to handle the NMI vector of the HPET NMI watchdog. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Thomas Gleixner Signed-off-by: Ricardo Neri --- Changes since v6: * Reworked patch "x86/apic/vector: Implement support for NMI delivery mode" into a separate local APIC NMI controller. (Thomas) Changes since v5: * Introduced this patch. Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- arch/x86/kernel/apic/vector.c | 57 +++++++++++++++++++++++++++++++++++ include/linux/irq.h | 5 +++ 2 files changed, 62 insertions(+) diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index 633b442c8f84..a4cf041427cb 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -42,6 +42,7 @@ EXPORT_SYMBOL_GPL(x86_vector_domain); static DEFINE_RAW_SPINLOCK(vector_lock); static cpumask_var_t vector_searchmask; static struct irq_chip lapic_controller; +static struct irq_chip lapic_nmi_controller; static struct irq_matrix *vector_matrix; #ifdef CONFIG_SMP static DEFINE_PER_CPU(struct hlist_head, cleanup_list); @@ -451,6 +452,10 @@ static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd, trace_vector_activate(irqd->irq, apicd->is_managed, apicd->can_reserve, reserve); + /* NMI has a fixed vector. No vector management required */ + if (apicd->hw_irq_cfg.delivery_mode == APIC_DELIVERY_MODE_NMI) + return 0; + raw_spin_lock_irqsave(&vector_lock, flags); if (!apicd->can_reserve && !apicd->is_managed) assign_irq_vector_any_locked(irqd); @@ -472,6 +477,10 @@ static void vector_free_reserved_and_managed(struct irq_data *irqd) trace_vector_teardown(irqd->irq, apicd->is_managed, apicd->has_reserved); + /* NMI has a fixed vector. No vector management required */ + if (apicd->hw_irq_cfg.delivery_mode == APIC_DELIVERY_MODE_NMI) + return; + if (apicd->has_reserved) irq_matrix_remove_reserved(vector_matrix); if (apicd->is_managed) @@ -539,6 +548,10 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, if (disable_apic) return -ENXIO; + /* Only one IRQ per NMI */ + if ((info->flags & X86_IRQ_ALLOC_AS_NMI) && nr_irqs != 1) + return -EINVAL; + /* * Catch any attempt to touch the cascade interrupt on a PIC * equipped system. @@ -573,6 +586,25 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, /* Don't invoke affinity setter on deactivated interrupts */ irqd_set_affinity_on_activate(irqd); + if (info->flags & X86_IRQ_ALLOC_AS_NMI) { + /* + * NMIs have a fixed vector and need their own + * interrupt chip so nothing can end up in the + * regular local APIC management code except the + * MSI message composing callback. + */ + apicd->hw_irq_cfg.delivery_mode = APIC_DELIVERY_MODE_NMI; + irqd->chip = &lapic_nmi_controller; + /* + * Exclude NMIs from balancing. This cannot work with + * the regular affinity mechanisms. The local APIC NMI + * controller provides a set_affinity() callback for the + * intended HPET NMI watchdog use case. + */ + irqd_set_no_balance(irqd); + return 0; + } + /* * A delivery mode may be specified in the interrupt allocation * info. If not, use the delivery mode of the APIC. @@ -872,8 +904,27 @@ static int apic_set_affinity(struct irq_data *irqd, return err ? err : IRQ_SET_MASK_OK; } +static int apic_nmi_set_affinity(struct irq_data *irqd, + const struct cpumask *dest, bool force) +{ + struct apic_chip_data *apicd = apic_chip_data(irqd); + static struct cpumask tmp_mask; + int cpu; + + cpumask_and(&tmp_mask, dest, cpu_online_mask); + if (cpumask_empty(&tmp_mask)) + return -ENODEV; + + cpu = cpumask_first(&tmp_mask); + apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); + irq_data_update_effective_affinity(irqd, cpumask_of(cpu)); + + return IRQ_SET_MASK_OK; +} + #else # define apic_set_affinity NULL +# define apic_nmi_set_affinity NULL #endif static int apic_retrigger_irq(struct irq_data *irqd) @@ -914,6 +965,12 @@ static struct irq_chip lapic_controller = { .irq_retrigger = apic_retrigger_irq, }; +static struct irq_chip lapic_nmi_controller = { + .name = "APIC-NMI", + .irq_set_affinity = apic_nmi_set_affinity, + .irq_compose_msi_msg = x86_vector_msi_compose_msg, +}; + #ifdef CONFIG_SMP static void free_moved_vector(struct apic_chip_data *apicd) diff --git a/include/linux/irq.h b/include/linux/irq.h index b1b28affb32a..c8738b36e316 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -263,6 +263,11 @@ static inline bool irqd_is_per_cpu(struct irq_data *d) return __irqd_to_state(d) & IRQD_PER_CPU; } +static inline void irqd_set_no_balance(struct irq_data *d) +{ + __irqd_to_state(d) |= IRQD_NO_BALANCING; +} + static inline bool irqd_can_balance(struct irq_data *d) { return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); From patchwork Wed Mar 1 23:47:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750263 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=TUujS3yU; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrNw4YxHz1yXC for ; Thu, 2 Mar 2023 10:41:52 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrNw3PJLz3f89 for ; Thu, 2 Mar 2023 10:41:52 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=TUujS3yU; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=TUujS3yU; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJY093nz3c9K for ; Thu, 2 Mar 2023 10:38:04 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713885; x=1709249885; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=K9unSxI1ETIAj+1EQ34Lma1zVNuCMXNt2Vl73pS93As=; b=TUujS3yUhSfD7Chvm02pO0rCpM8nxfn41zHwxf/TEG1Fp6n46eql8Ezl zJmcxzKfqpYhWjoDU7H7ud6GZZ+sBHVmJAnbnZqGHISY54ISPuyqIPBGE UPWireq888+y5uj5ekDxZ5F8pvABoBSw2ydnujHNvM8jqtr7vArrK1C3k qfiMqRQCLNC/+4KJn5pYoq+RDcLx7hzTKJ3qU0l3l875aG3DENM4TdVGS Qssnj8DZn72gNj3H7vd70ZVogLIf6OYHdnCTHKCetlK7kxU2PpwmOFiUt sMDgYLIbJ7kt4QGnHg7h8Eli3myEi5YQlNcqudj2MHFiYbVQifa2WX8et Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818696" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818696" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826802" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826802" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:56 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 05/24] x86/apic/vector: Skip cleanup for the NMI vector Date: Wed, 1 Mar 2023 15:47:34 -0800 Message-Id: <20230301234753.28582-6-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The NMI vector is fixed. No cleanup is needed after updating affinity. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ricardo Neri --- Changes since v6: * Introduced this patch. Changes since v5: * N/A Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- arch/x86/kernel/apic/vector.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index a4cf041427cb..3045823ecc1b 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -1050,6 +1050,10 @@ void send_cleanup_vector(struct irq_cfg *cfg) { struct apic_chip_data *apicd; + /* NMI has a fixed vector. No vector management required. */ + if (cfg->delivery_mode == APIC_DELIVERY_MODE_NMI) + return; + apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); if (apicd->move_in_progress) __send_cleanup_vector(apicd); From patchwork Wed Mar 1 23:47:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750265 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=YH+mxs1h; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrQz1wTsz1yXC for ; Thu, 2 Mar 2023 10:43:39 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrQy548lz3f46 for ; Thu, 2 Mar 2023 10:43:38 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=YH+mxs1h; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=YH+mxs1h; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJY40rPz3cBF for ; Thu, 2 Mar 2023 10:38:05 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713885; x=1709249885; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=X+fPhGM+miLCMioUQX1fq5QvQADp974IGsVIuBa8IIM=; b=YH+mxs1hSE90yWfCtw+w4Y4nk02pJMthVz7WPDVVe3TTL1il7ufwMdcR 1bVy4qWiFSRIp6dhwUPRIuVLVKgMqK+ewzXZK/TKO0L0Ap1erDNdzTrw1 4PHcobpj/UEsRBj8lS/Jg07WGF3l/wf1kUmPd5rjcBSetmj8fImq68X+b W4bj3Oijr7U+YN4JJPkICy5ZJYZqM2eK8f6JlI09Gjwxr+AjHrIr88p9Y ohF/egz1eeepWZ/vrtS/ktA8kwgXPDDQ82tGjshSqSmfXBrnW3u5G3idb RH3s7RnoROcOMRyclQ5I4XPmA8yyI2/9QVb914bierBYnIKs6sw9N3Wpw g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818703" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818703" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826807" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826807" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:56 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 06/24] iommu/vt-d: Clear the redirection hint when the destination mode is physical Date: Wed, 1 Mar 2023 15:47:35 -0800 Message-Id: <20230301234753.28582-7-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org, David Woodhouse , Lu Baolu Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" When the destination mode of an interrupt is physical APICID, the interrupt is delivered only to the single CPU of which the physical APICID is specified in the destination ID field. The redirection hint is meaningless. Furthermore, on certain processors, the IOMMU does not deliver the interrupt when the delivery mode is NMI, the redirection hint is set, and the destination mode is physical. Clearing the redirection hint ensures that the NMI is delivered. Cc: Andi Kleen Cc: David Woodhouse Cc: "Ravi V. Shankar" Cc: Lu Baolu Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Ashok Raj Reviewed-by: Lu Baolu Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch. Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- drivers/iommu/intel/irq_remapping.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c index 6d01fa078c36..2d68f94ae0ee 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1123,7 +1123,17 @@ static void prepare_irte(struct irte *irte, int vector, unsigned int dest) irte->dlvry_mode = apic->delivery_mode; irte->vector = vector; irte->dest_id = IRTE_DEST(dest); - irte->redir_hint = 1; + + /* + * When using the destination mode of physical APICID, only the + * processor specified in @dest receives the interrupt. The redirection + * hint is meaningless. + * + * Furthermore, on some processors, NMIs with physical delivery mode + * and the redirection hint set are delivered as regular interrupts + * or not delivered at all. + */ + irte->redir_hint = apic->dest_mode_logical; } struct irq_remap_ops intel_irq_remap_ops = { From patchwork Wed Mar 1 23:47:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750267 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=bMr+vtLi; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrT0343pz1yWw for ; Thu, 2 Mar 2023 10:45:24 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrT005dPz3cKD for ; Thu, 2 Mar 2023 10:45:24 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=bMr+vtLi; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=bMr+vtLi; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJY6zfpz3c41 for ; Thu, 2 Mar 2023 10:38:05 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713886; x=1709249886; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Q7jaVeyNCbxgl24yqNhvX8ZvPUYdNFgf6LLRZb5QSGE=; b=bMr+vtLi1slrYZHb0/a46nt1uz5E73qhpbSjY0fkTuGnxdPU7zwM5MXc VI1owAXekAzi7M8nW/54/qLGXO1PenZdDtz03GmgvAFr2wHzuGvi3vrHO QRJ4HuJWDG9ixTenHeCM2aYJm98Bqpy80NUlVaNPNJz9IBbmx4tTYpWTe ZpcMUHH3ewrSVMbUgFk5qVZIP8T5Dk/0HBF4in1awDki1U5haeodSGXyj hU21rro+5FJvWKEJBfaA1+h6oONPIirPCFE7mGgd2iMoYEE0i2NqE9Vdk by0PYRG9mOGIxBO0+FlzUC4WVllEaOc2IuvbzuUObu8l6htMQ8gx02MFJ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818711" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818711" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826811" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826811" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:56 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 07/24] iommu/vt-d: Rework prepare_irte() to support per-interrupt delivery mode Date: Wed, 1 Mar 2023 15:47:36 -0800 Message-Id: <20230301234753.28582-8-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , x86@kernel.org, Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org, David Woodhouse , Lu Baolu Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" struct irq_cfg::delivery_mode specifies the delivery mode of each interrupt separately. Configuring the delivery mode of an IRTE would require adding a third argument to prepare_irte(). Instead, take a pointer to the irq_cfg for which an IRTE is being configured. No functional changes. Cc: Andi Kleen Cc: David Woodhouse Cc: "Ravi V. Shankar" Cc: Lu Baolu Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Cc: x86@kernel.org Reviewed-by: Ashok Raj Reviewed-by: Tony Luck Reviewed-by: Lu Baolu Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Only change the signature of prepare_irte(). A separate patch changes the setting of the delivery_mode. Changes since v4: * None Changes since v3: * None Changes since v2: * None Changes since v1: * Introduced this patch. --- drivers/iommu/intel/irq_remapping.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c index 2d68f94ae0ee..1fe30c31fcbe 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1106,7 +1106,7 @@ void intel_irq_remap_add_device(struct dmar_pci_notify_info *info) dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev)); } -static void prepare_irte(struct irte *irte, int vector, unsigned int dest) +static void prepare_irte(struct irte *irte, struct irq_cfg *irq_cfg) { memset(irte, 0, sizeof(*irte)); @@ -1121,8 +1121,8 @@ static void prepare_irte(struct irte *irte, int vector, unsigned int dest) */ irte->trigger_mode = 0; irte->dlvry_mode = apic->delivery_mode; - irte->vector = vector; - irte->dest_id = IRTE_DEST(dest); + irte->vector = irq_cfg->vector; + irte->dest_id = IRTE_DEST(irq_cfg->dest_apicid); /* * When using the destination mode of physical APICID, only the @@ -1273,8 +1273,7 @@ static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, { struct irte *irte = &data->irte_entry; - prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid); - + prepare_irte(irte, irq_cfg); switch (info->type) { case X86_IRQ_ALLOC_TYPE_IOAPIC: /* Set source-id of interrupt request */ From patchwork Wed Mar 1 23:47:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750266 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=CHArbZUA; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrS01m5wz1yXC for ; Thu, 2 Mar 2023 10:44:32 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrS00fFKz3cJY for ; Thu, 2 Mar 2023 10:44:32 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=CHArbZUA; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=CHArbZUA; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJY72Bwz3c9K for ; Thu, 2 Mar 2023 10:38:05 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713886; x=1709249886; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=iAMY6btPT3LkFo8ii1+Ro1+SLEC/lk7JJlUCyqpnpJM=; b=CHArbZUAwDcZlmxLH9o2heZQwJeuzUYhKtZA3Pk4WYjO/c1v6xlF7QDQ DyX1iJNtT47bgmd9VLpuSoQu9lkUp7Y3qe6rpLb19foMpTbW5GP1u8D5e kTaKEoaKTPIW0j7ZM1X2YbzXhgBlTB5anOBDkXQ2bvo8Z9f64s1lU6jfK 28kP5izeRPJCtNhC/Y5x24VScI0ZObdm+vR94pmLZYRokplK06jHjN6sU BZ+N16C0FfaF1KQqp2bJXgNvYhqnlbznjBs9Uf97AkrXm/ebDJRJZ07YI 5gWHVdDYhh7jCBt2JMFY+R5OD79c7UoXJ7EjfoTJ0TFVupA1ULiLqvLjK Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818718" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818718" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826817" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826817" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:57 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 08/24] iommu/vt-d: Set the IRTE delivery mode individually for each interrupt Date: Wed, 1 Mar 2023 15:47:37 -0800 Message-Id: <20230301234753.28582-9-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org, David Woodhouse , Lu Baolu Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Use the mode specified in the provided interrupt hardware configuration data to set the delivery mode. Since most interrupts are configured to use the delivery mode of the APIC driver, there are no functional changes. The only exception are interrupts that do specify a different delivery mode. Cc: Andi Kleen Cc: David Woodhouse Cc: "Ravi V. Shankar" Cc: Lu Baolu Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Reviewed-by: Lu Baolu Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch. Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- drivers/iommu/intel/irq_remapping.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c index 1fe30c31fcbe..7b58406ea8d2 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1120,7 +1120,7 @@ static void prepare_irte(struct irte *irte, struct irq_cfg *irq_cfg) * irq migration in the presence of interrupt-remapping. */ irte->trigger_mode = 0; - irte->dlvry_mode = apic->delivery_mode; + irte->dlvry_mode = irq_cfg->delivery_mode; irte->vector = irq_cfg->vector; irte->dest_id = IRTE_DEST(irq_cfg->dest_apicid); From patchwork Wed Mar 1 23:47:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750268 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=EjOj3TX/; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrV94cmXz1yWw for ; Thu, 2 Mar 2023 10:46:25 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrV922z9z3cjB for ; Thu, 2 Mar 2023 10:46:25 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=EjOj3TX/; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=EjOj3TX/; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJZ33LJz3c6C for ; Thu, 2 Mar 2023 10:38:06 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713886; x=1709249886; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=mR16pLKgTuMhf9u2kE2UXUD7nzGYQyqB0h6xQLOZJvc=; b=EjOj3TX/NnDJ23yE1tNidQhgHdR5cOao0Y3OYzRo5hYttFGEf1PIgryG 8VsrJHlagz8RJ7ldoGfoZLZBdGs0EX+VqpWDZZCuty9kJ0iygKqtZJGWN h6I+np9mNPYzgWb2rZVuhRWc/ZzrGbDdbCs2h9AHUfL/6HXtX9Mvva35J 1GrzfihXDZ8FemsELDl8c+TRNL1mz+ofrqcE37Li5RKU+zDFwQ47ZDgpi kpO8hpgSyP4c+GdciI/caiSmc7GKy2dFkZFFktvmzgTKPRWgkwMnTsfc5 lT90b3C5g3Fjt6+5s184Fzt9psSBX6sfdCz+Xygh42C28sHnC6z8g8ol/ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818723" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818723" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826821" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826821" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:57 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 09/24] iommu/amd: Expose [set|get]_dev_entry_bit() Date: Wed, 1 Mar 2023 15:47:38 -0800 Message-Id: <20230301234753.28582-10-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Joerg Roedel , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Suravee Suthikulpanit , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" If an interrupt is allocated with NMI as delivery mode, the Device Table Entry needs to be modified accordingly in irq_remapping_alloc(). No functional changes. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Joerg Roedel Cc: Suravee Suthikulpanit Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- drivers/iommu/amd/amd_iommu.h | 3 +++ drivers/iommu/amd/init.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index c160a332ce33..b9b87a8cd48e 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -141,4 +141,7 @@ extern u64 amd_iommu_efr; extern u64 amd_iommu_efr2; extern bool amd_iommu_snp_en; + +extern void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit); +extern int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit); #endif diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 19a46b9f7357..559a9ecb785f 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -999,7 +999,7 @@ static void __set_dev_entry_bit(struct dev_table_entry *dev_table, dev_table[devid].data[i] |= (1UL << _bit); } -static void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) +void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) { struct dev_table_entry *dev_table = get_dev_table(iommu); @@ -1015,7 +1015,7 @@ static int __get_dev_entry_bit(struct dev_table_entry *dev_table, return (dev_table[devid].data[i] & (1UL << _bit)) >> _bit; } -static int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) +int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) { struct dev_table_entry *dev_table = get_dev_table(iommu); From patchwork Wed Mar 1 23:47:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750271 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=h5E6oTAm; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrYF21B9z1yWw for ; Thu, 2 Mar 2023 10:49:05 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrYD6bMnz3f5W for ; Thu, 2 Mar 2023 10:49:04 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=h5E6oTAm; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=h5E6oTAm; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJb0Kgqz3cLb for ; Thu, 2 Mar 2023 10:38:06 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713887; x=1709249887; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=btyWt/qyY31uspGHtLUS5h0GneCtSdCDc61owotTsK4=; b=h5E6oTAm1E/bpV/IHnHqUv6tUsIEJQyM1/A/Jyj7JCVWuDI7bs5Bb73D LXvAvjYpg4cRgmRO3c2Ngv95XnxWbBC/9stJ1XG5kydFYIGKvW2itJq4R ew1JbZfTeg++JLqrTEp+EVQrm49GaWySOA5aEwom4sRTztd6JQ19TI3nu J/QoxZyPtbmzyZeGIPxYB5cfGLugW8hWLlRB0pA+FfhRS3oRsMVXevmx5 rk/Bvi4yQHE4zFaXKmgMCio6QzfeJIMCpBICl9/Xu1Rz3BgXb/xX91gx8 3DoNAGNlqmG/7P5HRze0Qo2V9DFqoTVyrCHkXjIL3f4DL0XWJAHHHUGBO g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818727" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818727" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826826" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826826" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:57 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 10/24] iommu/amd: Enable NMIPass when allocating an NMI Date: Wed, 1 Mar 2023 15:47:39 -0800 Message-Id: <20230301234753.28582-11-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Joerg Roedel , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Suravee Suthikulpanit , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" As per the AMD I/O Virtualization Technology (IOMMU) Specification, the AMD IOMMU only remaps fixed and arbitrated MSIs. NMIs are controlled by the NMIPass bit of a Device Table Entry. When set, the IOMMU passes through NMI interrupt messages unmapped. Otherwise, they are aborted. Also, Section 2.2.5 Table 19 states that the IOMMU will abort NMIs when the destination mode is logical. Update the NMIPass setting of a device's DTE when an NMI is being allocated. Only do so when the destination mode of the APIC is not logical. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Joerg Roedel Cc: Suravee Suthikulpanit Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ricardo Neri --- Changes since v6: * Removed check for nr_irqs in irq_remapping_alloc(). Allocation had been rejected already in the root domain. (Thomas) Changes since v5: * Introduced this patch Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- drivers/iommu/amd/iommu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 5a505ba5467e..9bf71e7335f5 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3299,6 +3299,10 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI) return -EINVAL; + /* NMIs are aborted when the destination mode is logical. */ + if (info->flags & X86_IRQ_ALLOC_AS_NMI && apic->dest_mode_logical) + return -EPERM; + sbdf = get_devid(info); if (sbdf < 0) return -EINVAL; @@ -3348,6 +3352,13 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, goto out_free_parent; } + if (info->flags & X86_IRQ_ALLOC_AS_NMI) { + if (!get_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS)) { + set_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS); + iommu_flush_dte(iommu, devid); + } + } + for (i = 0; i < nr_irqs; i++) { irq_data = irq_domain_get_irq_data(domain, virq + i); cfg = irq_data ? irqd_cfg(irq_data) : NULL; From patchwork Wed Mar 1 23:47:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750269 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=n168adnf; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrWB3bNCz1yWw for ; Thu, 2 Mar 2023 10:47:18 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrWB2SPwz3cLr for ; Thu, 2 Mar 2023 10:47:18 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=n168adnf; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=n168adnf; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJZ5jWdz3c9K for ; Thu, 2 Mar 2023 10:38:06 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713886; x=1709249886; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=YMNfvnXnJB4uXk1mrYyUpmBPZvcLm4WxebEkvmrXwQo=; b=n168adnfUZB3psphHcNy3h3h5bKl0sXQdrNJ8bhaKib4Pc2VM2Bt7DqC 2Ka34KuTrQCb3JYWL5y15T28sjZKCmG6Ofy6E6XSBeTTDBvBlDEuK+Rvr uK3UrG2RNhl2RvnoxQ4WISFnc0Das1jnwe/4QB9bBD7xlZCJ6QR+ziPy0 tGTaeV0JmXJWAqjGoe5mqpEnWctO1LhxVfBKGMxmtOlbRD96x3JFnB43L 5a4zWZP+c852M/ojwvBaglxbVucIUv+mmr+MJuRHxSM+WETZHndVBnyYx bWsvrelGuCN/piJ0U0Wb+QitOqjmuYTKOTAfoqYAk3otdR882b+pWiwKv Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818733" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818733" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826831" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826831" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:57 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 11/24] iommu/amd: Compose MSI messages for NMIs in non-IR format Date: Wed, 1 Mar 2023 15:47:40 -0800 Message-Id: <20230301234753.28582-12-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Joerg Roedel , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Suravee Suthikulpanit , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" If NMIPass is enabled in a Device Table Entry, the IOMMU lets NMI interrupt messages pass through unmapped. The contents of the MSI message, not an IRTE, determine how and where the NMI is delivered. The IOMMU driver owns the MSI message of the NMI. Compose it using the non- interrupt-remapping format. Let descendant irqchips write the composed message. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Joerg Roedel Cc: Suravee Suthikulpanit Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ricardo Neri --- Changes since v6: * Reworded changelog to remove acronyms. (Thomas) * Removed confusing comment regarding interrupt vector cleanup after changing the affinity of an interrupt. (Thomas) Changes since v5: * Introduced this patch Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- drivers/iommu/amd/iommu.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 9bf71e7335f5..c6b0c365bf33 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3254,7 +3254,16 @@ static void irq_remapping_prepare_irte(struct amd_ir_data *data, case X86_IRQ_ALLOC_TYPE_HPET: case X86_IRQ_ALLOC_TYPE_PCI_MSI: case X86_IRQ_ALLOC_TYPE_PCI_MSIX: - fill_msi_msg(&data->msi_entry, irte_info->index); + if (irq_cfg->delivery_mode == APIC_DELIVERY_MODE_NMI) + /* + * The IOMMU lets NMIs pass through unmapped. Thus, the + * MSI message, not the IRTE, determines the interrupt + * configuration. Since we own the MSI message, + * compose it. + */ + __irq_msi_compose_msg(irq_cfg, &data->msi_entry, true); + else + fill_msi_msg(&data->msi_entry, irte_info->index); break; default: @@ -3643,6 +3652,15 @@ static int amd_ir_set_affinity(struct irq_data *data, */ send_cleanup_vector(cfg); + /* + * When the delivery mode of an interrupt is NMI, the IOMMU lets the NMI + * interrupt messages pass through unmapped. Changes in the destination + * must be reflected in the MSI message, not the IRTE. Descendant + * irqchips must set the affinity and write the MSI message. + */ + if (cfg->delivery_mode == APIC_DELIVERY_MODE_NMI) + return IRQ_SET_MASK_OK; + return IRQ_SET_MASK_OK_DONE; } From patchwork Wed Mar 1 23:47:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750272 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=WxmtFnda; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrZG4Tc7z1yWw for ; Thu, 2 Mar 2023 10:49:58 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrZG1s3wz3cgV for ; Thu, 2 Mar 2023 10:49:58 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=WxmtFnda; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=WxmtFnda; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJb3MzYz3cM1 for ; Thu, 2 Mar 2023 10:38:07 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713887; x=1709249887; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=F0R6+1IORr/b4JutI03SstHi+tgJzCauz5SrFc+e+nM=; b=WxmtFndaQrHRKarXgZNU+rx5FBPC0N6VQ1wNGzT4fXYXAjfCxzFO9xOz u4/LUmyjfKmbATlcFsBNnLalR8Qe/8NwmApcW4nFDaA7APvnCkXqX6igb SmbBW9NktsPgrlORGL/pYCPoN88cmVHPipbapZSGu18Y0e01JgGGbSH1/ Cu59O5FWR/vEFQsuejRtP70C0kValegRGumf5Xn4kedQHSKENWBOJUYBD CXrOstPs/ejfDW+zVBNMGJMvSSaFKW+E7zzn8aEHEmtsnXMGeXc/Rjms6 vgYlnitgKH5rvLED6qiMXguENv+wmJIVTmnlXSV2+KOWoFCm9iy2uRqgR w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818741" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818741" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826834" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826834" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:58 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 12/24] x86/hpet: Expose hpet_writel() in header Date: Wed, 1 Mar 2023 15:47:41 -0800 Message-Id: <20230301234753.28582-13-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" In order to allow hpet_writel() to be used by other components (e.g., the HPET-based hardlockup detector), expose it in the HPET header file. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * None Changes since v4: * Dropped exposing hpet_readq() as it is not needed. Changes since v3: * None Changes since v2: * None Changes since v1: * None --- arch/x86/include/asm/hpet.h | 1 + arch/x86/kernel/hpet.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index ab9f3dd87c80..be9848f0883f 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -72,6 +72,7 @@ extern int is_hpet_enabled(void); extern int hpet_enable(void); extern void hpet_disable(void); extern unsigned int hpet_readl(unsigned int a); +extern void hpet_writel(unsigned int d, unsigned int a); extern void force_hpet_resume(void); #ifdef CONFIG_HPET_EMULATE_RTC diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index c8eb1ac5125a..8303fb1b63a9 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -79,7 +79,7 @@ inline unsigned int hpet_readl(unsigned int a) return readl(hpet_virt_address + a); } -static inline void hpet_writel(unsigned int d, unsigned int a) +inline void hpet_writel(unsigned int d, unsigned int a) { writel(d, hpet_virt_address + a); } From patchwork Wed Mar 1 23:47:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750270 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=C5l6aadP; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrXC64Qzz1yWw for ; Thu, 2 Mar 2023 10:48:11 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrXC4qK8z3f7F for ; Thu, 2 Mar 2023 10:48:11 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=C5l6aadP; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=C5l6aadP; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJZ64Cbz3cJY for ; Thu, 2 Mar 2023 10:38:06 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713887; x=1709249887; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=zUIexEbd0hZhib5r+ZAg8qtfUzdZo+tlYmvOjzffG+U=; b=C5l6aadPgHyiXni63Tk8fCM95UYEUGEt6vRBeYPJX3jZIYHO7qfC0DeC 34Rhz9llrNRKCIe68Va+FTkDQ37eVMFRFNzIl9okS54lXDalBSc7tJ0zC kcCyUdpGLBvfBufv3EVIQ+zvyiGK3WYwJ8QKf1T6mgVnEVo6OtI7zCTtd MakEsANXqJVPSaqOrAxE9UdaxyThDZNHgdyQS7QBbqUMBFrFijGMM/ESg 32uPYDaIrdOnSeLEo8mqzBYhF7C1CL6Q22hpK7j/T6OJwfyxNzBZjcT5l 9Mk57o9SuKzg5evYvgfSS4xaHfsTFe/l1AwY3hfWIaofDUdmqmJjkPDOJ A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818748" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818748" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826838" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826838" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:58 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 13/24] x86/hpet: Add helper function hpet_set_comparator_periodic() Date: Wed, 1 Mar 2023 15:47:42 -0800 Message-Id: <20230301234753.28582-14-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Programming an HPET channel in periodic mode involves several steps. Besides the HPET clocksource, the HPET-based hardlockup detector may need to program its HPET channel in periodic mode. To avoid code duplication, wrap the programming of the HPET timer in a helper function. Cc: Andi Kleen Cc: Tony Luck Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Originally-by: Suravee Suthikulpanit Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- When programming the HPET channel in periodic mode, a udelay(1) between the two successive writes to HPET_Tn_CMP was introduced in commit e9e2cdb41241 ("[PATCH] clockevents: i386 drivers"). The commit message does not give any reason for such delay. The hardware specification does not seem to require it. The refactoring in this patch simply carries such delay. --- Changes since v6: * Reworded the commit message for clarity. Changes since v5: * None Changes since v4: * Implement function only for periodic mode. This removed extra logic to to use a non-zero period value as a proxy for periodic mode programming. (Thomas) * Added a comment on the history of the udelay() when programming the channel in periodic mode. (Ashok) Changes since v3: * Added back a missing hpet_writel() for time configuration. Changes since v2: * Introduced this patch. Changes since v1: * N/A --- arch/x86/include/asm/hpet.h | 2 ++ arch/x86/kernel/hpet.c | 49 ++++++++++++++++++++++++++++--------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index be9848f0883f..486e001413c7 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -74,6 +74,8 @@ extern void hpet_disable(void); extern unsigned int hpet_readl(unsigned int a); extern void hpet_writel(unsigned int d, unsigned int a); extern void force_hpet_resume(void); +extern void hpet_set_comparator_periodic(int channel, unsigned int cmp, + unsigned int period); #ifdef CONFIG_HPET_EMULATE_RTC diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 8303fb1b63a9..3563849c2290 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -294,6 +294,39 @@ static void hpet_enable_legacy_int(void) hpet_legacy_int_enabled = true; } +/** + * hpet_set_comparator_periodic() - Helper function to set periodic channel + * @channel: The HPET channel + * @cmp: The value to be written to the comparator/accumulator + * @period: Number of ticks per period + * + * Helper function for updating comparator, accumulator and period values. + * + * In periodic mode, HPET needs HPET_TN_SETVAL to be set before writing + * to the Tn_CMP to update the accumulator. Then, HPET needs a second + * write (with HPET_TN_SETVAL cleared) to Tn_CMP to set the period. + * The HPET_TN_SETVAL bit is automatically cleared after the first write. + * + * This function takes a 1 microsecond delay. However, this function is supposed + * to be called only once (or when reprogramming the timer) as it deals with a + * periodic timer channel. + * + * See the following documents: + * - Intel IA-PC HPET (High Precision Event Timers) Specification + * - AMD-8111 HyperTransport I/O Hub Data Sheet, Publication # 24674 + */ +void hpet_set_comparator_periodic(int channel, unsigned int cmp, unsigned int period) +{ + unsigned int v = hpet_readl(HPET_Tn_CFG(channel)); + + hpet_writel(v | HPET_TN_SETVAL, HPET_Tn_CFG(channel)); + + hpet_writel(cmp, HPET_Tn_CMP(channel)); + + udelay(1); + hpet_writel(period, HPET_Tn_CMP(channel)); +} + static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt) { unsigned int channel = clockevent_to_channel(evt)->num; @@ -306,19 +339,11 @@ static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt) now = hpet_readl(HPET_COUNTER); cmp = now + (unsigned int)delta; cfg = hpet_readl(HPET_Tn_CFG(channel)); - cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | - HPET_TN_32BIT; + cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_32BIT; hpet_writel(cfg, HPET_Tn_CFG(channel)); - hpet_writel(cmp, HPET_Tn_CMP(channel)); - udelay(1); - /* - * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL - * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL - * bit is automatically cleared after the first write. - * (See AMD-8111 HyperTransport I/O Hub Data Sheet, - * Publication # 24674) - */ - hpet_writel((unsigned int)delta, HPET_Tn_CMP(channel)); + + hpet_set_comparator_periodic(channel, cmp, (unsigned int)delta); + hpet_start_counter(); hpet_print_config(); From patchwork Wed Mar 1 23:47:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=e8hRTtkW; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrbG4cK9z2460 for ; Thu, 2 Mar 2023 10:50:50 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrbG3Pnmz3fc9 for ; Thu, 2 Mar 2023 10:50:50 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=e8hRTtkW; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=e8hRTtkW; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJb4TyPz3cMJ for ; Thu, 2 Mar 2023 10:38:07 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713887; x=1709249887; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=gdPe6IuTUA94m909UzTKj74jsvfoBAZ0rK9kosJdsBc=; b=e8hRTtkWHtdR3WPpf7Y5Z0k8Jt9z6LARn12ATMioV0deaSjbfoEbz1OX StlH79Q061bFWFbRG1AhpfHT9MJxpzszS/rVvKC+duwJOydB3ryzDJ/bI 95lN07pqMg+Cr/NL0IACTgp7BXU452kx1qaBGdk2exZcp+vcrwB4HZ3e0 x1dNok4/J1TuyfuYNoHIq0u3uJ9pkCV83GVUIKI6y5RNuEqrhtpSZvTGH tBGqlhNYkUjxYvSDzxkScQVBrAL1pDSwkWNozLAmKrkpK4kW33AGXJM5Z eApPKFXSMiaek75xL7rwOH066d7k5iJFLmCCCag2u0YG/3RptsyYmpmlP g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818751" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818751" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826842" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826842" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:58 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 14/24] x86/hpet: Prepare IRQ assignments to use the X86_ALLOC_AS_NMI flag Date: Wed, 1 Mar 2023 15:47:43 -0800 Message-Id: <20230301234753.28582-15-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The flag X86_ALLOC_AS_NMI indicates that the interrupts to be allocated in an interrupt domain need to be configured as NMIs. Add an as_nmi argument to hpet_assign_irq(). The HPET clock events do not need NMIs, but the HPET hardlockup detector does. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch. Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- arch/x86/kernel/hpet.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 3563849c2290..f42ce3fc4528 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -618,7 +618,7 @@ static inline int hpet_dev_id(struct irq_domain *domain) } static int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc, - int dev_num) + int dev_num, bool as_nmi) { struct irq_alloc_info info; @@ -627,6 +627,8 @@ static int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc, info.data = hc; info.devid = hpet_dev_id(domain); info.hwirq = dev_num; + if (as_nmi) + info.flags |= X86_IRQ_ALLOC_AS_NMI; return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); } @@ -755,7 +757,7 @@ static void __init hpet_select_clockevents(void) sprintf(hc->name, "hpet%d", i); - irq = hpet_assign_irq(hpet_domain, hc, hc->num); + irq = hpet_assign_irq(hpet_domain, hc, hc->num, false); if (irq <= 0) continue; From patchwork Wed Mar 1 23:47:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750274 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=kvMNTm5h; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrcJ07qjz246G for ; Thu, 2 Mar 2023 10:51:44 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrcH64Fcz3cMw for ; Thu, 2 Mar 2023 10:51:43 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=kvMNTm5h; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=kvMNTm5h; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJb4qnHz3cMK for ; Thu, 2 Mar 2023 10:38:07 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713887; x=1709249887; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+mf2a1s8IDXo9f4g6wZDARhxFh01FpRy/WRIkdf67AA=; b=kvMNTm5hs/0QNEnAUMLhqMNjK6EiIUSOOzvty3UHeez/7crPMehPegnO ovcYy6+gHbxu/1uPoNbE282jOkrV3FN78aEsQSggQgKYm8AdAOx2o8RTn ZXmy7bLAzes3a/cLEYD+rKA0ijm+WtsukTBKCJ8agGlh73EHLZ3slQt+0 srxfDvISHGwNWa+fCmCZQDWYGRMZJymL66vDz3+l2TfvNgn9ObCIH/Dix VxrslCOq7XW/ly5SUyCL2qWkS/vugXVALxy2woWnFSE8nABgGEIeVD5lv 73JzwhQXkVgOLIc1gtiBaymeKRUeZt9DroBrIsQWQg1NLXzEDaVwgtEVo A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818757" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818757" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826845" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826845" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:58 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 15/24] x86/hpet: Reserve an HPET channel for the hardlockup detector Date: Wed, 1 Mar 2023 15:47:44 -0800 Message-Id: <20230301234753.28582-16-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Create a new HPET_MODE_NMI_WATCHDOG mode category to reserve an HPET channel for the hard lockup detector. Only reserve the channel if the HPET frequency is sufficiently low to allow 32-bit register accesses and if Front Side BUS interrupt delivery (i.e., MSI interrupts) is supported. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Reworded the commit message for clarity. * Removed pointless global variable hld_data. Changes since v5: * Added a check for the allowed maximum frequency of the HPET. * Added hpet_hld_free_timer() to properly free the reserved HPET channel if the initialization is not completed. * Call hpet_assign_irq() with as_nmi = true. * Relocated declarations of functions and data structures of the detector to not depend on CONFIG_HPET_TIMER. Changes since v4: * Reworked timer reservation to use Thomas' rework on HPET channel management. * Removed hard-coded channel number for the hardlockup detector. * Provided more details on the sequence of HPET channel reservations. (Thomas Gleixner) * Only reserve a channel for the hardlockup detector if enabled via kernel command line. The function reserving the channel is called from hardlockup detector. (Thomas Gleixner) * Shorten the name of hpet_hardlockup_detector_get_timer() to hpet_hld_get_timer(). (Andi) * Simplify error handling when a channel is not found. (Tony) Changes since v3: * None Changes since v2: * None Changes since v1: * None --- arch/x86/include/asm/hpet.h | 22 ++++++++ arch/x86/kernel/hpet.c | 100 ++++++++++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+) diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index 486e001413c7..5762bd0169a1 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -103,4 +103,26 @@ static inline int is_hpet_enabled(void) { return 0; } #define default_setup_hpet_msi NULL #endif + +#ifdef CONFIG_X86_HARDLOCKUP_DETECTOR_HPET +/** + * struct hpet_hld_data - Data needed to operate the detector + * @has_periodic: The HPET channel supports periodic mode + * @channel: HPET channel assigned to the detector + * @channe_priv: Private data of the assigned channel + * @ticks_per_second: Frequency of the HPET timer + * @irq: IRQ number assigned to the HPET channel + */ +struct hpet_hld_data { + bool has_periodic; + u32 channel; + struct hpet_channel *channel_priv; + u64 ticks_per_second; + int irq; +}; + +extern struct hpet_hld_data *hpet_hld_get_timer(void); +extern void hpet_hld_free_timer(struct hpet_hld_data *hdata); +#endif /* CONFIG_X86_HARDLOCKUP_DETECTOR_HPET */ + #endif /* _ASM_X86_HPET_H */ diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index f42ce3fc4528..97570426f324 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -20,6 +20,7 @@ enum hpet_mode { HPET_MODE_LEGACY, HPET_MODE_CLOCKEVT, HPET_MODE_DEVICE, + HPET_MODE_NMI_WATCHDOG, }; struct hpet_channel { @@ -216,6 +217,7 @@ static void __init hpet_reserve_platform_timers(void) break; case HPET_MODE_CLOCKEVT: case HPET_MODE_LEGACY: + case HPET_MODE_NMI_WATCHDOG: hpet_reserve_timer(&hd, hc->num); break; } @@ -1498,3 +1500,101 @@ irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) } EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); #endif + +#ifdef CONFIG_X86_HARDLOCKUP_DETECTOR_HPET + +/* + * We program the channel in 32-bit mode to reduce the number of register + * accesses. The maximum value of watch_thresh is 60 seconds. The HPET counter + * should not wrap around more frequently than that: its frequency must be less + * than 71.582788 MHz. For safety, limit the frequency to 85% of the maximum + * permitted frequency. + * + * The frequency of the HPET in most systems in the field is less than 24MHz. + */ +#define HPET_HLD_MAX_FREQ 60845000ULL + +/** + * hpet_hld_free_timer - Free the reserved channel for the hardlockup detector + * @hdata: Data structure representing the reserved channel. + * + * Returns: none + */ +void hpet_hld_free_timer(struct hpet_hld_data *hld_data) +{ + hld_data->channel_priv->mode = HPET_MODE_UNUSED; + hld_data->channel_priv->in_use = 0; + kfree(hld_data); +} + +/** + * hpet_hld_get_timer - Get an HPET channel for the hardlockup detector + * + * Reserve an HPET channel if available, supports FSB mode, and has sufficiently + * low frequency. This function is called by the hardlockup detector if enabled + * in the kernel command line. + * + * Returns: a pointer with the properties of the reserved HPET channel. + */ +struct hpet_hld_data *hpet_hld_get_timer(void) +{ + struct hpet_channel *hc = hpet_base.channels; + struct hpet_hld_data *hld_data; + int i, irq; + + if (hpet_freq > HPET_HLD_MAX_FREQ) + return NULL; + + for (i = 0; i < hpet_base.nr_channels; i++) { + hc = hpet_base.channels + i; + + /* + * Associate the first unused channel to the hardlockup + * detector. Bailout if we cannot find one. This may happen if + * the HPET clocksource has taken all the timers. The HPET + * driver (/dev/hpet) has not taken any channels at this point. + */ + if (hc->mode == HPET_MODE_UNUSED) + break; + } + + if (i == hpet_base.nr_channels) + return NULL; + + if (!(hc->boot_cfg & HPET_TN_FSB_CAP)) + return NULL; + + hld_data = kzalloc(sizeof(*hld_data), GFP_KERNEL); + if (!hld_data) + return NULL; + + hc->mode = HPET_MODE_NMI_WATCHDOG; + hc->in_use = 1; + hld_data->channel_priv = hc; + + if (hc->boot_cfg & HPET_TN_PERIODIC_CAP) + hld_data->has_periodic = true; + + if (!hpet_domain) + hpet_domain = hpet_create_irq_domain(hpet_blockid); + + if (!hpet_domain) + goto err; + + /* Assign an IRQ with NMI delivery mode. */ + irq = hpet_assign_irq(hpet_domain, hc, hc->num, true); + if (irq <= 0) + goto err; + + hc->irq = irq; + hld_data->irq = irq; + hld_data->channel = i; + hld_data->ticks_per_second = hpet_freq; + + return hld_data; + +err: + hpet_hld_free_timer(hld_data); + return NULL; +} +#endif /* CONFIG_X86_HARDLOCKUP_DETECTOR_HPET */ From patchwork Wed Mar 1 23:47:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=D7B5abtj; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrdK0Pdhz2460 for ; Thu, 2 Mar 2023 10:52:37 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrdJ6Hzcz3fQn for ; Thu, 2 Mar 2023 10:52:36 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=D7B5abtj; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=D7B5abtj; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJb6b5Xz3cMR for ; Thu, 2 Mar 2023 10:38:07 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713888; x=1709249888; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=7e3va9vu9qwj2yqdORjxuaJ7bdwskL9Kry8TAY9yGpM=; b=D7B5abtjcVLoa1KjZE2mgwbYBp7xLnQhQbJG1luOjqbXKybN61RRziJQ cr7iCOTcMPLbbNdC2cg+vyryuuSvodyaBIp7az4N8aZtawLsCYJsi4ckM iQYd2kgEE5tfYiWfldBeyp1AFdVq+XCHQiXgbhnNTiTOCnwxFtuAbcJZK l5NbwfkzSxnv87houpH3ZfqdByxVSndoEOXLGHAXk/Gh48tv5o8EfgAzd JILUF5QHDzy8o3tCCItKumQDYtQ196dJ7Cf9y8F0VPv+8TmAmaoDxc+xj P6haIUz7cr2QV1MG5MC9p9nCkXUtbLe7+sX7xkCnv82WCdh00udTqiagL A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818764" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818764" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826849" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826849" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:59 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 16/24] watchdog/hardlockup: Define a generic function to detect hardlockups Date: Wed, 1 Mar 2023 15:47:45 -0800 Message-Id: <20230301234753.28582-17-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Nicholas Piggin , Andrew Morton , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The procedure to detect hardlockups is independent of the source of the the non-maskable interrupt that drives it. Place it in a separate, generic function to be invoked by various implementations of the NMI watchdog. Move the bulk of watchdog_overflow_callback() to the new function inspect_for_hardlockups(). This function can then be called from the applicable NMI handlers. No functional changes. Cc: Andi Kleen Cc: Nicholas Piggin Cc: Andrew Morton Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * None Changes since v4: * None Changes since v3: * None Changes since v2: * None Changes since v1: * None --- include/linux/nmi.h | 1 + kernel/watchdog_hld.c | 18 +++++++++++------- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/include/linux/nmi.h b/include/linux/nmi.h index 048c0b9aa623..75038cb2710e 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -209,6 +209,7 @@ int proc_nmi_watchdog(struct ctl_table *, int , void *, size_t *, loff_t *); int proc_soft_watchdog(struct ctl_table *, int , void *, size_t *, loff_t *); int proc_watchdog_thresh(struct ctl_table *, int , void *, size_t *, loff_t *); int proc_watchdog_cpumask(struct ctl_table *, int, void *, size_t *, loff_t *); +void inspect_for_hardlockups(struct pt_regs *regs); #ifdef CONFIG_HAVE_ACPI_APEI_NMI #include diff --git a/kernel/watchdog_hld.c b/kernel/watchdog_hld.c index 247bf0b1582c..b352e507b17f 100644 --- a/kernel/watchdog_hld.c +++ b/kernel/watchdog_hld.c @@ -106,14 +106,8 @@ static struct perf_event_attr wd_hw_attr = { .disabled = 1, }; -/* Callback function for perf event subsystem */ -static void watchdog_overflow_callback(struct perf_event *event, - struct perf_sample_data *data, - struct pt_regs *regs) +void inspect_for_hardlockups(struct pt_regs *regs) { - /* Ensure the watchdog never gets throttled */ - event->hw.interrupts = 0; - if (__this_cpu_read(watchdog_nmi_touch) == true) { __this_cpu_write(watchdog_nmi_touch, false); return; @@ -163,6 +157,16 @@ static void watchdog_overflow_callback(struct perf_event *event, return; } +/* Callback function for perf event subsystem */ +static void watchdog_overflow_callback(struct perf_event *event, + struct perf_sample_data *data, + struct pt_regs *regs) +{ + /* Ensure the watchdog never gets throttled */ + event->hw.interrupts = 0; + inspect_for_hardlockups(regs); +} + static int hardlockup_detector_event_create(void) { unsigned int cpu = smp_processor_id(); From patchwork Wed Mar 1 23:47:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750276 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=e98mV4j8; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrfM2c76z2460 for ; Thu, 2 Mar 2023 10:53:31 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrfL6pg2z3f3w for ; Thu, 2 Mar 2023 10:53:30 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=e98mV4j8; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=e98mV4j8; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJc2Tp0z3cMh for ; Thu, 2 Mar 2023 10:38:08 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713888; x=1709249888; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=y8eExCkaoLH5zqN5BzT0UUYALRj8RDWacqQHg/gnrqc=; b=e98mV4j834Yv364KRUjV++945aypqHTLErWVEKt/Zlz2cRhEY3ScgZqy I/xFB+vNF9C+xl6OOKcRG4TlEU344IJ+HWYU2qT+EoZRCFm5Zc/9HwJny iNde+F1zGuHNk/WtziZwnK+bhAy0XHTdK1VT0+6YnrS33+yVPvGrt46SA GHikiazd2ZoJldM4vDL1HQXl7KBfuXqsKZWpF9CbTFXZH4bdtimWiU8gw 3wfy0qWn50BfktoHhr1RXUodwplRzIUCez1miDyto9/3LbHNSXl/tr52F ae3QRYpf3cbsgmm3k6YvSUdsIrx0nVMMVtx2V1oC0C8qBhWdE3OZeSfH1 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818772" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818772" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826853" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826853" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:59 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 17/24] watchdog/hardlockup: Decouple the hardlockup detector from perf Date: Wed, 1 Mar 2023 15:47:46 -0800 Message-Id: <20230301234753.28582-18-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Nicholas Piggin , Andrew Morton , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The current default implementation of the hardlockup detector assumes that it is implemented using perf events. However, the hardlockup detector can be driven by other sources of non-maskable interrupts (e.g., a properly configured timer). Group and wrap in #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF all the code specific to perf: create and manage perf events, stop and start the perf- based detector. The generic portion of the detector (monitor the timers' thresholds, check timestamps and detect hardlockups as well as the implementation of arch_touch_nmi_watchdog()) is now selected with the new intermediate config symbol CONFIG_HARDLOCKUP_DETECTOR_CORE. The perf-based implementation of the detector selects the new intermediate symbol. Other implementations should do the same. Cc: Andi Kleen Cc: Nicholas Piggin Cc: Andrew Morton Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * None Changes since v4: * None Changes since v3: * Squashed into this patch a previous patch to make arch_touch_nmi_watchdog() part of the core detector code. Changes since v2: * Undid split of the generic hardlockup detector into a separate file. (Thomas Gleixner) * Added a new intermediate symbol CONFIG_HARDLOCKUP_DETECTOR_CORE to select generic parts of the detector (Paul E. McKenney, Thomas Gleixner). Changes since v1: * Make the generic detector code with CONFIG_HARDLOCKUP_DETECTOR. --- include/linux/nmi.h | 5 ++++- kernel/Makefile | 2 +- kernel/watchdog_hld.c | 32 ++++++++++++++++++++------------ lib/Kconfig.debug | 4 ++++ 4 files changed, 29 insertions(+), 14 deletions(-) diff --git a/include/linux/nmi.h b/include/linux/nmi.h index 75038cb2710e..a38c4509f9eb 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -94,8 +94,11 @@ static inline void hardlockup_detector_disable(void) {} # define NMI_WATCHDOG_SYSCTL_PERM 0444 #endif -#if defined(CONFIG_HARDLOCKUP_DETECTOR_PERF) +#if defined(CONFIG_HARDLOCKUP_DETECTOR_CORE) extern void arch_touch_nmi_watchdog(void); +#endif + +#if defined(CONFIG_HARDLOCKUP_DETECTOR_PERF) extern void hardlockup_detector_perf_stop(void); extern void hardlockup_detector_perf_restart(void); extern void hardlockup_detector_perf_disable(void); diff --git a/kernel/Makefile b/kernel/Makefile index 10ef068f598d..f35fad36cf81 100644 --- a/kernel/Makefile +++ b/kernel/Makefile @@ -91,7 +91,7 @@ obj-$(CONFIG_FAIL_FUNCTION) += fail_function.o obj-$(CONFIG_KGDB) += debug/ obj-$(CONFIG_DETECT_HUNG_TASK) += hung_task.o obj-$(CONFIG_LOCKUP_DETECTOR) += watchdog.o -obj-$(CONFIG_HARDLOCKUP_DETECTOR_PERF) += watchdog_hld.o +obj-$(CONFIG_HARDLOCKUP_DETECTOR_CORE) += watchdog_hld.o obj-$(CONFIG_SECCOMP) += seccomp.o obj-$(CONFIG_RELAY) += relay.o obj-$(CONFIG_SYSCTL) += utsname_sysctl.o diff --git a/kernel/watchdog_hld.c b/kernel/watchdog_hld.c index b352e507b17f..bb6435978c46 100644 --- a/kernel/watchdog_hld.c +++ b/kernel/watchdog_hld.c @@ -22,12 +22,8 @@ static DEFINE_PER_CPU(bool, hard_watchdog_warn); static DEFINE_PER_CPU(bool, watchdog_nmi_touch); -static DEFINE_PER_CPU(struct perf_event *, watchdog_ev); -static DEFINE_PER_CPU(struct perf_event *, dead_event); -static struct cpumask dead_events_mask; static unsigned long hardlockup_allcpu_dumped; -static atomic_t watchdog_cpus = ATOMIC_INIT(0); notrace void arch_touch_nmi_watchdog(void) { @@ -98,14 +94,6 @@ static inline bool watchdog_check_timestamp(void) } #endif -static struct perf_event_attr wd_hw_attr = { - .type = PERF_TYPE_HARDWARE, - .config = PERF_COUNT_HW_CPU_CYCLES, - .size = sizeof(struct perf_event_attr), - .pinned = 1, - .disabled = 1, -}; - void inspect_for_hardlockups(struct pt_regs *regs) { if (__this_cpu_read(watchdog_nmi_touch) == true) { @@ -157,6 +145,24 @@ void inspect_for_hardlockups(struct pt_regs *regs) return; } +#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF +#undef pr_fmt +#define pr_fmt(fmt) "NMI perf watchdog: " fmt + +static DEFINE_PER_CPU(struct perf_event *, watchdog_ev); +static DEFINE_PER_CPU(struct perf_event *, dead_event); +static struct cpumask dead_events_mask; + +static atomic_t watchdog_cpus = ATOMIC_INIT(0); + +static struct perf_event_attr wd_hw_attr = { + .type = PERF_TYPE_HARDWARE, + .config = PERF_COUNT_HW_CPU_CYCLES, + .size = sizeof(struct perf_event_attr), + .pinned = 1, + .disabled = 1, +}; + /* Callback function for perf event subsystem */ static void watchdog_overflow_callback(struct perf_event *event, struct perf_sample_data *data, @@ -298,3 +304,5 @@ int __init hardlockup_detector_perf_init(void) } return ret; } + +#endif /* CONFIG_HARDLOCKUP_DETECTOR_PERF */ diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index c8b379e2e9ad..1ff53c5995b1 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -1025,9 +1025,13 @@ config BOOTPARAM_SOFTLOCKUP_PANIC Say N if unsure. +config HARDLOCKUP_DETECTOR_CORE + bool + config HARDLOCKUP_DETECTOR_PERF bool select SOFTLOCKUP_DETECTOR + select HARDLOCKUP_DETECTOR_CORE # # Enables a timestamp based low pass filter to compensate for perf based From patchwork Wed Mar 1 23:47:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750278 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=H9dN0DdP; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrhQ1QM9z1yXC for ; Thu, 2 Mar 2023 10:55:17 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrhP5q55z3f3c for ; Thu, 2 Mar 2023 10:55:17 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=H9dN0DdP; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=H9dN0DdP; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJc3cSJz3cMl for ; Thu, 2 Mar 2023 10:38:08 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713888; x=1709249888; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=xD5rPq6P/jQ6w9PLq/j9I8SmnPmQHq2Xa5HGzEHRX2c=; b=H9dN0DdPlGPgjv9W6E5XkYvuSf9wgjzCKt1/miR8HymrguGkh7guhEKi NXCeNuWk3jpta1vZHEwRjfOjK3NmFInAmtcEV4TimgtzweyTJj3GtJUHn YBl1Qaym+yrQiIzuMRKzfJBYMDvV8aQS/SwoXheKzumi1MyYwWmmT/k8U Fasw19aNh+Qw5gNgGj0fz/ogW8+XxVB033tVmtCjJw/SdehksdxIQLoOQ 1pS7DJqw/ricGb5Tj45B4Z9mpuZ7XfxCxGE2M32+IzVCj0LCSw4cvJsJ6 wNmZb0FHssG12EB+wmcqmTBn81yDiC7wifMoK+014R+5IPZvt6+0C+KRl g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818780" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818780" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826857" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826857" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:59 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 18/24] init/main: Delay initialization of the lockup detector after smp_init() Date: Wed, 1 Mar 2023 15:47:47 -0800 Message-Id: <20230301234753.28582-19-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Nicholas Piggin , Andrew Morton , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Certain implementations of the hardlockup detector require support for Inter-Processor Interrupt shorthands. On x86, support for these can only be determined after all the possible CPUs have booted once (in smp_init()). Other architectures may not need such check. lockup_detector_init() only performs the initializations of data structures of the lockup detector. Hence, there are no dependencies on smp_init(). Cc: Andi Kleen Cc: Nicholas Piggin Cc: Andrew Morton Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Acked-by: Nicholas Piggin Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- init/main.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/init/main.c b/init/main.c index 4425d1783d5c..d0642a49e2e8 100644 --- a/init/main.c +++ b/init/main.c @@ -1620,9 +1620,11 @@ static noinline void __init kernel_init_freeable(void) rcu_init_tasks_generic(); do_pre_smp_initcalls(); - lockup_detector_init(); smp_init(); + + lockup_detector_init(); + sched_init_smp(); padata_init(); From patchwork Wed Mar 1 23:47:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=BVVTtGMu; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrgN3rhgz2460 for ; Thu, 2 Mar 2023 10:54:24 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrgN1D03z3fTl for ; Thu, 2 Mar 2023 10:54:24 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=BVVTtGMu; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=BVVTtGMu; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJc3Pzhz3cMk for ; Thu, 2 Mar 2023 10:38:08 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713888; x=1709249888; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=8QIuyN0QEY4OfKB2VbUhtM2hIu//OC14YEF4m3K65og=; b=BVVTtGMuyDzf1Dak8IbTGthLAf5gSqKGuL0KOVhuSvwzTaLsvTDE+Zdu no3vDY8C2LFYbBS0j+O3XJZeJtR4xyS5mJNT9scGW7+hEHeBtHpM4+oja ZwLcSJkUZ2R5ulBugrzby7TJIjh5SqYXQejy4GMEqF06ZwLMkyMlNxR9d n+HHRoW8o18t+pNlRM4y1vRsa4FUnSYMZAEGXwdF1TcRVYhvtPunqeUkA pM0kArgys2DWN2nvBzlh9SwtSzm79P6WiStjhz2kv5ECA3A4OkTff3a8V 95b9V/ruoTbI6Q0eyU/4WAXbkjeHMOjihNx8LQFhPkJKqBldoiLVFKtH7 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818781" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818781" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:38:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826860" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826860" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:59 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 19/24] x86/watchdog/hardlockup: Add an HPET-based hardlockup detector Date: Wed, 1 Mar 2023 15:47:48 -0800 Message-Id: <20230301234753.28582-20-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Implement a hardlockup detector that uses an HPET channel as the source of the non-maskable interrupt. Implement the basic functionality to start, stop, and configure the timer. Designate as the handling CPU one of the CPUs that the detector monitors. Use it to service the NMI from the HPET channel. When servicing the HPET NMI, issue an inter-processor interrupt to the rest of the monitored CPUs to look for hardlockups. Only enable the detector if IPI shorthands are enabled in the system. During operation, the HPET registers are only accessed to kick the timer. This operation can be avoided if the detector gets a periodic HPET channel. Since we use IPI shorthands, all CPUs get the IPI NMI. This would disturb the isolated CPUs specified in the nohz_full command-line parameter. In such case, do not enable this hardlockup detector implementation. The detector is not functional at this stage. A subsequent changeset will invoke the interfaces implemented in this changeset to operate the detector. Another subsequent changeset implements logic to determine if the HPET timer caused the NMI. For now, implement a stub function. Cc: Andi Kleen Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Added missing header asm/nmi.h. linux/nmi.h #includes it only if CONFIG_HAVE_NMI_WATCHDOG selected. Such option is not selected for ARCH=x86. * Removed IRQF_NOBALANCING from request_irq(). The NMI vector already is configured to prevent balancing. * Added check to not use the detector when the nohz_full= command-line parameter is present. * Since I dropped the patch that added a new NMI_WATCHDOG list of handlers, now I added my handler to the NMI_LOCAL list. This makes sense since now the watchdog NMIs are now delivered via IPIs. The only exception is the HPET NMI, but that interrupt can only be handled by the monitoring CPU. Changes since v5: * Squashed a previously separate patch to support interrupt remapping into this patch. There is no need to handle interrupt remapping separately. All the necessary plumbing is done in the interrupt subsystem. Now it uses request_irq(). * Use IPI shorthands to send an NMI to the CPUs being monitored. (Thomas) * Added extra check to only use the HPET hardlockup detector if the IPI shorthands are enabled. (Thomas) * Relocated flushing of outstanding interrupts from enable_timer() to disable_timer(). On some systems, making any change in the configuration of the HPET channel causes it to issue an interrupt. * Added a new cpumask to function as a per-cpu test bit to determine if a CPU should check for hardlockups. * Dropped pointless X86_64 || X86_32 check in Kconfig. (Tony) * Dropped pointless dependency on CONFIG_HPET. * Added dependency on CONFIG_GENERIC_MSI_IRQ, needed to build the [|IR]- HPET-MSI irq_chip. * Added hardlockup_detector_hpet_start() to be used when tsc_khz is recalibrated. * Reworked the periodic setting the HPET channel. Rather than changing it every time the channel is disabled or enabled, do it only once. While at here, wrap the code in an initial setup function. * Implemented hardlockup_detector_hpet_start() to be called when tsc_khz is refined. * Enhanced inline comments for clarity. * Added missing #include files. * Relocated function declarations to not depend on CONFIG_HPET_TIMER. Changes since v4: * Dropped hpet_hld_data.enabled_cpus and instead use cpumask_weight(). * Renamed hpet_hld_data.cpu_monitored_mask to hld_data_data.cpu_monitored_mask and converted it to cpumask_var_t. * Flushed out any outstanding interrupt before enabling the HPET channel. * Removed unnecessary MSI_DATA_LEVEL_ASSERT from the MSI message. * Added comments in hardlockup_detector_nmi_handler() to explain how CPUs are targeted for an IPI. * Updated code to only issue an IPI when needed (i.e., there are monitored CPUs to be inspected via an IPI). * Reworked hardlockup_detector_hpet_init() for readability. * Now reserve the cpumasks in the hardlockup detector code and not in the generic HPET code. * Handled the case of watchdog_thresh = 0 when disabling the detector. * Made this detector available to i386. * Reworked logic to kick the timer to remove a local variable. (Andi) * Added a comment on what type of timer channel will be assigned to the detector. (Andi) * Reworded prompt comment in Kconfig. (Andi) * Removed unneeded switch to level interrupt mode when disabling the timer. (Andi) * Disabled the HPET timer to avoid a race between an incoming interrupt and an update of the MSI destination ID. (Ashok) * Corrected a typo in an inline comment. (Tony) * Made the HPET hardlockup detector depend on HARDLOCKUP_DETECTOR instead of selecting it. Changes since v3: * Fixed typo in Kconfig.debug. (Randy Dunlap) * Added missing slab.h to include the definition of kfree to fix a build break. Changes since v2: * Removed use of struct cpumask in favor of a variable length array in conjunction with kzalloc. (Peter Zijlstra) * Removed redundant documentation of functions. (Thomas Gleixner) * Added CPU as argument hardlockup_detector_hpet_enable()/disable(). (Thomas Gleixner). Changes since v1: * Do not target CPUs in a round-robin manner. Instead, the HPET timer always targets the same CPU; other CPUs are monitored via an interprocessor interrupt. * Dropped support for IO APIC interrupts and instead use only MSI interrupts. * Removed use of generic irq code to set interrupt affinity and NMI delivery. Instead, configure the interrupt directly in HPET registers. (Thomas Gleixner) * Fixed unconditional return NMI_HANDLED when the HPET timer is programmed for FSB/MSI delivery. (Peter Zijlstra) --- arch/x86/Kconfig.debug | 8 + arch/x86/include/asm/hpet.h | 21 ++ arch/x86/kernel/Makefile | 1 + arch/x86/kernel/watchdog_hld_hpet.c | 380 ++++++++++++++++++++++++++++ 4 files changed, 410 insertions(+) create mode 100644 arch/x86/kernel/watchdog_hld_hpet.c diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index bdfe08f1a930..b4dced142116 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -110,6 +110,14 @@ config IOMMU_LEAK config HAVE_MMIOTRACE_SUPPORT def_bool y +config X86_HARDLOCKUP_DETECTOR_HPET + bool "HPET-based hardlockup detector" + select HARDLOCKUP_DETECTOR_CORE + depends on HARDLOCKUP_DETECTOR && HPET_TIMER && GENERIC_MSI_IRQ + help + Say y to drive the hardlockup detector using the High-Precision Event + Timer instead of performance counters. + config X86_DECODER_SELFTEST bool "x86 instruction decoder selftest" depends on DEBUG_KERNEL && INSTRUCTION_DECODER diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index 5762bd0169a1..c88901744848 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -105,6 +105,8 @@ static inline int is_hpet_enabled(void) { return 0; } #endif #ifdef CONFIG_X86_HARDLOCKUP_DETECTOR_HPET +#include + /** * struct hpet_hld_data - Data needed to operate the detector * @has_periodic: The HPET channel supports periodic mode @@ -112,6 +114,10 @@ static inline int is_hpet_enabled(void) { return 0; } * @channe_priv: Private data of the assigned channel * @ticks_per_second: Frequency of the HPET timer * @irq: IRQ number assigned to the HPET channel + * @handling_cpu: CPU handling the HPET interrupt + * @monitored_cpumask: CPUs monitored by the hardlockup detector + * @inspect_cpumask: CPUs that will be inspected at a given time. + * Each CPU clears itself upon inspection. */ struct hpet_hld_data { bool has_periodic; @@ -119,10 +125,25 @@ struct hpet_hld_data { struct hpet_channel *channel_priv; u64 ticks_per_second; int irq; + u32 handling_cpu; + cpumask_var_t monitored_cpumask; + cpumask_var_t inspect_cpumask; }; extern struct hpet_hld_data *hpet_hld_get_timer(void); extern void hpet_hld_free_timer(struct hpet_hld_data *hdata); +int hardlockup_detector_hpet_init(void); +void hardlockup_detector_hpet_start(void); +void hardlockup_detector_hpet_stop(void); +void hardlockup_detector_hpet_enable(unsigned int cpu); +void hardlockup_detector_hpet_disable(unsigned int cpu); +#else +static inline int hardlockup_detector_hpet_init(void) +{ return -ENODEV; } +static inline void hardlockup_detector_hpet_start(void) {} +static inline void hardlockup_detector_hpet_stop(void) {} +static inline void hardlockup_detector_hpet_enable(unsigned int cpu) {} +static inline void hardlockup_detector_hpet_disable(unsigned int cpu) {} #endif /* CONFIG_X86_HARDLOCKUP_DETECTOR_HPET */ #endif /* _ASM_X86_HPET_H */ diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index dd61752f4c96..58eb858f33ff 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -109,6 +109,7 @@ obj-$(CONFIG_VM86) += vm86_32.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_HPET_TIMER) += hpet.o +obj-$(CONFIG_X86_HARDLOCKUP_DETECTOR_HPET) += watchdog_hld_hpet.o obj-$(CONFIG_AMD_NB) += amd_nb.o obj-$(CONFIG_DEBUG_NMI_SELFTEST) += nmi_selftest.o diff --git a/arch/x86/kernel/watchdog_hld_hpet.c b/arch/x86/kernel/watchdog_hld_hpet.c new file mode 100644 index 000000000000..b583d3180ae0 --- /dev/null +++ b/arch/x86/kernel/watchdog_hld_hpet.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * A hardlockup detector driven by an HPET channel. + * + * Copyright (C) Intel Corporation 2023 + * + * An HPET channel is reserved for the detector. The channel issues an NMI to + * one of the CPUs in @watchdog_allowed_mask. This CPU monitors itself for + * hardlockups and sends an NMI IPI to the rest of the CPUs in the system. + * + * The detector uses IPI shorthands. Thus, all CPUs in the system get the NMI + * (offline CPUs also get the NMI but they "ignore" it). A cpumask is used to + * specify whether a CPU must check for hardlockups. + * + * The NMI also disturbs isolated CPUs. The detector fails to initialize if + * tick_nohz_full is enabled. + */ + +#define pr_fmt(fmt) "NMI hpet watchdog: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "apic/local.h" + +static struct hpet_hld_data *hld_data; + +static void __init setup_hpet_channel(struct hpet_hld_data *hdata) +{ + u32 v; + + v = hpet_readl(HPET_Tn_CFG(hdata->channel)); + if (hdata->has_periodic) + v |= HPET_TN_PERIODIC; + else + v &= ~HPET_TN_PERIODIC; + + /* + * Use 32-bit mode to limit the number of register accesses. If we are + * here the HPET frequency is sufficiently low to accommodate this mode. + */ + v |= HPET_TN_32BIT; + + /* If we are here, FSB mode is supported. */ + v |= HPET_TN_FSB; + + hpet_writel(v, HPET_Tn_CFG(hdata->channel)); +} + +/** + * kick_timer() - Reprogram timer to expire in the future + * @hdata: A data structure describing the HPET channel + * @force: Force reprogramming + * + * Reprogram the timer to expire in watchdog_thresh seconds in the future. + * If the timer supports periodic mode, it is not kicked unless @force is + * true. + */ +static void kick_timer(struct hpet_hld_data *hdata, bool force) +{ + u64 new_compare, count, period = 0; + + /* Kick the timer only when needed. */ + if (!force && hdata->has_periodic) + return; + + /* + * Update the comparator in increments of watch_thresh seconds relative + * to the current count. Since watch_thresh is given in seconds, we can + * safely update the comparator before the counter reaches such new + * value. + * + * Let it wrap around if needed. + */ + + count = hpet_readl(HPET_COUNTER); + new_compare = count + watchdog_thresh * hdata->ticks_per_second; + + if (!hdata->has_periodic) { + hpet_writel(new_compare, HPET_Tn_CMP(hdata->channel)); + return; + } + + period = watchdog_thresh * hdata->ticks_per_second; + hpet_set_comparator_periodic(hdata->channel, (u32)new_compare, + (u32)period); +} + +static void disable_timer(struct hpet_hld_data *hdata) +{ + u32 v; + + v = hpet_readl(HPET_Tn_CFG(hdata->channel)); + v &= ~HPET_TN_ENABLE; + + /* + * Prepare to flush out any outstanding interrupt. This can only be + * done in level-triggered mode. + */ + v |= HPET_TN_LEVEL; + hpet_writel(v, HPET_Tn_CFG(hdata->channel)); + + /* + * Even though we use the HPET channel in edge-triggered mode, hardware + * seems to keep an outstanding interrupt and posts an MSI message when + * making any change to it (e.g., enabling or setting to FSB mode). + * Flush out the interrupt status bit of our channel. + */ + hpet_writel(1 << hdata->channel, HPET_STATUS); +} + +static void enable_timer(struct hpet_hld_data *hdata) +{ + u32 v; + + v = hpet_readl(HPET_Tn_CFG(hdata->channel)); + v &= ~HPET_TN_LEVEL; + v |= HPET_TN_ENABLE; + hpet_writel(v, HPET_Tn_CFG(hdata->channel)); +} + +/** + * is_hpet_hld_interrupt() - Check if the HPET channel caused the interrupt + * @hdata: A data structure describing the HPET channel + * + * Returns: + * True if the HPET watchdog timer caused the interrupt. False otherwise. + */ +static bool is_hpet_hld_interrupt(struct hpet_hld_data *hdata) +{ + return false; +} + +/** + * hardlockup_detector_nmi_handler() - NMI Interrupt handler + * @type: Type of NMI handler; not used. + * @regs: Register values as seen when the NMI was asserted + * + * Check if our HPET channel caused the NMI. If yes, inspect for lockups by + * issuing an IPI to the rest of the CPUs. Also, kick the timer if it is + * non-periodic. + * + * Returns: + * NMI_DONE if the HPET timer did not cause the interrupt. NMI_HANDLED + * otherwise. + */ +static int hardlockup_detector_nmi_handler(unsigned int type, + struct pt_regs *regs) +{ + struct hpet_hld_data *hdata = hld_data; + int cpu; + + /* + * The CPU handling the HPET NMI will land here and trigger the + * inspection of hardlockups in the rest of the monitored + * CPUs. + */ + if (is_hpet_hld_interrupt(hdata)) { + /* + * Kick the timer first. If the HPET channel is periodic, it + * helps to reduce the delta between the expected TSC value and + * its actual value the next time the HPET channel fires. + */ + kick_timer(hdata, !(hdata->has_periodic)); + + if (cpumask_weight(hld_data->monitored_cpumask) > 1) { + /* + * Since we cannot know the source of an NMI, the best + * we can do is to use a flag to indicate to all online + * CPUs that they will get an NMI and that the source of + * that NMI is the hardlockup detector. Offline CPUs + * also receive the NMI but they ignore it. + */ + cpumask_copy(hld_data->inspect_cpumask, + cpu_online_mask); + + /* If we are here, IPI shorthands are enabled. */ + apic->send_IPI_allbutself(NMI_VECTOR); + } + + inspect_for_hardlockups(regs); + return NMI_HANDLED; + } + + /* The rest of the CPUs will land here after receiving the IPI. */ + cpu = smp_processor_id(); + if (cpumask_test_and_clear_cpu(cpu, hld_data->inspect_cpumask)) { + if (cpumask_test_cpu(cpu, hld_data->monitored_cpumask)) + inspect_for_hardlockups(regs); + + return NMI_HANDLED; + } + + return NMI_DONE; +} + +/** + * setup_hpet_irq() - Install the interrupt handler of the detector + * @data: Data associated with the instance of the HPET channel + * + * Returns: + * 0 success. An error code if setup was unsuccessful. + */ +static int setup_hpet_irq(struct hpet_hld_data *hdata) +{ + int ret; + + /* + * hld_data::irq was configured to deliver the interrupt as + * NMI. Thus, there is no need for a regular interrupt handler. + */ + ret = request_irq(hld_data->irq, no_action, IRQF_TIMER, + "hpet_hld", hld_data); + if (ret) + return ret; + + ret = register_nmi_handler(NMI_LOCAL, + hardlockup_detector_nmi_handler, 0, + "hpet_hld"); + if (ret) + free_irq(hld_data->irq, hld_data); + + return ret; +} + +/** + * hardlockup_detector_hpet_enable() - Enable the hardlockup detector + * @cpu: CPU Index in which the watchdog will be enabled. + * + * Enable the hardlockup detector in @cpu. Also, start the detector if not done + * before. + */ +void hardlockup_detector_hpet_enable(unsigned int cpu) +{ + cpumask_set_cpu(cpu, hld_data->monitored_cpumask); + + /* + * If this is the first CPU on which the detector is enabled, designate + * @cpu as the handling CPU and start everything. The HPET channel is + * disabled at this point. + */ + if (cpumask_weight(hld_data->monitored_cpumask) == 1) { + hld_data->handling_cpu = cpu; + + if (irq_set_affinity(hld_data->irq, + cpumask_of(hld_data->handling_cpu))) { + pr_warn_once("Failed to set affinity. Hardlockdup detector not started"); + return; + } + + kick_timer(hld_data, true); + enable_timer(hld_data); + } +} + +/** + * hardlockup_detector_hpet_disable() - Disable the hardlockup detector + * @cpu: CPU index in which the watchdog will be disabled + * + * Disable the hardlockup detector in @cpu. If @cpu is also handling the NMI + * from the HPET channel, update the affinity of the interrupt. + */ +void hardlockup_detector_hpet_disable(unsigned int cpu) +{ + cpumask_clear_cpu(cpu, hld_data->monitored_cpumask); + + if (hld_data->handling_cpu != cpu) + return; + + disable_timer(hld_data); + if (!cpumask_weight(hld_data->monitored_cpumask)) + return; + + /* + * If watchdog_thresh is zero, then the hardlockup detector is being + * disabled. + */ + if (!watchdog_thresh) + return; + + hld_data->handling_cpu = cpumask_any_but(hld_data->monitored_cpumask, + cpu); + /* + * Only update the affinity of the HPET channel interrupt when + * disabled. + */ + if (irq_set_affinity(hld_data->irq, + cpumask_of(hld_data->handling_cpu))) { + pr_warn_once("Failed to set affinity. Hardlockdup detector stopped"); + return; + } + + enable_timer(hld_data); +} + +void hardlockup_detector_hpet_stop(void) +{ + disable_timer(hld_data); +} + +void hardlockup_detector_hpet_start(void) +{ + kick_timer(hld_data, true); + enable_timer(hld_data); +} + +static const char hpet_hld_init_failed[] = "Initialization failed:"; + +/** + * hardlockup_detector_hpet_init() - Initialize the hardlockup detector + * + * Only initialize and configure the detector if an HPET is available on the + * system, the TSC is stable, IPI shorthands are enabled, and there are no + * isolated CPUs. + * + * Returns: + * 0 success. An error code if initialization was unsuccessful. + */ +int __init hardlockup_detector_hpet_init(void) +{ + int ret; + + if (!is_hpet_enabled()) { + pr_info("%s HPET unavailable\n", hpet_hld_init_failed); + return -ENODEV; + } + + if (tick_nohz_full_enabled()) { + pr_info("%s nohz_full in use\n", hpet_hld_init_failed); + return -EPERM; + } + + if (!static_branch_likely(&apic_use_ipi_shorthand)) { + pr_info("%s APIC IPI shorthands disabled\n", hpet_hld_init_failed); + return -ENODEV; + } + + if (check_tsc_unstable()) + return -ENODEV; + + hld_data = hpet_hld_get_timer(); + if (!hld_data) + return -ENODEV; + + disable_timer(hld_data); + + setup_hpet_channel(hld_data); + + ret = setup_hpet_irq(hld_data); + if (ret) + goto err_no_irq; + + if (!zalloc_cpumask_var(&hld_data->monitored_cpumask, GFP_KERNEL)) + goto err_no_monitored_cpumask; + + if (!zalloc_cpumask_var(&hld_data->inspect_cpumask, GFP_KERNEL)) + goto err_no_inspect_cpumask; + + return 0; + +err_no_inspect_cpumask: + free_cpumask_var(hld_data->monitored_cpumask); +err_no_monitored_cpumask: + ret = -ENOMEM; +err_no_irq: + hpet_hld_free_timer(hld_data); + hld_data = NULL; + + return ret; +} From patchwork Wed Mar 1 23:47:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750281 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=fhRVB+Mo; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrld3H6Mz1yXC for ; Thu, 2 Mar 2023 10:58:05 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrld25Lqz3fTT for ; Thu, 2 Mar 2023 10:58:05 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=fhRVB+Mo; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=fhRVB+Mo; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJd2CFyz3cNh for ; Thu, 2 Mar 2023 10:38:09 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713889; x=1709249889; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=EY5U0PovmXiAtFsslCouXhpNbANtXU/1R9huXKKUbQs=; b=fhRVB+Mo7cUNgN+gOO3zgndNLV7yOfhv4ICla6m0IBWB63sOeOSMn/WI tp6ckhG77RDYYl456QfHHxj3+j5SR3Eu1LfMDsipVAfgJ3JpeNO/qar84 rMoBbPZ2iOjJKnRv6mTvgHjhE24sIHqvK+Rh32YQU3cYL7OVdZa/OdIq5 3SeiXNFdnazMuKZecJR8J7W0xQ0w8ag0NQk3OxGl2bQCgNtMcvExKuSI3 wW0mwQEJorhD+FOZ/n5/dV6N3Ug5srxdEbYxsTkTjUy0b6TyH7/+Z4AlD 2zrzAn/m9gxRpCZX6SuHl0TAF5L6EXF6Bb05esWoyxAX4A1rAgdWBxCAd w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818786" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818786" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:38:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826864" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826864" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:38:00 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 20/24] x86/watchdog/hardlockup/hpet: Determine if HPET timer caused NMI Date: Wed, 1 Mar 2023 15:47:49 -0800 Message-Id: <20230301234753.28582-21-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" It is not possible to determine the source of a non-maskable interrupt (NMI) in x86. When dealing with an HPET channel, the only direct method to determine whether it caused an NMI would be to read the Interrupt Status register. Reading HPET registers is slow and, therefore, not to be done while in NMI context. Also, the interrupt status bit is not available if the HPET channel is programmed to deliver an MSI interrupt. An indirect manner to infer if the HPET channel is the source of an NMI is is to use the time-stamp counter (TSC). Compute the value that the TSC is expected to have at the next interrupt of the HPET channel and compare it with the value it has when the interrupt does happen. Let this error be tsc_next_error. If tsc_next_error is less than a certain value, assume that the HPET channel of the detector is the source of the NMI. Below is a table that characterizes tsc_next_error in a collection of systems. The error is expressed in microseconds as well as a percentage of tsc_delta: the computed number of TSC counts between two consecutive interrupts of the HPET channel. The table summarizes the error of 4096 interrupts of the HPET channel in two experiments: a) since the system booted and b) ignoring the first 5 minutes after boot. The maximum observed error in a) is 0.198%. For b) the maximum error is 0.045%. Allow a maximum tsc_next_error that is twice as big the maximum error observed in these experiments: 0.4% of tsc_delta. watchdog_thresh 1s 10s 60s tsc_next_error % us % us % us AMD EPYC 7742 64-Core Processor max(abs(a)) 0.04517 451.74 0.00171 171.04 0.00034 201.89 max(abs(b)) 0.04517 451.74 0.00171 171.04 0.00034 201.89 Intel(R) Xeon(R) CPU E7-8890 - INTEL_FAM6_HASWELL_X max(abs(a)) 0.00811 81.15 0.00462 462.40 0.00014 81.65 max(abs(b)) 0.00811 81.15 0.00084 84.31 0.00014 81.65 Intel(R) Xeon(R) Platinum 8170M - INTEL_FAM6_SKYLAKE_X max(abs(a)) 0.10530 1053.04 0.01324 1324.27 0.00407 2443.25 max(abs(b)) 0.01166 116.59 0.00114 114.11 0.00024 143.47 Intel(R) Xeon(R) CPU E5-2699A v4 - INTEL_FAM6_BROADSWELL_X max(abs(a)) 0.00010 99.34 0.00099 98.83 0.00016 97.50 max(abs(b)) 0.00010 99.34 0.00099 98.83 0.00016 97.50 Intel(R) Xeon(R) Gold 5318H - INTEL_FAM6_COOPERLAKE_X max(abs(a)) 0.11262 1126.17 0.01109 1109.17 0.00409 2455.73 max(abs(b)) 0.01073 107.31 0.00109 109.02 0.00019 115.34 Intel(R) Xeon(R) Platinum 8360Y - INTEL_FAM6_ICELAKE_X max(abs(a)) 0.19853 1985.30 0.00784 783.53 -0.00017 -104.77 max(abs(b)) 0.01550 155.02 0.00158 157.56 0.00020 117.74 Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- NOTE: The error characterization data is repeated here from the cover letter. --- Changes since v6: * Fixed bug when checking the error window. Now check for an error which is +/-4% the actual TSC value, not +/-2%. Changes since v5: * Reworked is_hpet_hld_interrupt() to reduce indentation. * Use time_in_range64() to compare the actual TSC value vs the expected value. This makes it more readable. (Tony) * Reduced the error window of the expected TSC value at the time of the HPET channel expiration. * Described better the heuristics used to determine if the HPET channel caused the NMI. (Tony) * Added a table to characterize the error in the expected TSC value when the HPET channel fires. * Removed references to groups of monitored CPUs. Instead, use tsc_khz directly. Changes since v4: * Compute the TSC expected value at the next HPET interrupt based on the number of monitored packages and not the number of monitored CPUs. Changes since v3: * None Changes since v2: * Reworked condition to check if the expected TSC value is within the error margin to avoid an unnecessary conditional. (Peter Zijlstra) * Removed TSC error margin from struct hld_data; use a global variable instead. (Peter Zijlstra) Changes since v1: * Introduced this patch. --- arch/x86/include/asm/hpet.h | 3 ++ arch/x86/kernel/watchdog_hld_hpet.c | 58 +++++++++++++++++++++++++++-- 2 files changed, 58 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index c88901744848..af0a504b5cff 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -113,6 +113,8 @@ static inline int is_hpet_enabled(void) { return 0; } * @channel: HPET channel assigned to the detector * @channe_priv: Private data of the assigned channel * @ticks_per_second: Frequency of the HPET timer + * @tsc_next: Estimated value of the TSC at the next + * HPET timer interrupt * @irq: IRQ number assigned to the HPET channel * @handling_cpu: CPU handling the HPET interrupt * @monitored_cpumask: CPUs monitored by the hardlockup detector @@ -124,6 +126,7 @@ struct hpet_hld_data { u32 channel; struct hpet_channel *channel_priv; u64 ticks_per_second; + u64 tsc_next; int irq; u32 handling_cpu; cpumask_var_t monitored_cpumask; diff --git a/arch/x86/kernel/watchdog_hld_hpet.c b/arch/x86/kernel/watchdog_hld_hpet.c index b583d3180ae0..a03126e02eda 100644 --- a/arch/x86/kernel/watchdog_hld_hpet.c +++ b/arch/x86/kernel/watchdog_hld_hpet.c @@ -12,6 +12,11 @@ * (offline CPUs also get the NMI but they "ignore" it). A cpumask is used to * specify whether a CPU must check for hardlockups. * + * It is not possible to determine the source of an NMI. Instead, we calculate + * the value that the TSC counter should have when the next HPET NMI occurs. If + * it has the calculated value +/- 0.4%, we conclude that the HPET channel is the + * source of the NMI. + * * The NMI also disturbs isolated CPUs. The detector fails to initialize if * tick_nohz_full is enabled. */ @@ -34,6 +39,7 @@ #include "apic/local.h" static struct hpet_hld_data *hld_data; +static u64 tsc_next_error; static void __init setup_hpet_channel(struct hpet_hld_data *hdata) { @@ -65,12 +71,39 @@ static void __init setup_hpet_channel(struct hpet_hld_data *hdata) * Reprogram the timer to expire in watchdog_thresh seconds in the future. * If the timer supports periodic mode, it is not kicked unless @force is * true. + * + * Also, compute the expected value of the time-stamp counter at the time of + * expiration as well as a deviation from the expected value. */ static void kick_timer(struct hpet_hld_data *hdata, bool force) { - u64 new_compare, count, period = 0; + u64 tsc_curr, tsc_delta, new_compare, count, period = 0; + + tsc_curr = rdtsc(); + + /* + * Compute the delta between the value of the TSC now and the value + * it will have the next time the HPET channel fires. + */ + tsc_delta = watchdog_thresh * tsc_khz * 1000L; + hdata->tsc_next = tsc_curr + tsc_delta; + + /* + * Define an error window between the expected TSC value and the actual + * value it will have the next time the HPET channel fires. Define this + * error as percentage of tsc_delta. + * + * The systems that have been tested so far exhibit an error of 0.05% + * of the expected TSC value once the system is up and running. Systems + * that refine tsc_khz exhibit a larger initial error up to 0.2%. To be + * safe, allow a maximum error of ~0.4% (i.e., tsc_delta / 256). + */ + tsc_next_error = tsc_delta >> 8; - /* Kick the timer only when needed. */ + /* + * We must compute the exptected TSC value always. Kick the timer only + * when needed. + */ if (!force && hdata->has_periodic) return; @@ -133,12 +166,31 @@ static void enable_timer(struct hpet_hld_data *hdata) * is_hpet_hld_interrupt() - Check if the HPET channel caused the interrupt * @hdata: A data structure describing the HPET channel * + * Determining the sources of NMIs is not possible. Furthermore, we have + * programmed the HPET channel for MSI delivery, which does not have a + * status bit. Also, reading HPET registers is slow. + * + * Instead, we just assume that an NMI delivered within a time window + * of when the HPET was expected to fire probably came from the HPET. + * + * The window is estimated using the TSC counter. Check the comments in + * kick_timer() for details on the size of the time window. + * * Returns: * True if the HPET watchdog timer caused the interrupt. False otherwise. */ static bool is_hpet_hld_interrupt(struct hpet_hld_data *hdata) { - return false; + u64 tsc_curr, tsc_curr_min, tsc_curr_max; + + if (smp_processor_id() != hdata->handling_cpu) + return false; + + tsc_curr = rdtsc(); + tsc_curr_min = tsc_curr - tsc_next_error; + tsc_curr_max = tsc_curr + tsc_next_error; + + return time_in_range64(hdata->tsc_next, tsc_curr_min, tsc_curr_max); } /** From patchwork Wed Mar 1 23:47:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750279 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=AOBB/LWd; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrjQ5Cm4z1yXC for ; Thu, 2 Mar 2023 10:56:10 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrjQ3xLmz3fSV for ; Thu, 2 Mar 2023 10:56:10 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=AOBB/LWd; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=AOBB/LWd; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJc5K9yz3cMy for ; Thu, 2 Mar 2023 10:38:08 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713888; x=1709249888; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=OqhPN6kNm1+6G6yIlNPIASa1IBCFVuZdDvhvGUbI0q8=; b=AOBB/LWdZLdxtjd4r+sxXsRjAkrteQbBt3PTcA4zb1+ePNicyjt2fNTB p7t4QptGyVpwdH2ji3gNCXPOISf0HYVSk5/JwwNtmET5EWMMa+uswDWv5 tbQ/fpB+GrNA8AAErsmEeehWUspm+/SDdMiZTGtPv/D/7mptGBuyS6em3 RI8lKjQXFNGrGpIv6yvTD4e5FKPrCucSNGJqgK+NM5Zh0TnHUJQRf6+Yl S9ASruNx1dwvqfux+XyQwROFMtt2kjANF5p7yeOKattvHAideDM6ZDP7o d3pdbbC2zHlob5Kpw4+NBut4/SoFliTTZ0XyP1vf2EUeAogwY5r7fprH+ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818792" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818792" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:38:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826868" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826868" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:38:00 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 21/24] watchdog/hardlockup/hpet: Only enable the HPET watchdog via a boot parameter Date: Wed, 1 Mar 2023 15:47:50 -0800 Message-Id: <20230301234753.28582-22-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Keep the HPET-based hardlockup detector disabled unless explicitly enabled via a command-line argument. If such parameter is not given, the initialization of the HPET-based hardlockup detector fails and the NMI watchdog will fall back to use the perf-based implementation. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Do not reuse the nmi_watchdog command line option. Instead, use a separate command line option. (Nicholas Piggin) * Document conflict with conflict between `hpet_nmi_watchdog` and `nohz_full` and dependency on `no_ipi_broadcast`. Changes since v5: * None Changes since v4: * None Changes since v3: * None Changes since v2: * Do not imply that using nmi_watchdog=hpet means the detector is enabled. Instead, print a warning in such case. Changes since v1: * Added documentation to the function handing the nmi_watchdog kernel command-line argument. --- Documentation/admin-guide/kernel-parameters.txt | 8 ++++++++ arch/x86/kernel/watchdog_hld_hpet.c | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 46268d6baa43..2d1262bb99c7 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1708,6 +1708,14 @@ hpet_mmap= [X86, HPET_MMAP] Allow userspace to mmap HPET registers. Default set by CONFIG_HPET_MMAP_DEFAULT. + hpet_nmi_watchdog [X86, KNL] + Drive the NMI watchdog with an HPET channel. This option + has no effect if the NMI watchdog is not enabled. + The HPET NMI watchdog conflicts with the parameters + nohz_full, no_ipi_broadcast, and hpet=disable. If any + of these parameters is present the NMI watchdog will + fall back to the perf-driven implementation. + hugepages= [HW] Number of HugeTLB pages to allocate at boot. If this follows hugepagesz (below), it specifies the number of pages of hugepagesz to be allocated. diff --git a/arch/x86/kernel/watchdog_hld_hpet.c b/arch/x86/kernel/watchdog_hld_hpet.c index a03126e02eda..0fc728ad6f15 100644 --- a/arch/x86/kernel/watchdog_hld_hpet.c +++ b/arch/x86/kernel/watchdog_hld_hpet.c @@ -39,6 +39,7 @@ #include "apic/local.h" static struct hpet_hld_data *hld_data; +static bool hardlockup_use_hpet; static u64 tsc_next_error; static void __init setup_hpet_channel(struct hpet_hld_data *hdata) @@ -366,6 +367,19 @@ void hardlockup_detector_hpet_start(void) enable_timer(hld_data); } +/** + * hardlockup_detector_hpet_setup() - Parse command-line parameters + * @str: A string containing the kernel command line + * + * If selected by the user, enable this hardlockup detector. + */ +static int __init hardlockup_detector_hpet_setup(char *str) +{ + hardlockup_use_hpet = true; + return 1; +} +__setup("hpet_nmi_watchdog", hardlockup_detector_hpet_setup); + static const char hpet_hld_init_failed[] = "Initialization failed:"; /** @@ -382,6 +396,9 @@ int __init hardlockup_detector_hpet_init(void) { int ret; + if (!hardlockup_use_hpet) + return -ENODEV; + if (!is_hpet_enabled()) { pr_info("%s HPET unavailable\n", hpet_hld_init_failed); return -ENODEV; From patchwork Wed Mar 1 23:47:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=NMPe86NR; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrmg2xk1z1yXC for ; Thu, 2 Mar 2023 10:58:59 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrmf5lpdz3cfd for ; Thu, 2 Mar 2023 10:58:58 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=NMPe86NR; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=NMPe86NR; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJd2gVWz3cMl for ; Thu, 2 Mar 2023 10:38:09 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713889; x=1709249889; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=E7eibuMdPGOmosuXsQch6hVs6NOJvXyAD7ZfCZZWJUQ=; b=NMPe86NRoMqDfEShtjZFZbjxmbk/1I6OUCgxJFbvGi7Mf9ngKynKUWwg G66U5QNar1svDU4hHcoyZ61btYUYxp9ZVh34H61VHBlGLLBZPKzwv6730 xy7BCY20KogJdP6Qozgn7FPxxmSnI6aZhKsNQ8SIV7DARFpteccvIihbY MxcisEkiMGM85XA/WF1rQNnAsbBwfD47wZgmLYKKlLWgtxU3kl4IxH27r x3B+8Nj4xPgti8zKwIN3OzTDWiKQu3ER1iljaGmdFKbdYyj9Ap9byDroa nSsAWMytirG2KD0V5smHVhZVUmleSJLC5VvFC9dMPE3V9YzmTw7S42Hdl g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818796" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818796" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:38:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826871" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826871" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:38:00 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 22/24] x86/watchdog: Add a shim hardlockup detector Date: Wed, 1 Mar 2023 15:47:51 -0800 Message-Id: <20230301234753.28582-23-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Add a shim hardlockup detector that allows to select between the perf- and HPET-driven implementations available for x86. Override the interfaces of the default hardlockup detector. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Nicholas Piggin Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Added watchdog_nmi_start() to be used when the watchdog is reconfigured. * Always build the x86-specific hardlockup detector shim; not only when the HPET-based detector is selected. * Corrected a typo in comment in watchdog_nmi_probe() (Ani) * Removed useless local ret variable in watchdog_nmi_enable(). (Ani) Changes since v4: * Use a switch to enable and disable the various available detectors. (Andi) Changes since v3: * Fixed style in multi-line comment. (Randy Dunlap) Changes since v2: * Pass cpu number as argument to hardlockup_detector_[enable|disable]. (Thomas Gleixner) Changes since v1: * Introduced this patch: Added an x86-specific shim hardlockup detector. (Nicholas Piggin) --- arch/x86/Kconfig.debug | 3 ++ arch/x86/kernel/Makefile | 2 + arch/x86/kernel/watchdog_hld.c | 86 ++++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 arch/x86/kernel/watchdog_hld.c diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index b4dced142116..41ae46314307 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -3,6 +3,9 @@ config EARLY_PRINTK_USB bool +config X86_HARDLOCKUP_DETECTOR + def_bool y if HARDLOCKUP_DETECTOR_CORE + config X86_VERBOSE_BOOTUP bool "Enable verbose x86 bootup info messages" default y diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 58eb858f33ff..706294fd5e46 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -108,6 +108,8 @@ obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_VM86) += vm86_32.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_X86_HARDLOCKUP_DETECTOR) += watchdog_hld.o + obj-$(CONFIG_HPET_TIMER) += hpet.o obj-$(CONFIG_X86_HARDLOCKUP_DETECTOR_HPET) += watchdog_hld_hpet.o diff --git a/arch/x86/kernel/watchdog_hld.c b/arch/x86/kernel/watchdog_hld.c new file mode 100644 index 000000000000..33c22f6456a3 --- /dev/null +++ b/arch/x86/kernel/watchdog_hld.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * A shim hardlockup detector for x86 to select between the perf- and HPET- + * driven implementations. + * + * Copyright (C) Intel Corporation 2023 + */ + +#include +#include + +enum x86_hardlockup_detector { + X86_HARDLOCKUP_DETECTOR_PERF, + X86_HARDLOCKUP_DETECTOR_HPET, +}; + +static enum x86_hardlockup_detector detector_type __ro_after_init; + +int watchdog_nmi_enable(unsigned int cpu) +{ + switch (detector_type) { + case X86_HARDLOCKUP_DETECTOR_PERF: + hardlockup_detector_perf_enable(); + break; + case X86_HARDLOCKUP_DETECTOR_HPET: + hardlockup_detector_hpet_enable(cpu); + break; + default: + return -ENODEV; + } + + return 0; +} + +void watchdog_nmi_disable(unsigned int cpu) +{ + switch (detector_type) { + case X86_HARDLOCKUP_DETECTOR_PERF: + hardlockup_detector_perf_disable(); + break; + case X86_HARDLOCKUP_DETECTOR_HPET: + hardlockup_detector_hpet_disable(cpu); + break; + } +} + +int __init watchdog_nmi_probe(void) +{ + int ret; + + /* + * Try first with the HPET hardlockup detector. It will only succeed if + * requested via the kernel command line. The perf-based detector is + * used by default. + */ + ret = hardlockup_detector_hpet_init(); + if (!ret) { + detector_type = X86_HARDLOCKUP_DETECTOR_HPET; + return ret; + } + + ret = hardlockup_detector_perf_init(); + if (!ret) { + detector_type = X86_HARDLOCKUP_DETECTOR_PERF; + return ret; + } + + return 0; +} + +void watchdog_nmi_stop(void) +{ + /* Only the HPET lockup detector defines a stop function. */ + if (detector_type == X86_HARDLOCKUP_DETECTOR_HPET) + hardlockup_detector_hpet_stop(); +} + +void watchdog_nmi_start(void) +{ + if (!(watchdog_enabled & NMI_WATCHDOG_ENABLED)) + return; + + /* Only the HPET lockup detector defines a start function. */ + if (detector_type == X86_HARDLOCKUP_DETECTOR_HPET) + hardlockup_detector_hpet_start(); +} From patchwork Wed Mar 1 23:47:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750280 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=ZAbHbTcF; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrkc30kYz1yXC for ; Thu, 2 Mar 2023 10:57:12 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrkc0Kj4z3cjQ for ; Thu, 2 Mar 2023 10:57:12 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=ZAbHbTcF; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=ZAbHbTcF; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJd1P7qz3cKD for ; Thu, 2 Mar 2023 10:38:09 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713889; x=1709249889; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=TJtWiEKn9cKtWyiPL16X6Q+Hc9VuKWnOfoMEGJZdAM0=; b=ZAbHbTcFOyZ2HMg5U6+7zoE73BhrYTXz6lzCN3hJyU18fkqmj/9lXgDJ CJX4r86woOWQ7zoXP6zd9VTEkPRhLkRRo8bIeJzqRM0FL6GUfIc1jwzIB D8o5CTZ1g+fiJIZJrq4YLzvzU8ys7BKkXW+cWQxneSZMvKShkO9zOayRT HXFD7kWMcKAMcPO4CEGV/YOmyGkW1oe7+SHMDNPb8bKnomF34iFM/M5qg /OLrt4EiDnmO9izIEi5aS803wfdcBb7Z4sbmTm5HNByHFVGeYTlbenEXV XSNTVXyWbHbcZqKy0SGPDeiiaCAH27M6V2pjz9BF+AyW2JM6a8Xpjqtnz w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818801" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818801" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:38:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826874" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826874" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:38:00 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 23/24] watchdog: Introduce hardlockup_detector_mark_unavailable() Date: Wed, 1 Mar 2023 15:47:52 -0800 Message-Id: <20230301234753.28582-24-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The NMI watchdog may become unreliable during runtime. This is the case in x86 if, for instance, the HPET-based hardlockup detector is in use and the TSC counter becomes unstable. Introduce a new interface to mark the hardlockup detector as unavailable in such cases. When doing this, update the state of /proc/sys/kernel/ nmi_watchdog to keep it consistent. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ricardo Neri --- Changes since v6: * Introduced this patch Changes since v5: * N/A Changes since v4 * N/A Changes since v3 * N/A Changes since v2: * N/A Changes since v1: * N/A --- include/linux/nmi.h | 2 ++ kernel/watchdog.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/include/linux/nmi.h b/include/linux/nmi.h index a38c4509f9eb..40a97139ec65 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -83,9 +83,11 @@ static inline void reset_hung_task_detector(void) { } #if defined(CONFIG_HARDLOCKUP_DETECTOR) extern void hardlockup_detector_disable(void); +extern void hardlockup_detector_mark_unavailable(void); extern unsigned int hardlockup_panic; #else static inline void hardlockup_detector_disable(void) {} +static inline void hardlockup_detector_mark_unavailable(void) {} #endif #if defined(CONFIG_HAVE_NMI_WATCHDOG) || defined(CONFIG_HARDLOCKUP_DETECTOR) diff --git a/kernel/watchdog.c b/kernel/watchdog.c index 8e61f21e7e33..0e4fed6d95b9 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -47,6 +47,8 @@ static int __read_mostly nmi_watchdog_available; struct cpumask watchdog_cpumask __read_mostly; unsigned long *watchdog_cpumask_bits = cpumask_bits(&watchdog_cpumask); +static void __lockup_detector_reconfigure(void); + #ifdef CONFIG_HARDLOCKUP_DETECTOR # ifdef CONFIG_SMP @@ -85,6 +87,24 @@ static int __init hardlockup_panic_setup(char *str) } __setup("nmi_watchdog=", hardlockup_panic_setup); +/** + * hardlockup_detector_mark_unavailable - Mark the NMI watchdog as unavailable + * + * Indicate that the hardlockup detector has become unavailable. This may + * happen if the hardware resources that the detector uses have become + * unreliable. + */ +void hardlockup_detector_mark_unavailable(void) +{ + mutex_lock(&watchdog_mutex); + + /* These variables can be updated without stopping the detector. */ + nmi_watchdog_user_enabled = 0; + nmi_watchdog_available = false; + + __lockup_detector_reconfigure(); + mutex_unlock(&watchdog_mutex); +} #endif /* CONFIG_HARDLOCKUP_DETECTOR */ /* From patchwork Wed Mar 1 23:47:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1750283 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=X6wJbQaq; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PRrng5JhBz1yXC for ; Thu, 2 Mar 2023 10:59:51 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PRrng41mFz3fcr for ; Thu, 2 Mar 2023 10:59:51 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=X6wJbQaq; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=X6wJbQaq; dkim-atps=neutral Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4PRrJd4NJFz3cQV for ; Thu, 2 Mar 2023 10:38:09 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713889; x=1709249889; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=NR72OLVunS5t2SqSsi29lRMoOPaXNWEb1txH4+ymFL0=; b=X6wJbQaqhjvo00wTDr3+7lf39mp6PXHSrKhM9MvuqMpqyr2aXbo2jkmW 2X7l4JrnDIotQ33Q0IxM6LcfAAYpkAqDCuQKMx5Ht7IUVPsXKYi4D/ALB MsQ9sg53psP3JSjOlnPaZhxikhNEf3RTDeN2k9Lgkmsuo3OxdkS6FY1Gh NKmQ0TaOTWB4bx06kIrMzhLx1sud8ZHJzfOTdWbYF/dtTXDnpHblRGHC6 bjjzYWKvkdeqG9PFpOvm+qTbn77PVN58GjyIkKnj4v9V2g+7yfa6/zWMK 3wzTsHE+cMOf7NeUEnsC5bgZ9QTykiJs+Me4yX0LGjgI7yEWtOsDR9ubR w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818805" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818805" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:38:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826877" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826877" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:38:01 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Subject: [PATCH v7 24/24] x86/tsc: Stop the HPET hardlockup detector if TSC become unstable Date: Wed, 1 Mar 2023 15:47:53 -0800 Message-Id: <20230301234753.28582-25-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , Ricardo Neri , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The HPET-based hardlockup detector relies on the TSC to determine if an observed NMI interrupt was originated by HPET timer. Hence, this detector can no longer be used with an unstable TSC. Once marked as unstable, the TSC cannot be stable again. In such case, permanently stop the HPET- based hardlockup detector. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Do not switch to the perf-based NMI watchdog. Instead, only stop the HPET-based NMI watchdog if the TSC counter becomes unstable. Changes since v5: * Relocated the declaration of hardlockup_detector_switch_to_perf() to x86/nmi.h It does not depend on HPET. * Removed function stub. The shim hardlockup detector is always for x86. Changes since v4: * Added a stub version of hardlockup_detector_switch_to_perf() for !CONFIG_HPET_TIMER. (lkp) * Reconfigure the whole lockup detector instead of unconditionally starting the perf-based hardlockup detector. Changes since v3: * None Changes since v2: * Introduced this patch. Changes since v1: * N/A --- arch/x86/include/asm/nmi.h | 6 ++++++ arch/x86/kernel/tsc.c | 3 +++ arch/x86/kernel/watchdog_hld.c | 11 +++++++++++ 3 files changed, 20 insertions(+) diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index 5c5f1e56c404..4d0687a2b4ea 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -63,4 +63,10 @@ void stop_nmi(void); void restart_nmi(void); void local_touch_nmi(void); +#ifdef CONFIG_HARDLOCKUP_DETECTOR +extern void hardlockup_detector_mark_hpet_hld_unavailable(void); +#else +static inline void hardlockup_detector_mark_hpet_hld_unavailable(void) {} +#endif + #endif /* _ASM_X86_NMI_H */ diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 344698852146..24f77efea569 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1191,6 +1191,9 @@ void mark_tsc_unstable(char *reason) clocksource_mark_unstable(&clocksource_tsc_early); clocksource_mark_unstable(&clocksource_tsc); + + /* The HPET hardlockup detector depends on a stable TSC. */ + hardlockup_detector_mark_hpet_hld_unavailable(); } EXPORT_SYMBOL_GPL(mark_tsc_unstable); diff --git a/arch/x86/kernel/watchdog_hld.c b/arch/x86/kernel/watchdog_hld.c index 33c22f6456a3..f5d79ce0e7a2 100644 --- a/arch/x86/kernel/watchdog_hld.c +++ b/arch/x86/kernel/watchdog_hld.c @@ -6,6 +6,8 @@ * Copyright (C) Intel Corporation 2023 */ +#define pr_fmt(fmt) "watchdog: " fmt + #include #include @@ -84,3 +86,12 @@ void watchdog_nmi_start(void) if (detector_type == X86_HARDLOCKUP_DETECTOR_HPET) hardlockup_detector_hpet_start(); } + +void hardlockup_detector_mark_hpet_hld_unavailable(void) +{ + if (detector_type != X86_HARDLOCKUP_DETECTOR_HPET) + return; + + pr_warn("TSC is unstable. Stopping the HPET NMI watchdog."); + hardlockup_detector_mark_unavailable(); +}