From patchwork Sat Feb 25 08:38:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1747749 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.a=rsa-sha256 header.s=google header.b=XZrLfkxc; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PP0YL3JF0z2466 for ; Sat, 25 Feb 2023 19:39:18 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E0063809A5; Sat, 25 Feb 2023 09:38:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="XZrLfkxc"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0466985B68; Sat, 25 Feb 2023 09:38:42 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 51D3485B84 for ; Sat, 25 Feb 2023 09:38:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dario.binacchi@amarulasolutions.com Received: by mail-ed1-x536.google.com with SMTP id d30so6416431eda.4 for ; Sat, 25 Feb 2023 00:38:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ziR30gGYbNwF+BWVCTJGgGS6T2Wya5Vb2HBNyjs4l0M=; b=XZrLfkxc4O69pl0OdbYBBhAdrqTpwpBRxTbG5sHP3aHUpZd3tFU70HmBX4NwhkpTRi AHSdDfI2JGM2hkJOXfeA/VlwUhXLuR6OxUbiJEQgHkN3xTZPMFbgcn5xKbIzZ92ZB5HK XAQ+2qIVO+iq+jMLvDDKcoG0HkQoJjw3AbKjA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ziR30gGYbNwF+BWVCTJGgGS6T2Wya5Vb2HBNyjs4l0M=; b=VZSJEn5Qs9qsVtIHBt3lsXtUSWlt1eEQmmn+rdw902SxZ2a0Nys8fmh37ZxaoBTiMl ic980GbTz7Q1MGqe2YgiJibuUZDfrEy2vYEcrE/45mntNX2aogz3ZLVzO3Yfo83vozxz Q6FnTaOkMCklSzvUjIICL3T9Q5TEf+UkQQG365tF37bWxIyLUNNQ/L/1il+Ts4yPl9zi ALiwbeCmOrInZF4LQTtrhhUMApHJycaDViU/q+0+AkiNhYuNjTqLUvEgDVS6du/II0BL 5cAmk6vCdA+J5dnVPGtU12pyRlP8pTcinnbmqdHdYiuY1yIehtRjmw1de03nVt4NmeE7 kT1w== X-Gm-Message-State: AO0yUKUywFCUJSu6ZMSrXgOgod/p+FkaLXIHV94juXA9JQVuq7oLH3Ft fTPq/OJ2byjWwuEJmPT/oObBFn0h3Hfr/e6oz9Y= X-Google-Smtp-Source: AK7set9E+UVbYQvL+RdmDUFTYMl4QbWvAfYrMqTrWk0U/DA44HhGVpWTqPZFz+butjXvXumiEoserA== X-Received: by 2002:a17:907:8b85:b0:8ee:babc:d40b with SMTP id tb5-20020a1709078b8500b008eebabcd40bmr8113130ejc.58.1677314314702; Sat, 25 Feb 2023 00:38:34 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-56-22-12.retail.telecomitalia.it. [82.56.22.12]) by smtp.gmail.com with ESMTPSA id u20-20020a170906655400b008f2b0c6052csm591958ejn.89.2023.02.25.00.38.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Feb 2023 00:38:34 -0800 (PST) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , linux-amarula@amarulasolutions.com, Dario Binacchi , Fabio Estevam , "NXP i.MX U-Boot Team" , Stefano Babic Subject: [PATCH 1/3] imx6: clock: improve calculations to get the PLL video rate Date: Sat, 25 Feb 2023 09:38:19 +0100 Message-Id: <20230225083821.472605-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230225083821.472605-1-dario.binacchi@amarulasolutions.com> References: <20230225083821.472605-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean During some tests to check the pixel clock rate in the transition from U-Boot to the Linux kernel, I noticed that with the same configuration of the registers the debug messages reported different rates. The same Linux kernel calculations are now used to get the PLL video rate. Signed-off-by: Dario Binacchi Reviewed-by: Michael Trimarchi --- arch/arm/mach-imx/mx6/clock.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index cb9d629be408..17d8dcd5c841 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -213,6 +213,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num) static u32 decode_pll(enum pll_clocks pll, u32 infreq) { u32 div, test_div, pll_num, pll_denom; + u64 temp64; switch (pll) { case PLL_SYS: @@ -272,7 +273,10 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) } test_div = 1 << (2 - test_div); - return infreq * (div + pll_num / pll_denom) / test_div; + temp64 = (u64)infreq; + temp64 *= pll_num; + do_div(temp64, pll_denom); + return infreq * div + (unsigned long)temp64; default: return 0; } From patchwork Sat Feb 25 08:38:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1747750 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[82.56.22.12]) by smtp.gmail.com with ESMTPSA id u20-20020a170906655400b008f2b0c6052csm591958ejn.89.2023.02.25.00.38.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Feb 2023 00:38:35 -0800 (PST) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , linux-amarula@amarulasolutions.com, Dario Binacchi , Fabio Estevam , "NXP i.MX U-Boot Team" , Stefano Babic Subject: [PATCH 2/3] imx6: clock: add support to get LCD pixel clock rate Date: Sat, 25 Feb 2023 09:38:20 +0100 Message-Id: <20230225083821.472605-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230225083821.472605-1-dario.binacchi@amarulasolutions.com> References: <20230225083821.472605-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add the get_lcd_clk() function to get the LCD pixel clock rate. The patch has been tested on imx6ul platform. Signed-off-by: Dario Binacchi --- arch/arm/include/asm/arch-mx6/clock.h | 2 + arch/arm/mach-imx/mx6/clock.c | 58 +++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 8ae49715789c..81af89c631f5 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -41,6 +41,8 @@ enum mxc_clock { MXC_SATA_CLK, MXC_NFC_CLK, MXC_I2C_CLK, + MXC_LCDIF1_CLK, + MXC_LCDIF2_CLK, }; enum ldb_di_clock { diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 17d8dcd5c841..267d86ab4194 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -418,6 +418,60 @@ static u32 get_uart_clk(void) return freq / (uart_podf + 1); } +static u32 get_lcd_clk(unsigned int ifnum) +{ + u32 pll_rate; + u32 pred, postd; + + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() && + !is_mx6sll()) { + debug("This chip does't support lcd\n"); + return 0; + } + + pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK); + if (ifnum == 1) { + if (!is_mx6sl()) { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cbcmr); + postd &= MXC_CCM_CBCMR_LCDIF1_PODF_MASK; + postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET; + } else { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cscmr1); + postd &= MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET; + postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET; + } + } else if (ifnum == 2) { + if (is_mx6sx()) { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cscmr1); + postd &= MXC_CCM_CSCMR1_LCDIF2_PODF_MASK; + postd = postd >> MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET; + + } else { + goto if_err; + } + } else { + goto if_err; + } + + return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1)); + +if_err: + debug("This chip not support lcd iterface %d\n", ifnum); + return 0; +} + static u32 get_cspi_clk(void) { u32 reg, cspi_podf; @@ -1273,6 +1327,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_usdhc_clk(3); case MXC_SATA_CLK: return get_ahb_clk(); + case MXC_LCDIF1_CLK: + return get_lcd_clk(1); + case MXC_LCDIF2_CLK: + return get_lcd_clk(2); default: printf("Unsupported MXC CLK: %d\n", clk); break; From patchwork Sat Feb 25 08:38:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1747751 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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[82.56.22.12]) by smtp.gmail.com with ESMTPSA id u20-20020a170906655400b008f2b0c6052csm591958ejn.89.2023.02.25.00.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Feb 2023 00:38:36 -0800 (PST) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lukasz Majewski , Sean Anderson , linux-amarula@amarulasolutions.com, Dario Binacchi , Fabio Estevam , "NXP i.MX U-Boot Team" , Stefano Babic Subject: [PATCH 3/3] imx6: clock: print real pixel clock rate Date: Sat, 25 Feb 2023 09:38:21 +0100 Message-Id: <20230225083821.472605-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230225083821.472605-1-dario.binacchi@amarulasolutions.com> References: <20230225083821.472605-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add debug messages to print the real pixel clock rate, which may not be the requested one. Signed-off-by: Dario Binacchi --- arch/arm/mach-imx/mx6/clock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 267d86ab4194..1bdc568f9b14 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -802,6 +802,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) } enable_lcdif_clock(base_addr, 1); + debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF1_CLK)); } else if (is_mx6sx()) { /* Setting LCDIF2 for i.MX6SX */ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) @@ -823,6 +824,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET)); enable_lcdif_clock(base_addr, 1); + debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF2_CLK)); } }