From patchwork Thu Feb 9 11:06:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yulong X-Patchwork-Id: 1739882 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PCDb70ydsz23hX for ; Thu, 9 Feb 2023 22:06:58 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 00F47385B516 for ; Thu, 9 Feb 2023 11:06:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id EA3A63858C50 for ; Thu, 9 Feb 2023 11:06:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EA3A63858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [43.139.163.53]) by APP-01 (Coremail) with SMTP id qwCowABXcNS20+RjQ2g2BA--.63625S3; Thu, 09 Feb 2023 19:06:31 +0800 (CST) From: shiyulong@iscas.ac.cn To: gcc-patches@gcc.gnu.org Cc: andrew@sifive.com, palmer@dabbelt.com, kito.cheng@gmail.com, jim.wilson.gcc@gmail.com, philipp.tomsich@vrull.eu, research_trasio@irq.a4lg.com, wuwei2016@iscas.ac.cn, jiawei@iscas.ac.cn, shihua@iscas.ac.cn, chenyixuan@iscas.ac.cn, yulong Subject: [PATCH V1 1/1] UNRATIFIED RISC-V: Add 'ZiCond' extension Date: Thu, 9 Feb 2023 19:06:17 +0800 Message-Id: <20230209110617.3370-2-shiyulong@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230209110617.3370-1-shiyulong@iscas.ac.cn> References: <20230209110617.3370-1-shiyulong@iscas.ac.cn> X-CM-TRANSID: qwCowABXcNS20+RjQ2g2BA--.63625S3 X-Coremail-Antispam: 1UD129KBjvJXoW3Gr1rKw1rKryxWw4DJryrZwb_yoWfXw1Upa yUGw45Aa4rZFnxWw4ftF1UG34rAwnagw1Fkwn7ur4UAw4UXrWkAFn8Kw17Xr4DXFs8Jr1I 93WYkFyY9w4jy3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmq14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7M4kE6xkIj40Ew7xC0wCY02Avz4vEOx0_Gw4l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC 6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWw C2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_ JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJV WUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIY CTnIWIevJa73UjIFyTuYvjfU0T5lDUUUU X-Originating-IP: [43.139.163.53] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong [DO NOT MERGE] Until 'ZiCond' extension is frozen/ratified and final version number is determined, this patch should not be merged upstream. This commit uses version 1.0 as in the documentation. This commit adds support for the latest draft of RISC-V Integer Conditional (ZiCond) extension consisting of 2 new instructions. This is based on the early draft of ZiCond on GitHub: gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zicond ext. * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New. (AVAIL): New. (RISCV_FTYPE_ATYPES2): New. * config/riscv/riscv-ftypes.def (2): New. * config/riscv/riscv-opts.h (MASK_ZICOND): New. (TARGET_ZICOND): New. * config/riscv/riscv.md (riscv_eqz_): Add new mode. (riscv_nez_): Add new mode. * config/riscv/riscv.opt: New. * config/riscv/riscv-zicond.def: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-1.c: New test. * gcc.target/riscv/zicond-2.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 4 ++++ gcc/config/riscv/riscv-builtins.cc | 8 ++++++++ gcc/config/riscv/riscv-ftypes.def | 2 ++ gcc/config/riscv/riscv-opts.h | 3 +++ gcc/config/riscv/riscv-zicond.def | 5 +++++ gcc/config/riscv/riscv.md | 22 ++++++++++++++++++++++ gcc/config/riscv/riscv.opt | 3 +++ gcc/testsuite/gcc.target/riscv/zicond-1.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/riscv/zicond-2.c | 15 +++++++++++++++ 9 files changed, 77 insertions(+) create mode 100644 gcc/config/riscv/riscv-zicond.def create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-2.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 787674003cb..5a8b1278ac8 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -190,6 +190,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicond",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1209,6 +1211,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM}, {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, + {"zicond", &gcc_options::x_riscv_zicond_subext, MASK_ZICOND}, + {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve64x", &gcc_options::x_target_flags, MASK_VECTOR}, diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 25ca407f9a9..66a8126b2b4 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -42,6 +42,7 @@ along with GCC; see the file COPYING3. If not see /* Macros to create an enumeration identifier for a function prototype. */ #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B +#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C /* Classifies the prototype of a built-in function. */ enum riscv_function_type { @@ -99,6 +100,10 @@ AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT) AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT) AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT) AVAIL (always, (!0)) +AVAIL (nez32, TARGET_ZICOND && !TARGET_64BIT) +AVAIL (nez64, TARGET_ZICOND && TARGET_64BIT) +AVAIL (eqz32, TARGET_ZICOND && !TARGET_64BIT) +AVAIL (eqz64, TARGET_ZICOND && TARGET_64BIT) /* Construct a riscv_builtin_description from the given arguments. @@ -142,9 +147,12 @@ AVAIL (always, (!0)) RISCV_ATYPE_##A #define RISCV_FTYPE_ATYPES1(A, B) \ RISCV_ATYPE_##A, RISCV_ATYPE_##B +#define RISCV_FTYPE_ATYPES2(A, B, C) \ + RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C static const struct riscv_builtin_description riscv_builtins[] = { #include "riscv-cmo.def" + #include "riscv-zicond.def" DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float), DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float), diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 3a40c33e7c2..d305282d811 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -32,3 +32,5 @@ DEF_RISCV_FTYPE (1, (VOID, USI)) DEF_RISCV_FTYPE (1, (VOID, VOID_PTR)) DEF_RISCV_FTYPE (1, (SI, SI)) DEF_RISCV_FTYPE (1, (DI, DI)) +DEF_RISCV_FTYPE (2, (SI, SI, SI)) +DEF_RISCV_FTYPE (2, (DI, DI, DI)) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index ff398c0a2ae..0baf6553913 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -166,6 +166,9 @@ enum stack_protector_guard { #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0) #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0) +#define MASK_ZICOND (1 << 0) +#define TARGET_ZICOND ((riscv_zicond_subext & MASK_ZICOND) != 0) + #define MASK_ZFHMIN (1 << 0) #define MASK_ZFH (1 << 1) diff --git a/gcc/config/riscv/riscv-zicond.def b/gcc/config/riscv/riscv-zicond.def new file mode 100644 index 00000000000..ceacb825933 --- /dev/null +++ b/gcc/config/riscv/riscv-zicond.def @@ -0,0 +1,5 @@ +RISCV_BUILTIN (nez_si, "zicond_nez", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, nez32), +RISCV_BUILTIN (nez_di, "zicond_nez", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, nez64), + +RISCV_BUILTIN (eqz_si, "zicond_eqz", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, eqz32), +RISCV_BUILTIN (eqz_di, "zicond_eqz", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, eqz64), \ No newline at end of file diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c8adc5af5d2..1b1979df0c9 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -98,6 +98,10 @@ UNSPECV_ZERO UNSPECV_PREI + ;;ZICOND instructions + UNSPECV_EQZ + UNSPECV_NEZ + ;; Zihintpause unspec UNSPECV_PAUSE ]) @@ -3085,6 +3089,24 @@ "prefetch.i\t%a0" ) +(define_insn "riscv_eqz_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec_volatile:X [(match_operand:X 1 "register_operand" " r") + (match_operand:X 2 "register_operand" " r")] + UNSPECV_EQZ))] + "TARGET_ZICOND" + "czero.eqz\t%0,%1,%2" +) + +(define_insn "riscv_nez_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec_volatile:X [(match_operand:X 1 "register_operand" " r") + (match_operand:X 2 "register_operand" " r")] + UNSPECV_NEZ))] + "TARGET_ZICOND" + "czero.nez\t%0,%1,%2" +) + (include "bitmanip.md") (include "sync.md") (include "peephole.md") diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index e78c99382cd..a422b16a02f 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -224,6 +224,9 @@ int riscv_zvl_flags TargetVariable int riscv_zicmo_subext +TargetVariable +int riscv_zicond_subext + TargetVariable int riscv_zf_subext diff --git a/gcc/testsuite/gcc.target/riscv/zicond-1.c b/gcc/testsuite/gcc.target/riscv/zicond-1.c new file mode 100644 index 00000000000..395e53f870f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zicond -mabi=ilp32" } */ + +void foo1() +{ + __builtin_riscv_zicond_nez(1,1); +} + +void foo2() +{ + __builtin_riscv_zicond_eqz(1,1); +} + +/* { dg-final { scan-assembler-times "czero.nez" 1 } } */ +/* { dg-final { scan-assembler-times "czero.eqz" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-2.c b/gcc/testsuite/gcc.target/riscv/zicond-2.c new file mode 100644 index 00000000000..4ae01cb8bfa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_zicond -mabi=lp64" } */ + +void foo1() +{ + __builtin_riscv_zicond_nez(1,1); +} + +void foo2() +{ + __builtin_riscv_zicond_eqz(1,1); +} + +/* { dg-final { scan-assembler-times "czero.nez" 1 } } */ +/* { dg-final { scan-assembler-times "czero.eqz" 1 } } */