From patchwork Tue Jan 31 12:18:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 1734813 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4P5kcG088Dz23gV for ; Tue, 31 Jan 2023 23:18:52 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4F5AD385B504 for ; Tue, 31 Jan 2023 12:18:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id 3134F3858D28 for ; Tue, 31 Jan 2023 12:18:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3134F3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp78t1675167502tbocrpap Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 31 Jan 2023 20:18:21 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: 1VT9TMQFSYvQn/UzBCy2zod379fzK0hmCIdQLm3fXF7Bidik5yYZ0L91h9P6r 8jhyJTjCL11jq0ef7S8wf+X+/+QNizNyBnO+/Znc0gCqVhu3ASuWWRo5zYqDOCfizI3z1li wK1zIEazFxBdWDyg6nrYXSSPJeZUB78QWfvwuJWgxdQxm9wxDXp7LvJ6YqeBsvKingv7YWK sbXxx2G5QhjYirGOHtcE4zu08m22xCV1Hpb5qxMz+k7UNEvNMt1vehHqsatFMXuoG1V7CZB v1d0sT44eKkaduMDoc4MmsrCM1TASgDvduud0MBEACjbWvc2NU6d0sPGAHhFImS8kitode5 5OHIsqv83ocaBkkAKhqUncFAnNNyBVurUIfb8fXgujNFF9Gm6Tig5FEOf44L45M2lZKCekY X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vsra.vv C API tests Date: Tue, 31 Jan 2023 20:18:20 +0800 Message-Id: <20230131121820.303684-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vsra_vv-1.c: New test. * gcc.target/riscv/rvv/base/vsra_vv-2.c: New test. * gcc.target/riscv/rvv/base/vsra_vv-3.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vsra_vv_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vsra_vv-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_m-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_m-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_m-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_mu-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_mu-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_mu-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_tu-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_tu-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_tu-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_tum-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_tum-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsra_vv_tum-3.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vsra_vv_tumu-1.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vsra_vv_tumu-2.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vsra_vv_tumu-3.c | 160 ++++++++++++++++++ 18 files changed, 2880 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-1.c new file mode 100644 index 00000000000..01dee8d57fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8(vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8(op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4(vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4(op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2(vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2(op1,shift,vl); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1(vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1(op1,shift,vl); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2(vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2(op1,shift,vl); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4(vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4(op1,shift,vl); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8(vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8(op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4(vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4(op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2(vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2(op1,shift,vl); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1(vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1(op1,shift,vl); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2(vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2(op1,shift,vl); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4(vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4(op1,shift,vl); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8(vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8(op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2(vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2(op1,shift,vl); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1(vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1(op1,shift,vl); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2(vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2(op1,shift,vl); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4(vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4(op1,shift,vl); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8(vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8(op1,shift,vl); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1(vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1(op1,shift,vl); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2(vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2(op1,shift,vl); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4(vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4(op1,shift,vl); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8(vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8(op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-2.c new file mode 100644 index 00000000000..5f8b50a63e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8(vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8(op1,shift,31); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4(vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4(op1,shift,31); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2(vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2(op1,shift,31); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1(vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1(op1,shift,31); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2(vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2(op1,shift,31); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4(vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4(op1,shift,31); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8(vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8(op1,shift,31); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4(vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4(op1,shift,31); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2(vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2(op1,shift,31); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1(vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1(op1,shift,31); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2(vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2(op1,shift,31); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4(vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4(op1,shift,31); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8(vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8(op1,shift,31); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2(vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2(op1,shift,31); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1(vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1(op1,shift,31); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2(vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2(op1,shift,31); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4(vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4(op1,shift,31); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8(vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8(op1,shift,31); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1(vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1(op1,shift,31); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2(vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2(op1,shift,31); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4(vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4(op1,shift,31); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8(vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8(op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-3.c new file mode 100644 index 00000000000..583cbbbbc26 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8(vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8(op1,shift,32); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4(vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4(op1,shift,32); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2(vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2(op1,shift,32); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1(vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1(op1,shift,32); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2(vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2(op1,shift,32); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4(vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4(op1,shift,32); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8(vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8(op1,shift,32); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4(vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4(op1,shift,32); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2(vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2(op1,shift,32); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1(vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1(op1,shift,32); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2(vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2(op1,shift,32); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4(vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4(op1,shift,32); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8(vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8(op1,shift,32); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2(vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2(op1,shift,32); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1(vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1(op1,shift,32); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2(vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2(op1,shift,32); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4(vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4(op1,shift,32); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8(vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8(op1,shift,32); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1(vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1(op1,shift,32); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2(vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2(op1,shift,32); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4(vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4(op1,shift,32); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8(vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8(op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-1.c new file mode 100644 index 00000000000..0dfa861ff6b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_m(mask,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_m(mask,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_m(mask,op1,shift,vl); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_m(mask,op1,shift,vl); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_m(mask,op1,shift,vl); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_m(mask,op1,shift,vl); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_m(mask,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_m(mask,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_m(mask,op1,shift,vl); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_m(mask,op1,shift,vl); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_m(mask,op1,shift,vl); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_m(mask,op1,shift,vl); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_m(mask,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_m(mask,op1,shift,vl); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_m(mask,op1,shift,vl); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_m(mask,op1,shift,vl); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_m(mask,op1,shift,vl); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_m(mask,op1,shift,vl); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_m(mask,op1,shift,vl); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_m(mask,op1,shift,vl); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_m(mask,op1,shift,vl); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_m(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-2.c new file mode 100644 index 00000000000..ac068e2831f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_m(mask,op1,shift,31); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_m(mask,op1,shift,31); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_m(mask,op1,shift,31); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_m(mask,op1,shift,31); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_m(mask,op1,shift,31); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_m(mask,op1,shift,31); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_m(mask,op1,shift,31); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_m(mask,op1,shift,31); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_m(mask,op1,shift,31); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_m(mask,op1,shift,31); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_m(mask,op1,shift,31); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_m(mask,op1,shift,31); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_m(mask,op1,shift,31); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_m(mask,op1,shift,31); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_m(mask,op1,shift,31); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_m(mask,op1,shift,31); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_m(mask,op1,shift,31); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_m(mask,op1,shift,31); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_m(mask,op1,shift,31); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_m(mask,op1,shift,31); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_m(mask,op1,shift,31); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_m(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-3.c new file mode 100644 index 00000000000..94bdae5468a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_m(mask,op1,shift,32); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_m(mask,op1,shift,32); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_m(mask,op1,shift,32); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_m(mask,op1,shift,32); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_m(mask,op1,shift,32); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_m(mask,op1,shift,32); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_m(mask,op1,shift,32); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_m(mask,op1,shift,32); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_m(mask,op1,shift,32); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_m(mask,op1,shift,32); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_m(mask,op1,shift,32); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_m(mask,op1,shift,32); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_m(mask,op1,shift,32); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_m(mask,op1,shift,32); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_m(mask,op1,shift,32); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_m(mask,op1,shift,32); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_m(mask,op1,shift,32); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_m(mask,op1,shift,32); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_m(mask,op1,shift,32); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_m(mask,op1,shift,32); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_m(mask,op1,shift,32); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_m(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-1.c new file mode 100644 index 00000000000..23f11f6941e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_mu(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_mu(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_mu(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_mu(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_mu(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_mu(mask,merge,op1,shift,vl); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_mu(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_mu(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_mu(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_mu(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_mu(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_mu(mask,merge,op1,shift,vl); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_mu(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_mu(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_mu(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_mu(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_mu(mask,merge,op1,shift,vl); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_mu(mask,merge,op1,shift,vl); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_mu(mask,merge,op1,shift,vl); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_mu(mask,merge,op1,shift,vl); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_mu(mask,merge,op1,shift,vl); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-2.c new file mode 100644 index 00000000000..089d438833c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_mu(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_mu(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_mu(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_mu(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_mu(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_mu(mask,merge,op1,shift,31); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_mu(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_mu(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_mu(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_mu(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_mu(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_mu(mask,merge,op1,shift,31); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_mu(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_mu(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_mu(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_mu(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_mu(mask,merge,op1,shift,31); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_mu(mask,merge,op1,shift,31); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_mu(mask,merge,op1,shift,31); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_mu(mask,merge,op1,shift,31); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_mu(mask,merge,op1,shift,31); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-3.c new file mode 100644 index 00000000000..7aa6d0b74d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_mu(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_mu(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_mu(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_mu(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_mu(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_mu(mask,merge,op1,shift,32); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_mu(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_mu(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_mu(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_mu(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_mu(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_mu(mask,merge,op1,shift,32); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_mu(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_mu(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_mu(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_mu(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_mu(mask,merge,op1,shift,32); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_mu(mask,merge,op1,shift,32); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_mu(mask,merge,op1,shift,32); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_mu(mask,merge,op1,shift,32); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_mu(mask,merge,op1,shift,32); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-1.c new file mode 100644 index 00000000000..2ceec88237e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_tu(merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_tu(merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_tu(merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_tu(merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_tu(merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_tu(merge,op1,shift,vl); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_tu(merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_tu(merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_tu(merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_tu(merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_tu(merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_tu(merge,op1,shift,vl); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_tu(merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_tu(merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_tu(merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_tu(merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_tu(merge,op1,shift,vl); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_tu(merge,op1,shift,vl); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_tu(merge,op1,shift,vl); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_tu(merge,op1,shift,vl); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_tu(merge,op1,shift,vl); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-2.c new file mode 100644 index 00000000000..8895d37b7b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_tu(merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_tu(merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_tu(merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_tu(merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_tu(merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_tu(merge,op1,shift,31); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_tu(merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_tu(merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_tu(merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_tu(merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_tu(merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_tu(merge,op1,shift,31); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_tu(merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_tu(merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_tu(merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_tu(merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_tu(merge,op1,shift,31); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_tu(merge,op1,shift,31); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_tu(merge,op1,shift,31); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_tu(merge,op1,shift,31); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_tu(merge,op1,shift,31); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-3.c new file mode 100644 index 00000000000..d26847ef583 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_tu(merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_tu(merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_tu(merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_tu(merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_tu(merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_tu(merge,op1,shift,32); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_tu(merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_tu(merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_tu(merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_tu(merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_tu(merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_tu(merge,op1,shift,32); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_tu(merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_tu(merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_tu(merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_tu(merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_tu(merge,op1,shift,32); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_tu(merge,op1,shift,32); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_tu(merge,op1,shift,32); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_tu(merge,op1,shift,32); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_tu(merge,op1,shift,32); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-1.c new file mode 100644 index 00000000000..8211863b7be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_tum(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_tum(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_tum(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_tum(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_tum(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_tum(mask,merge,op1,shift,vl); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_tum(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_tum(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_tum(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_tum(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_tum(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_tum(mask,merge,op1,shift,vl); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_tum(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_tum(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_tum(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_tum(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_tum(mask,merge,op1,shift,vl); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_tum(mask,merge,op1,shift,vl); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_tum(mask,merge,op1,shift,vl); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_tum(mask,merge,op1,shift,vl); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_tum(mask,merge,op1,shift,vl); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-2.c new file mode 100644 index 00000000000..bce925ec7a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_tum(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_tum(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_tum(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_tum(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_tum(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_tum(mask,merge,op1,shift,31); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_tum(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_tum(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_tum(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_tum(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_tum(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_tum(mask,merge,op1,shift,31); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_tum(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_tum(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_tum(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_tum(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_tum(mask,merge,op1,shift,31); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_tum(mask,merge,op1,shift,31); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_tum(mask,merge,op1,shift,31); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_tum(mask,merge,op1,shift,31); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_tum(mask,merge,op1,shift,31); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-3.c new file mode 100644 index 00000000000..8eec0de0743 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_tum(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_tum(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_tum(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_tum(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_tum(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_tum(mask,merge,op1,shift,32); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_tum(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_tum(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_tum(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_tum(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_tum(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_tum(mask,merge,op1,shift,32); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_tum(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_tum(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_tum(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_tum(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_tum(mask,merge,op1,shift,32); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_tum(mask,merge,op1,shift,32); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_tum(mask,merge,op1,shift,32); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_tum(mask,merge,op1,shift,32); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_tum(mask,merge,op1,shift,32); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-1.c new file mode 100644 index 00000000000..0f87991436a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_tumu(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_tumu(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_tumu(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_tumu(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_tumu(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_tumu(mask,merge,op1,shift,vl); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_tumu(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_tumu(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_tumu(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_tumu(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_tumu(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_tumu(mask,merge,op1,shift,vl); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_tumu(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_tumu(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_tumu(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_tumu(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_tumu(mask,merge,op1,shift,vl); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_tumu(mask,merge,op1,shift,vl); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_tumu(mask,merge,op1,shift,vl); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_tumu(mask,merge,op1,shift,vl); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_tumu(mask,merge,op1,shift,vl); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-2.c new file mode 100644 index 00000000000..49dd44fe5cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_tumu(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_tumu(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_tumu(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_tumu(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_tumu(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_tumu(mask,merge,op1,shift,31); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_tumu(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_tumu(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_tumu(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_tumu(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_tumu(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_tumu(mask,merge,op1,shift,31); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_tumu(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_tumu(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_tumu(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_tumu(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_tumu(mask,merge,op1,shift,31); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_tumu(mask,merge,op1,shift,31); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_tumu(mask,merge,op1,shift,31); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_tumu(mask,merge,op1,shift,31); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_tumu(mask,merge,op1,shift,31); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-3.c new file mode 100644 index 00000000000..5403c7c2510 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsra_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf8_tumu(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vsra_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf4_tumu(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vsra_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8mf2_tumu(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vsra_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m1_tumu(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vsra_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m2_tumu(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vsra_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m4_tumu(mask,merge,op1,shift,32); +} + + +vint8m8_t test___riscv_vsra_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i8m8_tumu(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vsra_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf4_tumu(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vsra_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16mf2_tumu(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vsra_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m1_tumu(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vsra_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m2_tumu(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vsra_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m4_tumu(mask,merge,op1,shift,32); +} + + +vint16m8_t test___riscv_vsra_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i16m8_tumu(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vsra_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32mf2_tumu(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vsra_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m1_tumu(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vsra_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m2_tumu(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vsra_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m4_tumu(mask,merge,op1,shift,32); +} + + +vint32m8_t test___riscv_vsra_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i32m8_tumu(mask,merge,op1,shift,32); +} + + +vint64m1_t test___riscv_vsra_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m1_tumu(mask,merge,op1,shift,32); +} + + +vint64m2_t test___riscv_vsra_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m2_tumu(mask,merge,op1,shift,32); +} + + +vint64m4_t test___riscv_vsra_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m4_tumu(mask,merge,op1,shift,32); +} + + +vint64m8_t test___riscv_vsra_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsra_vv_i64m8_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */