From patchwork Fri Jan 27 10:39:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 1732782 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=eyfCMQzw; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4P3Dc432bZz23hp for ; Fri, 27 Jan 2023 21:40:04 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 731BD3858436 for ; Fri, 27 Jan 2023 10:40:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 731BD3858436 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1674816000; bh=GpmzcMSnm0dJb3Xtv3WX/X6Ac5mtymVFzPibRkCRrow=; h=Date:To:Cc:Subject:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=eyfCMQzwM+q8lyO+qS7aYq95SQVurMbdSfQpRSosbDnWai5W2cts/DOPs/vM+kvJc 7fiuXxYkg+XpT+7PcBUWRmkv3qEbYSRId1Fi4MDXCoGtuNsmWZMzz4KwiMdVwAnKIL Z5kuNbl+no70LyJZQyp31Au50iz576bhiJg07QEA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2089.outbound.protection.outlook.com [40.107.6.89]) by sourceware.org (Postfix) with ESMTPS id 3340E3858C74 for ; Fri, 27 Jan 2023 10:39:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3340E3858C74 Received: from AM6PR02CA0022.eurprd02.prod.outlook.com (2603:10a6:20b:6e::35) by PAXPR08MB6608.eurprd08.prod.outlook.com (2603:10a6:102:150::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.23; Fri, 27 Jan 2023 10:39:36 +0000 Received: from AM7EUR03FT034.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:6e:cafe::bb) by AM6PR02CA0022.outlook.office365.com (2603:10a6:20b:6e::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.34 via Frontend Transport; Fri, 27 Jan 2023 10:39:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT034.mail.protection.outlook.com (100.127.140.87) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.22 via Frontend Transport; Fri, 27 Jan 2023 10:39:36 +0000 Received: ("Tessian outbound b1d3ffe56e73:v132"); Fri, 27 Jan 2023 10:39:36 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 6809ff6d8c57b3e2 X-CR-MTA-TID: 64aa7808 Received: from 501651a644e8.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id F663A4EC-F914-4683-9262-20115014810C.1; Fri, 27 Jan 2023 10:39:29 +0000 Received: from EUR04-DB3-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 501651a644e8.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 27 Jan 2023 10:39:29 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Sqa3y3MtNWJSwL34Ii4U8NygdBO8ZJoBq+t9FP9pKxZVe1ToCoXWJDGwN5ImKecHKfRNHcTOo8I0RGrEBg4hEBbGU4c00h4jj8SpmN3F6XePLvXFM67B61NvBFrur0NckCaIC6Y8GYU0lnnbmiC6DmXfj3SkLjH1tewY9gMe/+s6KlC6rl20BbC3idCCZL6nW+WIa76EcBMZxkM7iIgoypcGsee0nMY3K/5y9b0Y3VKZHKqYGOmb5yfy0FIS6nbSIb8ZzLL5hDxlCSjZWogDDfkxy9Kq0AjGy0AIXu14TxtIvPME5hRkArgE6EjGvR5okSamzFV9JDFWW5Up4bcD0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GpmzcMSnm0dJb3Xtv3WX/X6Ac5mtymVFzPibRkCRrow=; b=Wek/lTmG5+SMQ8V8CPpck0eTwzOL8E5O5t0xQ/OnPbdq+HToBMLDHmfMrYkT3+jZ5N471ZZzTjbawaePIxkSLpI19uHNRoQufsrfSp+1QNt9hwxukG+LDSzer4l9PMZ0vAlAZUJmelibGwGRw4hmw2N9pJ/12zXC941MvvLiIEapBLe5ldyCjILdPvjtz1d9GAtR5thEnz8k0X8B/6RS0zcK+DQhucDrxxOOvxnWhph1gNo5x7pdOX3YJVsRNDneFxFvXjaMQXk98su3gIDkDIGqosA6gMu5ufwnS5Yfcoz0FVqxumi4MGp6YWZ8iiSdxfHoYlAxZs4SCqdwnEY1UA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI1PR08MB5325.eurprd08.prod.outlook.com (2603:10a6:803:13e::17) by AM9PR08MB5876.eurprd08.prod.outlook.com (2603:10a6:20b:2d5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.23; Fri, 27 Jan 2023 10:39:28 +0000 Received: from VI1PR08MB5325.eurprd08.prod.outlook.com ([fe80::7e84:c35c:e966:c886]) by VI1PR08MB5325.eurprd08.prod.outlook.com ([fe80::7e84:c35c:e966:c886%9]) with mapi id 15.20.6043.023; Fri, 27 Jan 2023 10:39:28 +0000 Date: Fri, 27 Jan 2023 10:39:25 +0000 To: gcc-patches@gcc.gnu.org Cc: nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com Subject: [PATCH]AArch64: Fix codegen regressions around tbz. Message-ID: Content-Disposition: inline X-ClientProxiedBy: LO2P265CA0379.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a3::31) To VI1PR08MB5325.eurprd08.prod.outlook.com (2603:10a6:803:13e::17) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI1PR08MB5325:EE_|AM9PR08MB5876:EE_|AM7EUR03FT034:EE_|PAXPR08MB6608:EE_ X-MS-Office365-Filtering-Correlation-Id: 887ac194-ae75-4a95-6ace-08db0052c930 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: zPdP0uiKdF5kXzCPqC1s2rpdLAh7nDoKsHuuyA88r+hAZ/w3iR7HS2IUH5JUgdXvFS8zIjhhSzQKWea9grcYM2PhIQAkBALRL6sJiVnLTCWGEV5kTVSlHr7qiplVBxX5g5lvle3aT6m/rbCjlvV1oCB5hpPq6QFD/xvNpW6ejWH6iOMUq5vAN6V4YAfzia7UuYMo9QrtZgVbfp/GwQkTUj2g/uAG5rAWyIPtiVjibJD+xX2geUoE4t7ESCH3GSKo87zlEcWDbpNsph5OroGRbKGczzKRE8lsGlZbXDq8V+BDsXAUafALlmvQJWyiOR+kkwSTbvkYVxtj6D/feOsuVjl/C+YMbLx9DMhPqafRTucYLoVk17LgzqPwl+qONxl26to9nraKWXoKhwrb5i7Solfs2h2Y++4FZ9cVoa0/OdVqQN5cCKxS1WXr8ASZn3zPIMILdgWnnvUsDja+kE5FokgfXvvDV/PJZ67W5eVu7zBVoTZRvsL6t3oiYgL8WZh7paJ0O37lx8jh0220BXmub+8R2T4tyF0DEXX01LXJl1s9m3W8PPOGa9D+jyTIdW5vW99AMXeXqwZ9ZDXVgvRlE9rlkA2Zc594vmMWmKV3pmoKb9iFzfJ4BcyVARQz6KVCFGmcqq82Vk62ngT5FjkkeK6Rz++80AjdW+d/yJQC0F36o+Bpcdj57QiQ3rsVqnjrxFuK88Rb7QOv6tY6BeYFMvN9bBUMjUlZc4bowTu/h8QQPJzo3SSGUOzjMg++l0eo X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR08MB5325.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230025)(4636009)(376002)(366004)(396003)(346002)(136003)(39860400002)(451199018)(6666004)(41300700001)(36756003)(83380400001)(66476007)(66556008)(316002)(66946007)(4326008)(6916009)(478600001)(6486002)(86362001)(2616005)(8676002)(235185007)(26005)(186003)(6512007)(44832011)(2906002)(8936002)(5660300002)(33964004)(44144004)(38100700002)(6506007)(84970400001)(4216001)(2700100001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB5876 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: ab7613c7-64d4-4848-9421-08db0052c3fa X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tF8ZYXiD1IPJsVm+hnx1oZ8cgo1PwZtzYlLDrCEy0y/ZQYS50rl/wr8XKU3RxkNSdDxG234/+eFyEaaUFEp9XJGmHkyI7zBP3YLsoMqCSEK3QAJOvXNSHCuGiXYwROZfURBD9nO+1HzrlXS9RARtyZ9cXNgy956XrOtpWC45/12akw94b5eft+8i1TJBXyWGEuGxFvHiOFiKap4Q3ZGbNDX/Z8UL6mpZoGP4DVcr9QlMp5LPKrL+biS4DF08eHdQexuDEETmEIAoRThjJxRhyAgC+CI1EKmSKHzpi0S+uQor+KTcZzsuhp3vqCZ29saD46837ADC3SHfrwE11wKjkoDVFtZGIBndVrm1TiHFtppTlIv0DgXmtn3sFe4Q6OdLTXlzjL8Jp44pYmSFPx7oY5KjakNCbd+1KNX4KaMHqrpjajoW1NweZbcn87K61XamUcb6/sbCR9Zp+uRX4XJzxBDm2n2rsebfpYREmdxFFqdOTMuDnqu5p2JIZ/XvODATFCmjOi5LWUXvtc3XCeDvlye5jQhAPAavLbuMa8URV7DqUWFw1g+X/hVfcWew9KTnZ6FMYU+53Iw9iPTdF7/3fhD2/v4ORRDqLVAHGTM6lnd9THei1xKmpAovloQrfhxEmR6KLuFqwAuUaQQ4hBlugl+0PW4DRUPskXKpNg+7hkKb215OQQmfm/1TzpGGoGn3c5/LWfy/CD6m7CeGFlfI+PgrednK7VU5XnzExQFfBvVTSwNXsi2eLWUsy1ovofJgzbmcDL/JQbnVZ67GP0jS1pcv5dTPFaPzeb1+pJ+3U1A= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230025)(4636009)(396003)(376002)(39860400002)(346002)(136003)(451199018)(46966006)(40470700004)(36840700001)(6486002)(33964004)(6506007)(44144004)(478600001)(186003)(26005)(4326008)(6916009)(6512007)(84970400001)(8676002)(6666004)(70586007)(70206006)(336012)(82310400005)(41300700001)(2616005)(47076005)(83380400001)(2906002)(86362001)(8936002)(81166007)(40460700003)(36860700001)(82740400003)(36756003)(44832011)(40480700001)(5660300002)(316002)(356005)(235185007)(4216001)(2700100001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2023 10:39:36.4987 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 887ac194-ae75-4a95-6ace-08db0052c930 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6608 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tamar Christina via Gcc-patches From: Tamar Christina Reply-To: Tamar Christina Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi All, We were analyzing code quality after recent changes and have noticed that the tbz support somehow managed to increase the number of branches overall rather than decreased them. While investigating this we figured out that the problem is that when an existing & exists in gimple and the instruction is generated because of the range information gotten from the ANDed constant that we end up with the situation that you get a NOP AND in the RTL expansion. This is not a problem as CSE will take care of it normally. The issue is when this original AND was done in a location where PRE or FRE "lift" the AND to a different basic block. This triggers a problem when the resulting value is not single use. Instead of having an AND and tbz, we end up generating an AND + TST + BR if the mode is HI or QI. This CSE across BB was a problem before but this change made it worse. Our branch patterns rely on combine being able to fold AND or zero_extends into the instructions. To work around this (since a proper fix is outside of the scope of stage-4) we are limiting the new tbranch optab to only HI and QI mode values. This isn't a problem because these two modes are modes for which we don't have CBZ support, so they are the problematic cases to begin with. Additionally booleans are QI. The second thing we're doing is limiting the only legal bitpos to pos 0. i.e. only the bottom bit. This such that we prevent the double ANDs as much as possible. Now most other cases, i.e. where we had an explicit & in the source code are still handled correctly by the anonymous (*tb1) pattern that was added along with tbranch support. This means we don't expand the superflous AND here, and while it doesn't fix the problem that in the cross BB case we loss tbz, it also doesn't make things worse. With these tweaks we've now reduced the number of insn uniformly as originally expected. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64.md (tbranch_3): Restrict to SHORT and bottom bit only. gcc/testsuite/ChangeLog: * gcc.target/aarch64/tbz_2.c: New test. --- inline copy of patch -- diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 2c1367977a68fc8e4289118e07bb61398856791e..aa09e93d85e9628e8944e03498697eb9597ef867 100644 --- diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 2c1367977a68fc8e4289118e07bb61398856791e..aa09e93d85e9628e8944e03498697eb9597ef867 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -949,8 +949,8 @@ (define_insn "*cb1" (define_expand "tbranch_3" [(set (pc) (if_then_else - (EQL (match_operand:ALLI 0 "register_operand") - (match_operand 1 "aarch64_simd_shift_imm_")) + (EQL (match_operand:SHORT 0 "register_operand") + (match_operand 1 "const0_operand")) (label_ref (match_operand 2 "")) (pc)))] "" diff --git a/gcc/testsuite/gcc.target/aarch64/tbz_2.c b/gcc/testsuite/gcc.target/aarch64/tbz_2.c new file mode 100644 index 0000000000000000000000000000000000000000..ec128b58f35276a7c5452685a65c73f95f2d5f9a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tbz_2.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -std=c99 -fno-unwind-tables -fno-asynchronous-unwind-tables" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +#include + +void h(void); + +/* +** g1: +** cbnz w0, .L[0-9]+ +** ret +** ... +*/ +void g1(int x) +{ + if (__builtin_expect (x, 0)) + h (); +} + +/* +** g2: +** tbnz x0, 0, .L[0-9]+ +** ret +** ... +*/ +void g2(int x) +{ + if (__builtin_expect (x & 1, 0)) + h (); +} + +/* +** g3: +** tbnz x0, 3, .L[0-9]+ +** ret +** ... +*/ +void g3(int x) +{ + if (__builtin_expect (x & 8, 0)) + h (); +} + +/* +** g4: +** tbnz w0, #31, .L[0-9]+ +** ret +** ... +*/ +void g4(int x) +{ + if (__builtin_expect (x & (1 << 31), 0)) + h (); +} + +/* +** g5: +** tst w0, 255 +** bne .L[0-9]+ +** ret +** ... +*/ +void g5(char x) +{ + if (__builtin_expect (x, 0)) + h (); +} + +/* +** g6: +** tbnz w0, 0, .L[0-9]+ +** ret +** ... +*/ +void g6(char x) +{ + if (__builtin_expect (x & 1, 0)) + h (); +} + +/* +** g7: +** tst w0, 3 +** bne .L[0-9]+ +** ret +** ... +*/ +void g7(char x) +{ + if (__builtin_expect (x & 3, 0)) + h (); +} + +/* +** g8: +** tbnz w0, 7, .L[0-9]+ +** ret +** ... +*/ +void g8(char x) +{ + if (__builtin_expect (x & (1 << 7), 0)) + h (); +} + +/* +** g9: +** tbnz w0, 0, .L[0-9]+ +** ret +** ... +*/ +void g9(bool x) +{ + if (__builtin_expect (x, 0)) + h (); +} + +/* +** g10: +** tbnz w0, 0, .L[0-9]+ +** ret +** ... +*/ +void g10(bool x) +{ + if (__builtin_expect (x & 1, 0)) + h (); +} + --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -949,8 +949,8 @@ (define_insn "*cb1" (define_expand "tbranch_3" [(set (pc) (if_then_else - (EQL (match_operand:ALLI 0 "register_operand") - (match_operand 1 "aarch64_simd_shift_imm_")) + (EQL (match_operand:SHORT 0 "register_operand") + (match_operand 1 "const0_operand")) (label_ref (match_operand 2 "")) (pc)))] "" diff --git a/gcc/testsuite/gcc.target/aarch64/tbz_2.c b/gcc/testsuite/gcc.target/aarch64/tbz_2.c new file mode 100644 index 0000000000000000000000000000000000000000..ec128b58f35276a7c5452685a65c73f95f2d5f9a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tbz_2.c @@ -0,0 +1,130 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -std=c99 -fno-unwind-tables -fno-asynchronous-unwind-tables" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +#include + +void h(void); + +/* +** g1: +** cbnz w0, .L[0-9]+ +** ret +** ... +*/ +void g1(int x) +{ + if (__builtin_expect (x, 0)) + h (); +} + +/* +** g2: +** tbnz x0, 0, .L[0-9]+ +** ret +** ... +*/ +void g2(int x) +{ + if (__builtin_expect (x & 1, 0)) + h (); +} + +/* +** g3: +** tbnz x0, 3, .L[0-9]+ +** ret +** ... +*/ +void g3(int x) +{ + if (__builtin_expect (x & 8, 0)) + h (); +} + +/* +** g4: +** tbnz w0, #31, .L[0-9]+ +** ret +** ... +*/ +void g4(int x) +{ + if (__builtin_expect (x & (1 << 31), 0)) + h (); +} + +/* +** g5: +** tst w0, 255 +** bne .L[0-9]+ +** ret +** ... +*/ +void g5(char x) +{ + if (__builtin_expect (x, 0)) + h (); +} + +/* +** g6: +** tbnz w0, 0, .L[0-9]+ +** ret +** ... +*/ +void g6(char x) +{ + if (__builtin_expect (x & 1, 0)) + h (); +} + +/* +** g7: +** tst w0, 3 +** bne .L[0-9]+ +** ret +** ... +*/ +void g7(char x) +{ + if (__builtin_expect (x & 3, 0)) + h (); +} + +/* +** g8: +** tbnz w0, 7, .L[0-9]+ +** ret +** ... +*/ +void g8(char x) +{ + if (__builtin_expect (x & (1 << 7), 0)) + h (); +} + +/* +** g9: +** tbnz w0, 0, .L[0-9]+ +** ret +** ... +*/ +void g9(bool x) +{ + if (__builtin_expect (x, 0)) + h (); +} + +/* +** g10: +** tbnz w0, 0, .L[0-9]+ +** ret +** ... +*/ +void g10(bool x) +{ + if (__builtin_expect (x & 1, 0)) + h (); +} +