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Received: from mail.bootlin.com ([62.4.15.54]) by merlin.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1evhDM-0002WG-W7; Tue, 13 Mar 2018 10:31:30 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id 255D420873; Tue, 13 Mar 2018 11:31:12 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id B9D0920877; Tue, 13 Mar 2018 11:30:27 +0100 (CET) From: Gregory CLEMENT To: Boris Brezillon , Miquel Raynal , linux-mtd@lists.infradead.org Subject: [PATCH v3] mtd: nand: marvell: Fix clock resource by adding a register clock Date: Tue, 13 Mar 2018 11:30:16 +0100 Message-Id: <20180313103016.7695-1-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.16.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180313_063129_247154_F9DDE09B X-CRM114-Status: GOOD ( 19.78 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.1 on merlin.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Jason Cooper , Antoine Tenart , Gregory CLEMENT , Omri Itach , Nadav Haklai , Shadi Ammouri , Igal Liberman , Thomas Petazzoni , Marcin Wojtas , Hanna Hawa , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updated accordingly. Signed-off-by: Gregory CLEMENT --- Changelog: v2 -> v3 - Updating the kerneldoc - Renaming unprepare_clk to unprepare_ecc_clk - Adding extra test on the presence of "core" clock to make Boris happy v1 -> v2 - Removed the unnecessary IS_ERR() call - Skip the reg clock only if it is not present by checking "-ENOENT" - Add a label for uninitializing the reg clock. .../devicetree/bindings/mtd/marvell-nand.txt | 6 +++- drivers/mtd/nand/marvell_nand.c | 34 ++++++++++++++++++---- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/marvell-nand.txt b/Documentation/devicetree/bindings/mtd/marvell-nand.txt index c08fb477b3c6..4ee9813bf88f 100644 --- a/Documentation/devicetree/bindings/mtd/marvell-nand.txt +++ b/Documentation/devicetree/bindings/mtd/marvell-nand.txt @@ -14,7 +14,11 @@ Required properties: - #address-cells: shall be set to 1. Encode the NAND CS. - #size-cells: shall be set to 0. - interrupts: shall define the NAND controller interrupt. -- clocks: shall reference the NAND controller clock. +- clocks: shall reference the NAND controller clocks, the second one is + optional but needed for the Armada 7K/8K SoCs +- clock-names: mandatory if there is a second clock, in this case the + name must be "core" for the first clock and "reg" for the second + one - marvell,system-controller: Set to retrieve the syscon node that handles NAND controller related registers (only required with the "marvell,armada-8k-nand[-controller]" compatibles). diff --git a/drivers/mtd/nand/marvell_nand.c b/drivers/mtd/nand/marvell_nand.c index 2196f2a233d6..0e7e8017046a 100644 --- a/drivers/mtd/nand/marvell_nand.c +++ b/drivers/mtd/nand/marvell_nand.c @@ -308,6 +308,7 @@ struct marvell_nfc_caps { * @dev: Parent device (used to print error messages) * @regs: NAND controller registers * @ecc_clk: ECC block clock, two times the NAND controller clock + * @reg_clk: Regsiters clock * @complete: Completion object to wait for NAND controller events * @assigned_cs: Bitmask describing already assigned CS lines * @chips: List containing all the NAND chips attached to @@ -321,6 +322,7 @@ struct marvell_nfc { struct device *dev; void __iomem *regs; struct clk *ecc_clk; + struct clk *reg_clk; struct completion complete; unsigned long assigned_cs; struct list_head chips; @@ -2739,7 +2741,12 @@ static int marvell_nfc_probe(struct platform_device *pdev) return irq; } - nfc->ecc_clk = devm_clk_get(&pdev->dev, NULL); + nfc->ecc_clk = devm_clk_get(&pdev->dev, "core"); + + /* Managed the legacy case (when the first clock was not named) */ + if (nfc->ecc_clk == ERR_PTR(-ENOENT)) + nfc->ecc_clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(nfc->ecc_clk)) return PTR_ERR(nfc->ecc_clk); @@ -2747,12 +2754,24 @@ static int marvell_nfc_probe(struct platform_device *pdev) if (ret) return ret; + nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); + if (PTR_ERR(nfc->reg_clk) != -ENOENT) { + if (!IS_ERR(nfc->reg_clk)) { + ret = clk_prepare_enable(nfc->reg_clk); + if (ret) + goto unprepare_ecc_clk; + } else { + ret = PTR_ERR(nfc->reg_clk); + goto unprepare_ecc_clk; + } + } + marvell_nfc_disable_int(nfc, NDCR_ALL_INT); marvell_nfc_clear_int(nfc, NDCR_ALL_INT); ret = devm_request_irq(dev, irq, marvell_nfc_isr, 0, "marvell-nfc", nfc); if (ret) - goto unprepare_clk; + goto unprepare_reg_clk; /* Get NAND controller capabilities */ if (pdev->id_entry) @@ -2763,23 +2782,25 @@ static int marvell_nfc_probe(struct platform_device *pdev) if (!nfc->caps) { dev_err(dev, "Could not retrieve NFC caps\n"); ret = -EINVAL; - goto unprepare_clk; + goto unprepare_reg_clk; } /* Init the controller and then probe the chips */ ret = marvell_nfc_init(nfc); if (ret) - goto unprepare_clk; + goto unprepare_reg_clk; platform_set_drvdata(pdev, nfc); ret = marvell_nand_chips_init(dev, nfc); if (ret) - goto unprepare_clk; + goto unprepare_reg_clk; return 0; -unprepare_clk: +unprepare_reg_clk: + clk_disable_unprepare(nfc->reg_clk); +unprepare_ecc_clk: clk_disable_unprepare(nfc->ecc_clk); return ret; @@ -2796,6 +2817,7 @@ static int marvell_nfc_remove(struct platform_device *pdev) dma_release_channel(nfc->dma_chan); } + clk_disable_unprepare(nfc->reg_clk); clk_disable_unprepare(nfc->ecc_clk); return 0;