From patchwork Thu Dec 15 21:31:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1716277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NY56j0kvHz2405 for ; Fri, 16 Dec 2022 08:32:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230020AbiLOVc1 (ORCPT ); Thu, 15 Dec 2022 16:32:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230006AbiLOVcS (ORCPT ); Thu, 15 Dec 2022 16:32:18 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 22CCF1CB37; Thu, 15 Dec 2022 13:32:17 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,248,1665414000"; d="scan'208";a="143493758" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 16 Dec 2022 06:32:16 +0900 Received: from localhost.localdomain (unknown [10.226.92.26]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B674040062B3; Fri, 16 Dec 2022 06:32:12 +0900 (JST) From: Biju Das To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: Biju Das , Geert Uytterhoeven , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Prabhakar Mahadev Lad , Rob Herring Subject: [PATCH v5 1/9] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding Date: Thu, 15 Dec 2022 21:31:58 +0000 Message-Id: <20221215213206.56666-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> References: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG). Signed-off-by: Biju Das Reviewed-by: Rob Herring --- v4->v5: * Added Rb tag from Rob. v3->v4: * Replaced companion->renesas,gpt for the phandle to gpt instance * Replaced renesas,id->renesas,poeg-id * Removed default from renesas,poeg-id as default for a required property doesn't make much sense. * Updated the example and required properties with above changes v2->v3: * Removed Rb tag from Rob as there are some changes introduced. * Added companion property, so that poeg can link with gpt device * Documented renesas,id, as identifier for POEGG{A,B,C,D}. * Updated the example. v1->v2: * Updated the description. REF->v1: * Modelled as pincontrol as most of its configuration is intended to be static. * Updated reg size in example. --- .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml new file mode 100644 index 000000000000..ab2d456c93e4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L Port Output Enable for GPT (POEG) + +maintainers: + - Biju Das + +description: | + The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be + disabled by using the port output enabling function for the GPT (POEG). + Specifically, either of the following ways can be used. + * Input level detection of the GTETRGA to GTETRGD pins. + * Output-disable request from the GPT. + * SSF bit setting(ie, by setting POEGGn.SSF to 1) + + The state of the GTIOCxA and the GTIOCxB pins when the output is disabled, + are controlled by the GPT module. + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-poeg # RZ/G2{L,LC} + - renesas,r9a07g054-poeg # RZ/V2L + - const: renesas,rzg2l-poeg + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + renesas,gpt: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to gpt instance that serves the pwm operation. + + renesas,poeg-id: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + description: | + POEG group index. Valid values are: + <0> : POEG group A + <1> : POEG group B + <2> : POEG group C + <3> : POEG group D + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - resets + - renesas,poeg-id + - renesas,gpt + +additionalProperties: false + +examples: + - | + #include + #include + + poeggd: poeg@10049400 { + compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg"; + reg = <0x10049400 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_POEG_D_RST>; + renesas,poeg-id = <3>; + renesas,gpt = <&gpt>; + }; From patchwork Thu Dec 15 21:31:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1716280 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NY56k2qfHz240d for ; Fri, 16 Dec 2022 08:32:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230012AbiLOVc2 (ORCPT ); Thu, 15 Dec 2022 16:32:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230010AbiLOVcX (ORCPT ); Thu, 15 Dec 2022 16:32:23 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A270F1C437; Thu, 15 Dec 2022 13:32:21 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,248,1665414000"; d="scan'208";a="146337516" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 16 Dec 2022 06:32:20 +0900 Received: from localhost.localdomain (unknown [10.226.92.26]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7021E40071FC; Fri, 16 Dec 2022 06:32:17 +0900 (JST) From: Biju Das To: Linus Walleij , Philipp Zabel Cc: Biju Das , Geert Uytterhoeven , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Chris Paterson , Prabhakar Mahadev Lad Subject: [PATCH v5 2/9] drivers: pinctrl: renesas: Add RZ/G2L POEG driver support Date: Thu, 15 Dec 2022 21:31:59 +0000 Message-Id: <20221215213206.56666-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> References: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The output pins of the RZ/G2L general PWM timer (GPT) can be disabled by using the port output enabling function for the GPT (POEG). This patch adds basic support using s/w control through sysfs to enable/disable output from GPT. Signed-off-by: Biju Das --- v4->v5: * Updated kernel version in sysfs doc. v3->v4: * Updated commit description. v2->v3: * Added sysfs documentation for output_disable * PWM_RZG2L_GPT implies ARCH_RZG2L. So removed ARCH_RZG2L dependency * Used dev_get_drvdata to get device data * Replaced sprintf->sysfs_emit in show(). v1->v2: * Renamed the file poeg-rzg2l->rzg2l-poeg * Removed the macro POEGG as there is only single register and updated rzg2l_poeg_write() and rzg2l_poeg_read() * Updated error handling in probe() Ref->v1: * Moved driver files from soc to pincontrol directory * Updated KConfig --- .../ABI/testing/sysfs-platform-rzg2l-poeg | 18 ++ drivers/pinctrl/renesas/Kconfig | 2 + drivers/pinctrl/renesas/Makefile | 2 + drivers/pinctrl/renesas/poeg/Kconfig | 11 ++ drivers/pinctrl/renesas/poeg/Makefile | 2 + drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 157 ++++++++++++++++++ 6 files changed, 192 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-rzg2l-poeg create mode 100644 drivers/pinctrl/renesas/poeg/Kconfig create mode 100644 drivers/pinctrl/renesas/poeg/Makefile create mode 100644 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c diff --git a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg new file mode 100644 index 000000000000..157c98c49940 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg @@ -0,0 +1,18 @@ +What: /sys/devices/platform//output_disable +Date: November 2022 +KernelVersion: 6.3 +Contact: Biju Das +Description: + This file can be read and write. + The file used to control the output disable using + register settings. + + Write the following string to control the output disable: + + - "1" - request output-disable from software. + - "0" - request no output-disable from software. + + Read the file, then it shows the following strings: + + - "1" - Output-disable request from software occurred. + - "0" - No output-disable request from software occurred. diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 0903a0a41831..92bdc2e1e125 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -308,4 +308,6 @@ config PINCTRL_PFC_SHX3 bool "pin control support for SH-X3" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO +source "drivers/pinctrl/renesas/poeg/Kconfig" + endmenu diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 558b30ce0dec..de1bb592fbf3 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -52,6 +52,8 @@ obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o obj-$(CONFIG_PINCTRL_RZV2M) += pinctrl-rzv2m.o +obj-$(CONFIG_POEG_RZG2L) += poeg/ + ifeq ($(CONFIG_COMPILE_TEST),y) CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a diff --git a/drivers/pinctrl/renesas/poeg/Kconfig b/drivers/pinctrl/renesas/poeg/Kconfig new file mode 100644 index 000000000000..306e8ae81cb2 --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +config POEG_RZG2L + tristate "Renesas RZ/G2L poeg support" + depends on PWM_RZG2L_GPT || COMPILE_TEST + depends on HAS_IOMEM + help + This driver exposes the Port Output Enable for GPT(POEG) found + in Renesas RZ/G2L alike SoCs. + + To compile this driver as a module, choose M here: the module + will be called rzg2l-poeg. diff --git a/drivers/pinctrl/renesas/poeg/Makefile b/drivers/pinctrl/renesas/poeg/Makefile new file mode 100644 index 000000000000..610bdd6182be --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_POEG_RZG2L) += rzg2l-poeg.o diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c new file mode 100644 index 000000000000..3788191bc2f1 --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2L Port Output Enable for GPT (POEG) driver + * + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include + +#define POEGG_SSF BIT(3) + +struct rzg2l_poeg_chip { + struct reset_control *rstc; + void __iomem *mmio; +}; + +static void rzg2l_poeg_write(struct rzg2l_poeg_chip *chip, u32 data) +{ + iowrite32(data, chip->mmio); +} + +static u32 rzg2l_poeg_read(struct rzg2l_poeg_chip *chip) +{ + return ioread32(chip->mmio); +} + +static ssize_t output_disable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct rzg2l_poeg_chip *chip; + unsigned int val; + u32 reg_val; + int ret; + + chip = dev_get_drvdata(dev); + ret = kstrtouint(buf, 0, &val); + if (ret) + return ret; + + reg_val = rzg2l_poeg_read(chip); + if (val) + reg_val |= POEGG_SSF; + else + reg_val &= ~POEGG_SSF; + + rzg2l_poeg_write(chip, reg_val); + + return count; +} + +static ssize_t output_disable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct rzg2l_poeg_chip *chip; + u32 reg; + + chip = dev_get_drvdata(dev); + reg = rzg2l_poeg_read(chip); + + return sysfs_emit(buf, "%u\n", (reg & POEGG_SSF) ? 1 : 0); +} + +static DEVICE_ATTR_RW(output_disable); + +static struct attribute *poeg_attrs[] = { + &dev_attr_output_disable.attr, + NULL, +}; + +static const struct attribute_group poeg_groups = { + .attrs = poeg_attrs, +}; + +static const struct of_device_id rzg2l_poeg_of_table[] = { + { .compatible = "renesas,rzg2l-poeg", }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg2l_poeg_of_table); + +static int rzg2l_poeg_probe(struct platform_device *pdev) +{ + struct rzg2l_poeg_chip *chip; + int ret; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->mmio = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(chip->mmio)) + return PTR_ERR(chip->mmio); + + chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(chip->rstc)) + return dev_err_probe(&pdev->dev, PTR_ERR(chip->rstc), + "get reset failed\n"); + + ret = reset_control_deassert(chip->rstc); + if (ret) + return ret; + + platform_set_drvdata(pdev, chip); + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); + goto err_pm_disable; + } + + ret = sysfs_create_group(&pdev->dev.kobj, &poeg_groups); + if (ret < 0) { + dev_err(&pdev->dev, "failed to create sysfs: %d\n", ret); + goto err_pm; + } + + return 0; + +err_pm: + pm_runtime_put(&pdev->dev); +err_pm_disable: + pm_runtime_disable(&pdev->dev); + reset_control_assert(chip->rstc); + + return ret; +} + +static int rzg2l_poeg_remove(struct platform_device *pdev) +{ + struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev); + + sysfs_remove_group(&pdev->dev.kobj, &poeg_groups); + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + reset_control_assert(chip->rstc); + + return 0; +} + +static struct platform_driver rzg2l_poeg_driver = { + .driver = { + .name = "rzg2l-poeg", + .of_match_table = of_match_ptr(rzg2l_poeg_of_table), + }, + .probe = rzg2l_poeg_probe, + .remove = rzg2l_poeg_remove, +}; +module_platform_driver(rzg2l_poeg_driver); + +MODULE_AUTHOR("Biju Das "); +MODULE_DESCRIPTION("Renesas RZ/G2L POEG Driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Dec 15 21:32:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1716282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NY56l31LZz2405 for ; Fri, 16 Dec 2022 08:32:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230010AbiLOVc3 (ORCPT ); Thu, 15 Dec 2022 16:32:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230014AbiLOVc0 (ORCPT ); Thu, 15 Dec 2022 16:32:26 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0C7B127B10; Thu, 15 Dec 2022 13:32:24 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,248,1665414000"; d="scan'208";a="143493768" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 16 Dec 2022 06:32:24 +0900 Received: from localhost.localdomain (unknown [10.226.92.26]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 52CB040071FC; Fri, 16 Dec 2022 06:32:21 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v5 3/9] pwm: rzg2l-gpt: Add support for output disable request from gpt Date: Thu, 15 Dec 2022 21:32:00 +0000 Message-Id: <20221215213206.56666-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> References: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org When dead time error occurs or the GTIOCA pin output value is the same as the GTIOCB pin output value, output protection is required. GPT detects this condition and generates output disable requests to POEG based on the settings in the output disable request permission bits, such as GTINTAD.GRPDTE, GTINTAD.GRPABH, GTINTAD.GRPABL. After the POEG receives output disable requests from each channel and calculates external input using an OR operation, the POEG generates output disable requests to GPT. This patch adds support for output disable request from gpt, when same time output level is high. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 111 ++++++++++++++++++++++++++ include/linux/soc/renesas/rzg2l-gpt.h | 32 ++++++++ 2 files changed, 143 insertions(+) create mode 100644 include/linux/soc/renesas/rzg2l-gpt.h diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 6bf407550326..bcf843b51e3d 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -26,12 +26,14 @@ #include #include #include +#include #include #define RZG2L_GTCR 0x2c #define RZG2L_GTUDDTYC 0x30 #define RZG2L_GTIOR 0x34 #define RZG2L_GTINTAD 0x38 +#define RZG2L_GTST 0x3c #define RZG2L_GTBER 0x40 #define RZG2L_GTCNT 0x48 #define RZG2L_GTCCRA 0x4c @@ -72,6 +74,12 @@ (FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) | RZG2L_GTIOR_OBE) #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) + +#define RZG2L_GTST_OABHF BIT(29) +#define RZG2L_GTST_OABLF BIT(30) + +#define RZG2L_GTST_POEG_IRQ_MASK GENMASK(30, 28) #define RZG2L_GTCCR(i) (0x4c + 4 * (i)) @@ -458,6 +466,109 @@ static const struct dev_pm_ops rzg2l_gpt_pm_ops = { SET_RUNTIME_PM_OPS(rzg2l_gpt_pm_runtime_suspend, rzg2l_gpt_pm_runtime_resume, NULL) }; +u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 val = 0; + u32 offs; + u32 reg; + + rzg2l_gpt = dev_get_drvdata(dev); + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + val <<= 3; + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + reg = rzg2l_gpt_read(rzg2l_gpt, offs + RZG2L_GTST); + val |= FIELD_GET(RZG2L_GTST_POEG_IRQ_MASK, reg); + } + + return val; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_irq_status); + +int rzg2l_gpt_poeg_disable_req_clr(void *dev, u8 grp) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 offs; + u32 reg; + + rzg2l_gpt = dev_get_drvdata(dev); + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + reg = rzg2l_gpt_read(rzg2l_gpt, offs + RZG2L_GTST); + + if (reg & (RZG2L_GTST_OABHF | RZG2L_GTST_OABLF)) + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR, + RZG2L_GTIOR_OBE, 0); + } + + return 0; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_clr); + +int rzg2l_gpt_pin_reenable(void *dev, u8 grp) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 offs; + + rzg2l_gpt = dev_get_drvdata(dev); + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR, + RZG2L_GTIOR_OBE, RZG2L_GTIOR_OBE); + } + return 0; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_pin_reenable); + +static int rzg2l_gpt_poeg_disable_req_endisable(void *dev, u8 grp, int op, bool on) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 offs; + + rzg2l_gpt = dev_get_drvdata(dev); + pm_runtime_get_sync(dev); + + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + if (on) + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD, op, op); + else + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD, op, 0); + } + + pm_runtime_put(dev); + + return 0; +} + +int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8 grp, bool on) +{ + int id = RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high); + static void rzg2l_gpt_reset_assert_pm_disable(void *data) { struct rzg2l_gpt_chip *rzg2l_gpt = data; diff --git a/include/linux/soc/renesas/rzg2l-gpt.h b/include/linux/soc/renesas/rzg2l-gpt.h new file mode 100644 index 000000000000..87e641fd8732 --- /dev/null +++ b/include/linux/soc/renesas/rzg2l-gpt.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_SOC_RENESAS_RZG2L_GPT_H__ +#define __LINUX_SOC_RENESAS_RZG2L_GPT_H__ + +#if IS_ENABLED(CONFIG_PWM_RZG2L_GPT) +u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp); +int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp); +int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); +int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on); +#else +static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) +{ + return -ENODEV; +} + +static inline int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp) +{ + return -ENODEV; +} + +static inline int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp) +{ + return -ENODEV; +} + +static inline int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on) +{ + return -ENODEV; +} +#endif + +#endif /* __LINUX_SOC_RENESAS_RZG2L_GPT_H__ */ From patchwork Thu Dec 15 21:32:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1716284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NY56p5n9vz2405 for ; Fri, 16 Dec 2022 08:32:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230030AbiLOVcd (ORCPT ); Thu, 15 Dec 2022 16:32:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229782AbiLOVca (ORCPT ); Thu, 15 Dec 2022 16:32:30 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 502105C750; Thu, 15 Dec 2022 13:32:28 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,248,1665414000"; d="scan'208";a="143493772" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 16 Dec 2022 06:32:28 +0900 Received: from localhost.localdomain (unknown [10.226.92.26]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 08EC240062B3; Fri, 16 Dec 2022 06:32:24 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v5 4/9] pinctrl: renesas: rzg2l-poeg: Add support for GPT Output-Disable Request Date: Thu, 15 Dec 2022 21:32:01 +0000 Message-Id: <20221215213206.56666-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> References: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch supports output-disable requests from GPT. Added sysfs to enable/disable request from GPT when both outputs are high. When both outputs are high, gpt detects the condition and triggers an interrupt to POEG. POEG handles the interrupt and send notification to userspace. userspace handles the fault and issue a write call to cancel the disable output request. Signed-off-by: Biju Das --- .../ABI/testing/sysfs-platform-rzg2l-poeg | 23 ++ drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 252 +++++++++++++++++- include/linux/soc/renesas/rzg2l-poeg.h | 16 ++ 3 files changed, 288 insertions(+), 3 deletions(-) create mode 100644 include/linux/soc/renesas/rzg2l-poeg.h diff --git a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg index 157c98c49940..598fca265aad 100644 --- a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg +++ b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg @@ -16,3 +16,26 @@ Description: - "1" - Output-disable request from software occurred. - "0" - No output-disable request from software occurred. + +What: /sys/devices/platform//gpt_req_both_high +Date: November 2022 +KernelVersion: 6.3 +Contact: Biju Das +Description: + This file can be read and write. + The file used to configure the output disable request from + gpt when same time output level high. + + Write the following string to control the output disable: + + - "1" - Enables output-disable request from gpt when same time + output level high. + - "0" - Disables output-disable request from gpt when same time + output level high. + + Read the file, then it shows the following strings: + + - "1" - Output-disable request from gpt when same time + output level high is enabled. + - "0" - Output-disable request from gpt when same time + output level high is disabled. diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c index 3788191bc2f1..2a66dc869fd3 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -4,19 +4,40 @@ * * Copyright (C) 2022 Renesas Electronics Corporation */ - +#include +#include #include +#include #include #include +#include #include #include +#include #include +#include +#include +#include +#define POEGG_IOCE BIT(5) +#define POEGG_PIDE BIT(4) #define POEGG_SSF BIT(3) +#define POEGG_IOCF BIT(1) +#define POEGG_PIDF BIT(0) + +static struct class *poeg_class; +static dev_t g_poeg_dev; +static int minor_n; struct rzg2l_poeg_chip { + struct device *gpt_dev; struct reset_control *rstc; void __iomem *mmio; + u8 index; + DECLARE_BITMAP(gpt_irq, 3); + struct cdev poeg_cdev; + wait_queue_head_t events_wait; + DECLARE_KFIFO_PTR(events, struct poeg_event); }; static void rzg2l_poeg_write(struct rzg2l_poeg_chip *chip, u32 data) @@ -66,10 +87,46 @@ static ssize_t output_disable_show(struct device *dev, return sysfs_emit(buf, "%u\n", (reg & POEGG_SSF) ? 1 : 0); } +static ssize_t gpt_req_both_high_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct rzg2l_poeg_chip *chip; + unsigned int val; + int ret; + + chip = dev_get_drvdata(dev); + ret = kstrtouint(buf, 0, &val); + if (ret) + return ret; + + if (val) + set_bit(RZG2L_GPT_OABHF, chip->gpt_irq); + else + clear_bit(RZG2L_GPT_OABHF, chip->gpt_irq); + + rzg2l_gpt_poeg_disable_req_both_high(chip->gpt_dev, chip->index, + test_bit(RZG2L_GPT_OABHF, chip->gpt_irq)); + + return count; +} + +static ssize_t gpt_req_both_high_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct rzg2l_poeg_chip *chip; + + chip = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%u\n", test_bit(RZG2L_GPT_OABHF, chip->gpt_irq)); +} + static DEVICE_ATTR_RW(output_disable); +static DEVICE_ATTR_RW(gpt_req_both_high); static struct attribute *poeg_attrs[] = { &dev_attr_output_disable.attr, + &dev_attr_gpt_req_both_high.attr, NULL, }; @@ -83,19 +140,161 @@ static const struct of_device_id rzg2l_poeg_of_table[] = { }; MODULE_DEVICE_TABLE(of, rzg2l_poeg_of_table); +static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) +{ + struct rzg2l_poeg_chip *chip = ptr; + struct poeg_event ev; + u32 val; + + val = rzg2l_gpt_poeg_disable_req_irq_status(chip->gpt_dev, chip->index); + ev.channel = chip->index; + ev.gpt_disable_irq_status = val; + kfifo_in(&chip->events, &ev, 1); + wake_up_poll(&chip->events_wait, EPOLLIN); + + val = rzg2l_poeg_read(chip); + if (val & POEGG_IOCF) + val &= ~POEGG_IOCF; + + if (val & POEGG_PIDF) + val &= ~POEGG_PIDF; + + rzg2l_poeg_write(chip, val); + rzg2l_gpt_poeg_disable_req_clr(chip->gpt_dev, chip->index); + + return IRQ_HANDLED; +} + +static void rzg2l_poeg_cleanup(void *data) +{ + struct rzg2l_poeg_chip *chip = data; + + put_device(chip->gpt_dev); +} + +static __poll_t rzg2l_poeg_chrdev_poll(struct file *filp, + struct poll_table_struct *pollt) +{ + struct rzg2l_poeg_chip *const chip = filp->private_data; + __poll_t events = 0; + + poll_wait(filp, &chip->events_wait, pollt); + if (!kfifo_is_empty(&chip->events)) + events = EPOLLIN | EPOLLRDNORM; + + return events; +} + +static ssize_t rzg2l_poeg_chrdev_read(struct file *filp, char __user *buf, + size_t len, loff_t *f_ps) +{ + struct rzg2l_poeg_chip *const chip = filp->private_data; + unsigned int copied; + int err; + + if (len < sizeof(struct poeg_event)) + return -EINVAL; + + do { + if (kfifo_is_empty(&chip->events)) { + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + + err = wait_event_interruptible(chip->events_wait, + !kfifo_is_empty(&chip->events)); + if (err < 0) + return err; + } + + err = kfifo_to_user(&chip->events, buf, len, &copied); + if (err < 0) + return err; + } while (!copied); + + return copied; +} + +static ssize_t rzg2l_poeg_chrdev_write(struct file *filp, + const char __user *buf, + size_t len, loff_t *f_ps) +{ + struct rzg2l_poeg_chip *const chip = filp->private_data; + + rzg2l_gpt_pin_reenable(chip->gpt_dev, chip->index); + + return len; +} + +static int rzg2l_poeg_chrdev_open(struct inode *inode, struct file *filp) +{ + struct rzg2l_poeg_chip *const chip = container_of(inode->i_cdev, + typeof(*chip), + poeg_cdev); + + filp->private_data = chip; + + return nonseekable_open(inode, filp); +} + +static int rzg2l_poeg_chrdev_release(struct inode *inode, struct file *filp) +{ + filp->private_data = NULL; + + return 0; +} + +static const struct file_operations poeg_fops = { + .owner = THIS_MODULE, + .read = rzg2l_poeg_chrdev_read, + .write = rzg2l_poeg_chrdev_write, + .poll = rzg2l_poeg_chrdev_poll, + .open = rzg2l_poeg_chrdev_open, + .release = rzg2l_poeg_chrdev_release, +}; + static int rzg2l_poeg_probe(struct platform_device *pdev) { + struct platform_device *gpt_pdev = NULL; struct rzg2l_poeg_chip *chip; + struct device_node *np; + u32 val; + int irq; int ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; + np = of_parse_phandle(pdev->dev.of_node, "renesas,gpt", 0); + if (np) + gpt_pdev = of_find_device_by_node(np); + + of_node_put(np); + if (!gpt_pdev) + return -ENODEV; + + if (!of_property_read_u32(pdev->dev.of_node, "renesas,poeg-id", &val)) + chip->index = val; + + chip->gpt_dev = &gpt_pdev->dev; + ret = devm_add_action_or_reset(&pdev->dev, + rzg2l_poeg_cleanup, chip); + if (ret < 0) + return ret; + chip->mmio = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(chip->mmio)) return PTR_ERR(chip->mmio); + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_irq(&pdev->dev, irq, rzg2l_poeg_irq, 0, + dev_name(&pdev->dev), chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "cannot get irq\n"); + chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(chip->rstc)) return dev_err_probe(&pdev->dev, PTR_ERR(chip->rstc), @@ -113,13 +312,26 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) goto err_pm_disable; } + rzg2l_poeg_write(chip, POEGG_IOCE | POEGG_PIDE); + ret = sysfs_create_group(&pdev->dev.kobj, &poeg_groups); if (ret < 0) { dev_err(&pdev->dev, "failed to create sysfs: %d\n", ret); goto err_pm; } - return 0; + init_waitqueue_head(&chip->events_wait); + cdev_init(&chip->poeg_cdev, &poeg_fops); + chip->poeg_cdev.owner = THIS_MODULE; + ret = cdev_add(&chip->poeg_cdev, MKDEV(MAJOR(g_poeg_dev), minor_n), 1); + if (ret) + goto err_pm; + + device_create(poeg_class, NULL, MKDEV(MAJOR(g_poeg_dev), minor_n), + NULL, "poeg%d", minor_n); + minor_n++; + + return kfifo_alloc(&chip->events, 64, GFP_KERNEL); err_pm: pm_runtime_put(&pdev->dev); @@ -134,6 +346,10 @@ static int rzg2l_poeg_remove(struct platform_device *pdev) { struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev); + kfifo_free(&chip->events); + device_destroy(poeg_class, + MKDEV(MAJOR(g_poeg_dev), MINOR(chip->poeg_cdev.dev))); + cdev_del(&chip->poeg_cdev); sysfs_remove_group(&pdev->dev.kobj, &poeg_groups); pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); @@ -150,7 +366,37 @@ static struct platform_driver rzg2l_poeg_driver = { .probe = rzg2l_poeg_probe, .remove = rzg2l_poeg_remove, }; -module_platform_driver(rzg2l_poeg_driver); + +static int rzg2l_poeg_device_init(void) +{ + int err; + + err = alloc_chrdev_region(&g_poeg_dev, 0, 1, "poeg"); + if (err) + goto out; + + poeg_class = class_create(THIS_MODULE, "poeg"); + if (IS_ERR(poeg_class)) { + err = PTR_ERR(poeg_class); + goto err_free_chrdev; + } + + return platform_driver_register(&rzg2l_poeg_driver); + +err_free_chrdev: + unregister_chrdev_region(g_poeg_dev, 1); +out: + return err; +} + +static void rzg2l_poeg_device_exit(void) +{ + class_destroy(poeg_class); + unregister_chrdev_region(g_poeg_dev, 1); +} + +module_init(rzg2l_poeg_device_init); +module_exit(rzg2l_poeg_device_exit); MODULE_AUTHOR("Biju Das "); MODULE_DESCRIPTION("Renesas RZ/G2L POEG Driver"); diff --git a/include/linux/soc/renesas/rzg2l-poeg.h b/include/linux/soc/renesas/rzg2l-poeg.h new file mode 100644 index 000000000000..0b3d47d80af8 --- /dev/null +++ b/include/linux/soc/renesas/rzg2l-poeg.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_SOC_RENESAS_RZG2L_POEG_H__ +#define __LINUX_SOC_RENESAS_RZG2L_POEG_H__ + +#include + +#define RZG2L_GPT_DTEF 0 +#define RZG2L_GPT_OABHF 1 +#define RZG2L_GPT_OABLF 2 + +struct poeg_event { + __u32 gpt_disable_irq_status; + __u8 channel; +}; + +#endif /* __LINUX_SOC_RENESAS_RZG2L_POEG_H__ */ From patchwork Thu Dec 15 21:32:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1716286 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NY56s3pwHz2405 for ; Fri, 16 Dec 2022 08:32:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229639AbiLOVcg (ORCPT ); Thu, 15 Dec 2022 16:32:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230083AbiLOVcd (ORCPT ); Thu, 15 Dec 2022 16:32:33 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4F053164A5; Thu, 15 Dec 2022 13:32:32 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,248,1665414000"; d="scan'208";a="146337526" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 16 Dec 2022 06:32:31 +0900 Received: from localhost.localdomain (unknown [10.226.92.26]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A2B1A40071FC; Fri, 16 Dec 2022 06:32:28 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v5 5/9] pwm: rzg2l-gpt: Add support for output disable when both output low Date: Thu, 15 Dec 2022 21:32:02 +0000 Message-Id: <20221215213206.56666-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> References: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support for output disable request from gpt, when same time output level is low. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 9 +++++++++ include/linux/soc/renesas/rzg2l-gpt.h | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index bcf843b51e3d..749c468a5d66 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -75,6 +75,7 @@ #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW BIT(30) #define RZG2L_GTST_OABHF BIT(29) #define RZG2L_GTST_OABLF BIT(30) @@ -569,6 +570,14 @@ int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8 grp, bool on) } EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high); +int rzg2l_gpt_poeg_disable_req_both_low(void *dev, u8 grp, bool on) +{ + int id = RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_low); + static void rzg2l_gpt_reset_assert_pm_disable(void *data) { struct rzg2l_gpt_chip *rzg2l_gpt = data; diff --git a/include/linux/soc/renesas/rzg2l-gpt.h b/include/linux/soc/renesas/rzg2l-gpt.h index 87e641fd8732..1977d94baf8d 100644 --- a/include/linux/soc/renesas/rzg2l-gpt.h +++ b/include/linux/soc/renesas/rzg2l-gpt.h @@ -7,6 +7,7 @@ u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp); int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp); int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on); +int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on); #else static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) { @@ -27,6 +28,11 @@ static inline int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, { return -ENODEV; } + +static inline int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on) +{ + return -ENODEV; +} #endif #endif /* __LINUX_SOC_RENESAS_RZG2L_GPT_H__ */ From patchwork Thu Dec 15 21:32:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1716289 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NY56w6KZcz240d for ; Fri, 16 Dec 2022 08:32:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230014AbiLOVcj (ORCPT ); Thu, 15 Dec 2022 16:32:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229782AbiLOVcg (ORCPT ); Thu, 15 Dec 2022 16:32:36 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D45A55C749; Thu, 15 Dec 2022 13:32:35 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,248,1665414000"; d="scan'208";a="146337529" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 16 Dec 2022 06:32:35 +0900 Received: from localhost.localdomain (unknown [10.226.92.26]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 422C140071FC; Fri, 16 Dec 2022 06:32:31 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v5 6/9] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT when both outputs are low. Date: Thu, 15 Dec 2022 21:32:03 +0000 Message-Id: <20221215213206.56666-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> References: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support fpr output-disable requests from GPT, when both outputs are low. Added sysfs to enable/disable for configuring GPT output disable request when both outputs are low. Signed-off-by: Biju Das --- .../ABI/testing/sysfs-platform-rzg2l-poeg | 23 ++++++++++++ drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 36 +++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg index 598fca265aad..45a7f44dccdd 100644 --- a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg +++ b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg @@ -39,3 +39,26 @@ Description: output level high is enabled. - "0" - Output-disable request from gpt when same time output level high is disabled. + +What: /sys/devices/platform//gpt_req_both_low +Date: November 2022 +KernelVersion: 6.3 +Contact: Biju Das +Description: + This file can be read and write. + The file used to configure the output disable request from + gpt when same time output level low. + + Write the following string to control the output disable: + + - "1" - Enables output-disable request from gpt when same time + output level low. + - "0" - Disables output-disable request from gpt when same time + output level low. + + Read the file, then it shows the following strings: + + - "1" - Output-disable request from gpt when same time + output level low is enabled. + - "0" - Output-disable request from gpt when same time + output level low is disabled. diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c index 2a66dc869fd3..58a2cc9519e5 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -121,12 +121,48 @@ static ssize_t gpt_req_both_high_show(struct device *dev, return sysfs_emit(buf, "%u\n", test_bit(RZG2L_GPT_OABHF, chip->gpt_irq)); } +static ssize_t gpt_req_both_low_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct rzg2l_poeg_chip *chip; + unsigned int val; + int ret; + + chip = dev_get_drvdata(dev); + ret = kstrtouint(buf, 0, &val); + if (ret) + return ret; + + if (val) + set_bit(RZG2L_GPT_OABLF, chip->gpt_irq); + else + clear_bit(RZG2L_GPT_OABLF, chip->gpt_irq); + + rzg2l_gpt_poeg_disable_req_both_low(chip->gpt_dev, chip->index, + test_bit(RZG2L_GPT_OABLF, chip->gpt_irq)); + + return count; +} + +static ssize_t gpt_req_both_low_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct rzg2l_poeg_chip *chip; + + chip = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%u\n", test_bit(RZG2L_GPT_OABLF, chip->gpt_irq)); +} + static DEVICE_ATTR_RW(output_disable); static DEVICE_ATTR_RW(gpt_req_both_high); +static DEVICE_ATTR_RW(gpt_req_both_low); static struct attribute *poeg_attrs[] = { &dev_attr_output_disable.attr, &dev_attr_gpt_req_both_high.attr, + &dev_attr_gpt_req_both_low.attr, NULL, }; From patchwork Thu Dec 15 21:32:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1716291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NY5726vM7z240d for ; Fri, 16 Dec 2022 08:32:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230095AbiLOVco (ORCPT ); Thu, 15 Dec 2022 16:32:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229904AbiLOVcm (ORCPT ); Thu, 15 Dec 2022 16:32:42 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 817171D66D; Thu, 15 Dec 2022 13:32:39 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,248,1665414000"; d="scan'208";a="143493780" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 16 Dec 2022 06:32:38 +0900 Received: from localhost.localdomain (unknown [10.226.92.26]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D958E40071FC; Fri, 16 Dec 2022 06:32:35 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v5 7/9] pwm: rzg2l-gpt: Add support for output disable on dead time error Date: Thu, 15 Dec 2022 21:32:04 +0000 Message-Id: <20221215213206.56666-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> References: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support for output disable request from gpt, when dead time error occurred. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 9 +++++++++ include/linux/soc/renesas/rzg2l-gpt.h | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 749c468a5d66..080cb582e38d 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -74,6 +74,7 @@ (FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) | RZG2L_GTIOR_OBE) #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_DEADTIME_ERROR BIT(28) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW BIT(30) @@ -578,6 +579,14 @@ int rzg2l_gpt_poeg_disable_req_both_low(void *dev, u8 grp, bool on) } EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_low); +int rzg2l_gpt_poeg_disable_req_deadtime_error(void *dev, u8 grp, bool on) +{ + int id = RZG2L_GTINTAD_OUTPUT_DISABLE_DEADTIME_ERROR; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_deadtime_error); + static void rzg2l_gpt_reset_assert_pm_disable(void *data) { struct rzg2l_gpt_chip *rzg2l_gpt = data; diff --git a/include/linux/soc/renesas/rzg2l-gpt.h b/include/linux/soc/renesas/rzg2l-gpt.h index 1977d94baf8d..c0827eaecdb7 100644 --- a/include/linux/soc/renesas/rzg2l-gpt.h +++ b/include/linux/soc/renesas/rzg2l-gpt.h @@ -8,6 +8,7 @@ int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp); int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on); int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on); +int rzg2l_gpt_poeg_disable_req_deadtime_error(void *gpt_device, u8 grp, bool on); #else static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) { @@ -33,6 +34,11 @@ static inline int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, { return -ENODEV; } + +static inline int rzg2l_gpt_poeg_disable_req_deadtime_err(void *gpt_device, u8 grp, bool on) +{ + return -ENODEV; +} #endif #endif /* __LINUX_SOC_RENESAS_RZG2L_GPT_H__ */ From patchwork Thu Dec 15 21:32:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1716292 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NY5791VxNz2405 for ; Fri, 16 Dec 2022 08:32:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230052AbiLOVcw (ORCPT ); Thu, 15 Dec 2022 16:32:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229904AbiLOVcp (ORCPT ); Thu, 15 Dec 2022 16:32:45 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D2C7C5C0E9; Thu, 15 Dec 2022 13:32:43 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,248,1665414000"; d="scan'208";a="143493797" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 16 Dec 2022 06:32:42 +0900 Received: from localhost.localdomain (unknown [10.226.92.26]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7F44440071FC; Fri, 16 Dec 2022 06:32:39 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v5 8/9] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT on dead time error Date: Thu, 15 Dec 2022 21:32:05 +0000 Message-Id: <20221215213206.56666-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> References: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support for output-disable requests from GPT, when dead time error occurs. Added sysfs to enable/disable for configuring GPT output disable request for dead time error. Signed-off-by: Biju Das --- .../ABI/testing/sysfs-platform-rzg2l-poeg | 23 ++++++++++++ drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 37 +++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg index 45a7f44dccdd..4ad421fef3b9 100644 --- a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg +++ b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg @@ -62,3 +62,26 @@ Description: output level low is enabled. - "0" - Output-disable request from gpt when same time output level low is disabled. + +What: /sys/devices/platform//gpt_req_deadtime_err +Date: November 2022 +KernelVersion: 6.3 +Contact: Biju Das +Description: + This file can be read and write. + The file used to configure the output disable request from + gpt when dead time error occurred. + + Write the following string to control the output disable: + + - "1" - Enables output-disable request from gpt when dead time + error occurs. + - "0" - Disables output-disable request from gpt when dead time + error occurs. + + Read the file, then it shows the following strings: + + - "1" - Output-disable request from gpt when dead time + error occurs is enabled. + - "0" - Output-disable request from gpt when dead time + error occurs is disabled. diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c index 58a2cc9519e5..c712d26c4282 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -155,14 +155,51 @@ static ssize_t gpt_req_both_low_show(struct device *dev, return sysfs_emit(buf, "%u\n", test_bit(RZG2L_GPT_OABLF, chip->gpt_irq)); } +static ssize_t gpt_req_deadtime_err_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct rzg2l_poeg_chip *chip; + unsigned int val; + int ret; + + chip = dev_get_drvdata(dev); + ret = kstrtouint(buf, 0, &val); + if (ret) + return ret; + + if (val) + set_bit(RZG2L_GPT_DTEF, chip->gpt_irq); + else + clear_bit(RZG2L_GPT_DTEF, chip->gpt_irq); + + rzg2l_gpt_poeg_disable_req_deadtime_error(chip->gpt_dev, chip->index, + test_bit(RZG2L_GPT_DTEF, chip->gpt_irq)); + + return count; +} + +static ssize_t gpt_req_deadtime_err_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct rzg2l_poeg_chip *chip; + + chip = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%u\n", test_bit(RZG2L_GPT_DTEF, chip->gpt_irq)); +} + static DEVICE_ATTR_RW(output_disable); static DEVICE_ATTR_RW(gpt_req_both_high); static DEVICE_ATTR_RW(gpt_req_both_low); +static DEVICE_ATTR_RW(gpt_req_deadtime_err); static struct attribute *poeg_attrs[] = { &dev_attr_output_disable.attr, &dev_attr_gpt_req_both_high.attr, &dev_attr_gpt_req_both_low.attr, + &dev_attr_gpt_req_deadtime_err.attr, NULL, }; From patchwork Thu Dec 15 21:32:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1716294 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NY57C4kKpz2405 for ; Fri, 16 Dec 2022 08:32:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229620AbiLOVcy (ORCPT ); Thu, 15 Dec 2022 16:32:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229782AbiLOVcu (ORCPT ); Thu, 15 Dec 2022 16:32:50 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BF0FE27B22; Thu, 15 Dec 2022 13:32:46 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,248,1665414000"; d="scan'208";a="146337568" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 16 Dec 2022 06:32:46 +0900 Received: from localhost.localdomain (unknown [10.226.92.26]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 28EA640062B3; Fri, 16 Dec 2022 06:32:42 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v5 9/9] tools/poeg: Add test app for poeg Date: Thu, 15 Dec 2022 21:32:06 +0000 Message-Id: <20221215213206.56666-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> References: <20221215213206.56666-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Signed-off-by: Biju Das --- tools/poeg/Build | 1 + tools/poeg/Makefile | 53 ++++++++++++++++++++++++++++++++++++++ tools/poeg/poeg_app.c | 60 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+) create mode 100644 tools/poeg/Build create mode 100644 tools/poeg/Makefile create mode 100644 tools/poeg/poeg_app.c diff --git a/tools/poeg/Build b/tools/poeg/Build new file mode 100644 index 000000000000..f960920a4afb --- /dev/null +++ b/tools/poeg/Build @@ -0,0 +1 @@ +poeg_app-y += poeg_app.o diff --git a/tools/poeg/Makefile b/tools/poeg/Makefile new file mode 100644 index 000000000000..6946e6956215 --- /dev/null +++ b/tools/poeg/Makefile @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +include ../scripts/Makefile.include + +bindir ?= /usr/bin + +ifeq ($(srctree),) +srctree := $(patsubst %/,%,$(dir $(CURDIR))) +srctree := $(patsubst %/,%,$(dir $(srctree))) +endif + +# Do not use make's built-in rules +# (this improves performance and avoids hard-to-debug behaviour); +MAKEFLAGS += -r + +override CFLAGS += -O2 -Wall -g -D_GNU_SOURCE -I$(OUTPUT)include + +ALL_TARGETS := poeg_app +ALL_PROGRAMS := $(patsubst %,$(OUTPUT)%,$(ALL_TARGETS)) + +all: $(ALL_PROGRAMS) + +export srctree OUTPUT CC LD CFLAGS +include $(srctree)/tools/build/Makefile.include + +# +# We need the following to be outside of kernel tree +# +$(OUTPUT)include/linux/poeg.h: ../../include/linux/soc/renesas/rzg2l-poeg.h + mkdir -p $(OUTPUT)include/linux 2>&1 || true + ln -sf $(CURDIR)/../../include/linux/soc/renesas/rzg2l-poeg.h $@ + +prepare: $(OUTPUT)include/linux/poeg.h + +COUNTER_EXAMPLE := $(OUTPUT)poeg_app.o +$(COUNTER_EXAMPLE): prepare FORCE + $(Q)$(MAKE) $(build)=poeg_app +$(OUTPUT)poeg_app: $(COUNTER_EXAMPLE) + $(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) $< -o $@ + +clean: + rm -f $(ALL_PROGRAMS) + rm -rf $(OUTPUT)include/linux/counter.h + find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete + +install: $(ALL_PROGRAMS) + install -d -m 755 $(DESTDIR)$(bindir); \ + for program in $(ALL_PROGRAMS); do \ + install $$program $(DESTDIR)$(bindir); \ + done + +FORCE: + +.PHONY: all install clean FORCE prepare diff --git a/tools/poeg/poeg_app.c b/tools/poeg/poeg_app.c new file mode 100644 index 000000000000..79cacb8c60c5 --- /dev/null +++ b/tools/poeg/poeg_app.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * POEG - example userspace application + * Copyright (C) 2022 Biju Das + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +int main(int argc, char *arg[]) +{ + struct poeg_event event_data; + unsigned int val; + int ret, fd, i; + + fd = open("/dev/poeg3", O_RDWR); + if (fd < 0) + perror("open"); + else + printf("[POEG]open\n"); + + for (;;) { + ret = read(fd, &event_data, sizeof(event_data)); + if (ret == -1) { + perror("Failed to read event data"); + return 1; + } + + val = event_data.gpt_disable_irq_status; + if (val) { + /* emulate fault clearing condition by adding delay */ + sleep(2); + for (i = 0; i < 8; i++) { + if (val & 7) { + printf("gpt ch:%u, irq=%x\n", i, val & 7); + ret = write(fd, &event_data, sizeof(event_data)); + } + val >>= 3; + } + } + } + + if (close(fd) != 0) + perror("close"); + else + printf("[POEG]close\n"); + + return 0; +}