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Thu, 8 Dec 2022 07:26:47 -0500 (EST) From: Klaus Jensen To: qemu-devel@nongnu.org Cc: Keith Busch , Klaus Jensen , Jinhao Fan , qemu-block@nongnu.org, Klaus Jensen Subject: [PATCH v2 1/3] hw/nvme: use QOM accessors Date: Thu, 8 Dec 2022 13:26:40 +0100 Message-Id: <20221208122642.80574-2-its@irrelevant.dk> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208122642.80574-1-its@irrelevant.dk> References: <20221208122642.80574-1-its@irrelevant.dk> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=14672; i=k.jensen@samsung.com; h=from:subject; bh=YKD3FMQzHHSanaA1nz49QpYFdpT+GMImWpmsnTBS2qc=; b=owJ4nAFtAZL+kA0DAAoBTeGvMW1PDekByyZiAGOR2AJdSXFK7HQtzDzYytN8I85Y0Lw4lEDIn6vr d5ISRxmFF4kBMwQAAQoAHRYhBFIoM6p14tzmokdmwE3hrzFtTw3pBQJjkdgCAAoJEE3hrzFtTw3p26 MH/iltQ+4vqtaAScZ9An+gMWQTwWtv2fuIIt6ORMDloc9yFw34d1gcDPxeQbBe7sT4lDlKAjDvLVoP ZdlUfxzBwas44tEGE0uS1xy8UWvkrZudD6IEqR/HSX6dfRI5iOXObCK7lp8S4iCBOddz01Pf/qyS93 8t1aLUgObFIqUIlfwnl6lBJcctPisN5sgHjOA9i/Mjhwf+y9Ovzrky7PRCbh2ZjziNdiygzqWCOYp/ Tsm+mmIDqV5ncplbezn/fAOdKNY9RzWta0tV2trkdt/clJHmue11tgaRS4C1iIhMODHWb76zoFK3La sXD2fuPBpNwMCoxYQYR8pAgqsD2AIzJDBEAapD X-Developer-Key: i=k.jensen@samsung.com; a=openpgp; fpr=DDCA4D9C9EF931CC3468427263D56FC5E55DA838 Received-SPF: pass client-ip=66.111.4.26; envelope-from=its@irrelevant.dk; helo=out2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Klaus Jensen Replace various ->parent_obj use with the equivalent QOM accessors. Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daudé --- hw/nvme/ctrl.c | 89 +++++++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 41 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index e54276dc1dc7..6b70c1e39831 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -449,7 +449,7 @@ static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size) return 0; } - return pci_dma_read(&n->parent_obj, addr, buf, size); + return pci_dma_read(PCI_DEVICE(n), addr, buf, size); } static int nvme_addr_write(NvmeCtrl *n, hwaddr addr, const void *buf, int size) @@ -469,7 +469,7 @@ static int nvme_addr_write(NvmeCtrl *n, hwaddr addr, const void *buf, int size) return 0; } - return pci_dma_write(&n->parent_obj, addr, buf, size); + return pci_dma_write(PCI_DEVICE(n), addr, buf, size); } static bool nvme_nsid_valid(NvmeCtrl *n, uint32_t nsid) @@ -514,24 +514,27 @@ static uint8_t nvme_sq_empty(NvmeSQueue *sq) static void nvme_irq_check(NvmeCtrl *n) { + PCIDevice *pci = PCI_DEVICE(n); uint32_t intms = ldl_le_p(&n->bar.intms); - if (msix_enabled(&(n->parent_obj))) { + if (msix_enabled(pci)) { return; } if (~intms & n->irq_status) { - pci_irq_assert(&n->parent_obj); + pci_irq_assert(pci); } else { - pci_irq_deassert(&n->parent_obj); + pci_irq_deassert(pci); } } static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq) { + PCIDevice *pci = PCI_DEVICE(n); + if (cq->irq_enabled) { - if (msix_enabled(&(n->parent_obj))) { + if (msix_enabled(pci)) { trace_pci_nvme_irq_msix(cq->vector); - msix_notify(&(n->parent_obj), cq->vector); + msix_notify(pci, cq->vector); } else { trace_pci_nvme_irq_pin(); assert(cq->vector < 32); @@ -546,7 +549,7 @@ static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq) static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq) { if (cq->irq_enabled) { - if (msix_enabled(&(n->parent_obj))) { + if (msix_enabled(PCI_DEVICE(n))) { return; } else { assert(cq->vector < 32); @@ -570,7 +573,7 @@ static void nvme_req_clear(NvmeRequest *req) static inline void nvme_sg_init(NvmeCtrl *n, NvmeSg *sg, bool dma) { if (dma) { - pci_dma_sglist_init(&sg->qsg, &n->parent_obj, 0); + pci_dma_sglist_init(&sg->qsg, PCI_DEVICE(n), 0); sg->flags = NVME_SG_DMA; } else { qemu_iovec_init(&sg->iov, 0); @@ -1333,7 +1336,7 @@ static inline void nvme_blk_write(BlockBackend *blk, int64_t offset, static void nvme_update_cq_head(NvmeCQueue *cq) { - pci_dma_read(&cq->ctrl->parent_obj, cq->db_addr, &cq->head, + pci_dma_read(PCI_DEVICE(cq->ctrl), cq->db_addr, &cq->head, sizeof(cq->head)); trace_pci_nvme_shadow_doorbell_cq(cq->cqid, cq->head); } @@ -1363,7 +1366,7 @@ static void nvme_post_cqes(void *opaque) req->cqe.sq_id = cpu_to_le16(sq->sqid); req->cqe.sq_head = cpu_to_le16(sq->head); addr = cq->dma_addr + cq->tail * n->cqe_size; - ret = pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe, + ret = pci_dma_write(PCI_DEVICE(n), addr, (void *)&req->cqe, sizeof(req->cqe)); if (ret) { trace_pci_nvme_err_addr_write(addr); @@ -4615,6 +4618,7 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req) static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n) { + PCIDevice *pci = PCI_DEVICE(n); uint16_t offset = (cq->cqid << 3) + (1 << 2); n->cq[cq->cqid] = NULL; @@ -4625,8 +4629,8 @@ static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n) event_notifier_set_handler(&cq->notifier, NULL); event_notifier_cleanup(&cq->notifier); } - if (msix_enabled(&n->parent_obj)) { - msix_vector_unuse(&n->parent_obj, cq->vector); + if (msix_enabled(pci)) { + msix_vector_unuse(pci, cq->vector); } if (cq->cqid) { g_free(cq); @@ -4664,8 +4668,10 @@ static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr, uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled) { - if (msix_enabled(&n->parent_obj)) { - msix_vector_use(&n->parent_obj, vector); + PCIDevice *pci = PCI_DEVICE(n); + + if (msix_enabled(pci)) { + msix_vector_use(pci, vector); } cq->ctrl = n; cq->cqid = cqid; @@ -4716,7 +4722,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req) trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_PRP_OFFSET | NVME_DNR; } - if (unlikely(!msix_enabled(&n->parent_obj) && vector)) { + if (unlikely(!msix_enabled(PCI_DEVICE(n)) && vector)) { trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } @@ -5959,6 +5965,7 @@ static uint16_t nvme_assign_virt_res_to_sec(NvmeCtrl *n, NvmeRequest *req, static uint16_t nvme_virt_set_state(NvmeCtrl *n, uint16_t cntlid, bool online) { + PCIDevice *pci = PCI_DEVICE(n); NvmeCtrl *sn = NULL; NvmeSecCtrlEntry *sctrl; int vf_index; @@ -5968,9 +5975,9 @@ static uint16_t nvme_virt_set_state(NvmeCtrl *n, uint16_t cntlid, bool online) return NVME_INVALID_CTRL_ID | NVME_DNR; } - if (!pci_is_vf(&n->parent_obj)) { + if (!pci_is_vf(pci)) { vf_index = le16_to_cpu(sctrl->vfn) - 1; - sn = NVME(pcie_sriov_get_vf_at_index(&n->parent_obj, vf_index)); + sn = NVME(pcie_sriov_get_vf_at_index(pci, vf_index)); } if (online) { @@ -6028,6 +6035,7 @@ static uint16_t nvme_virt_mngmt(NvmeCtrl *n, NvmeRequest *req) static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) { + PCIDevice *pci = PCI_DEVICE(n); uint64_t dbs_addr = le64_to_cpu(req->cmd.dptr.prp1); uint64_t eis_addr = le64_to_cpu(req->cmd.dptr.prp2); int i; @@ -6054,8 +6062,7 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) */ sq->db_addr = dbs_addr + (i << 3); sq->ei_addr = eis_addr + (i << 3); - pci_dma_write(&n->parent_obj, sq->db_addr, &sq->tail, - sizeof(sq->tail)); + pci_dma_write(pci, sq->db_addr, &sq->tail, sizeof(sq->tail)); if (n->params.ioeventfd && sq->sqid != 0) { if (!nvme_init_sq_ioeventfd(sq)) { @@ -6068,8 +6075,7 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) /* CAP.DSTRD is 0, so offset of ith cq db_addr is (i<<3)+(1<<2) */ cq->db_addr = dbs_addr + (i << 3) + (1 << 2); cq->ei_addr = eis_addr + (i << 3) + (1 << 2); - pci_dma_write(&n->parent_obj, cq->db_addr, &cq->head, - sizeof(cq->head)); + pci_dma_write(pci, cq->db_addr, &cq->head, sizeof(cq->head)); if (n->params.ioeventfd && cq->cqid != 0) { if (!nvme_init_cq_ioeventfd(cq)) { @@ -6141,14 +6147,14 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req) static void nvme_update_sq_eventidx(const NvmeSQueue *sq) { - pci_dma_write(&sq->ctrl->parent_obj, sq->ei_addr, &sq->tail, + pci_dma_write(PCI_DEVICE(sq->ctrl), sq->ei_addr, &sq->tail, sizeof(sq->tail)); trace_pci_nvme_eventidx_sq(sq->sqid, sq->tail); } static void nvme_update_sq_tail(NvmeSQueue *sq) { - pci_dma_read(&sq->ctrl->parent_obj, sq->db_addr, &sq->tail, + pci_dma_read(PCI_DEVICE(sq->ctrl), sq->db_addr, &sq->tail, sizeof(sq->tail)); trace_pci_nvme_shadow_doorbell_sq(sq->sqid, sq->tail); } @@ -6216,7 +6222,7 @@ static void nvme_update_msixcap_ts(PCIDevice *pci_dev, uint32_t table_size) static void nvme_activate_virt_res(NvmeCtrl *n) { - PCIDevice *pci_dev = &n->parent_obj; + PCIDevice *pci_dev = PCI_DEVICE(n); NvmePriCtrlCap *cap = &n->pri_ctrl_cap; NvmeSecCtrlEntry *sctrl; @@ -6239,7 +6245,7 @@ static void nvme_activate_virt_res(NvmeCtrl *n) static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst) { - PCIDevice *pci_dev = &n->parent_obj; + PCIDevice *pci_dev = PCI_DEVICE(n); NvmeSecCtrlEntry *sctrl; NvmeNamespace *ns; int i; @@ -6356,7 +6362,7 @@ static int nvme_start_ctrl(NvmeCtrl *n) uint32_t page_size = 1 << page_bits; NvmeSecCtrlEntry *sctrl = nvme_sctrl(n); - if (pci_is_vf(&n->parent_obj) && !sctrl->scs) { + if (pci_is_vf(PCI_DEVICE(n)) && !sctrl->scs) { trace_pci_nvme_err_startfail_virt_state(le16_to_cpu(sctrl->nvi), le16_to_cpu(sctrl->nvq), sctrl->scs ? "ONLINE" : @@ -6471,6 +6477,7 @@ static void nvme_cmb_enable_regs(NvmeCtrl *n) static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, unsigned size) { + PCIDevice *pci = PCI_DEVICE(n); uint64_t cap = ldq_le_p(&n->bar.cap); uint32_t cc = ldl_le_p(&n->bar.cc); uint32_t intms = ldl_le_p(&n->bar.intms); @@ -6494,7 +6501,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, switch (offset) { case NVME_REG_INTMS: - if (unlikely(msix_enabled(&(n->parent_obj)))) { + if (unlikely(msix_enabled(pci))) { NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, "undefined access to interrupt mask set" " when MSI-X is enabled"); @@ -6507,7 +6514,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, nvme_irq_check(n); break; case NVME_REG_INTMC: - if (unlikely(msix_enabled(&(n->parent_obj)))) { + if (unlikely(msix_enabled(pci))) { NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, "undefined access to interrupt mask clr" " when MSI-X is enabled"); @@ -6732,7 +6739,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size) return 0; } - if (pci_is_vf(&n->parent_obj) && !nvme_sctrl(n)->scs && + if (pci_is_vf(PCI_DEVICE(n)) && !nvme_sctrl(n)->scs && addr != NVME_REG_CSTS) { trace_pci_nvme_err_ignored_mmio_vf_offline(addr, size); return 0; @@ -6753,6 +6760,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size) static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) { + PCIDevice *pci = PCI_DEVICE(n); uint32_t qid; if (unlikely(addr & ((1 << 2) - 1))) { @@ -6820,8 +6828,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) start_sqs = nvme_cq_full(cq) ? 1 : 0; cq->head = new_head; if (!qid && n->dbbuf_enabled) { - pci_dma_write(&n->parent_obj, cq->db_addr, &cq->head, - sizeof(cq->head)); + pci_dma_write(pci, cq->db_addr, &cq->head, sizeof(cq->head)); } if (start_sqs) { NvmeSQueue *sq; @@ -6894,8 +6901,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) * including ones that run on Linux, are not updating Admin Queues, * so we can't trust reading it for an appropriate sq tail. */ - pci_dma_write(&n->parent_obj, sq->db_addr, &sq->tail, - sizeof(sq->tail)); + pci_dma_write(pci, sq->db_addr, &sq->tail, sizeof(sq->tail)); } qemu_bh_schedule(sq->bh); @@ -6909,7 +6915,7 @@ static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data, trace_pci_nvme_mmio_write(addr, data, size); - if (pci_is_vf(&n->parent_obj) && !nvme_sctrl(n)->scs && + if (pci_is_vf(PCI_DEVICE(n)) && !nvme_sctrl(n)->scs && addr != NVME_REG_CSTS) { trace_pci_nvme_err_ignored_mmio_vf_offline(addr, size); return; @@ -7093,10 +7099,11 @@ static void nvme_init_state(NvmeCtrl *n) NvmePriCtrlCap *cap = &n->pri_ctrl_cap; NvmeSecCtrlList *list = &n->sec_ctrl_list; NvmeSecCtrlEntry *sctrl; + PCIDevice *pci = PCI_DEVICE(n); uint8_t max_vfs; int i; - if (pci_is_vf(&n->parent_obj)) { + if (pci_is_vf(pci)) { sctrl = nvme_sctrl(n); max_vfs = 0; n->conf_ioqpairs = sctrl->nvq ? le16_to_cpu(sctrl->nvq) - 1 : 0; @@ -7125,7 +7132,7 @@ static void nvme_init_state(NvmeCtrl *n) cap->cntlid = cpu_to_le16(n->cntlid); cap->crt = NVME_CRT_VQ | NVME_CRT_VI; - if (pci_is_vf(&n->parent_obj)) { + if (pci_is_vf(pci)) { cap->vqprt = cpu_to_le16(1 + n->conf_ioqpairs); } else { cap->vqprt = cpu_to_le16(1 + n->params.max_ioqpairs - @@ -7138,7 +7145,7 @@ static void nvme_init_state(NvmeCtrl *n) cap->vqfrt / MAX(max_vfs, 1); } - if (pci_is_vf(&n->parent_obj)) { + if (pci_is_vf(pci)) { cap->viprt = cpu_to_le16(n->conf_msix_qsize); } else { cap->viprt = cpu_to_le16(n->params.msix_qsize - @@ -7445,7 +7452,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev) stl_le_p(&n->bar.vs, NVME_SPEC_VER); n->bar.intmc = n->bar.intms = 0; - if (pci_is_vf(&n->parent_obj) && !sctrl->scs) { + if (pci_is_vf(pci_dev) && !sctrl->scs) { stl_le_p(&n->bar.csts, NVME_CSTS_FAILED); } } @@ -7483,6 +7490,7 @@ void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns) static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n = NVME(pci_dev); + DeviceState *dev = DEVICE(pci_dev); NvmeNamespace *ns; Error *local_err = NULL; NvmeCtrl *pn = NVME(pcie_sriov_get_pf(pci_dev)); @@ -7502,8 +7510,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) return; } - qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS, - &pci_dev->qdev, n->parent_obj.qdev.id); + qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, dev->id); if (nvme_init_subsys(n, errp)) { error_propagate(errp, local_err); From patchwork Thu Dec 8 12:26:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Klaus Jensen X-Patchwork-Id: 1713726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=irrelevant.dk header.i=@irrelevant.dk header.a=rsa-sha256 header.s=fm1 header.b=Fn1gMoFW; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.a=rsa-sha256 header.s=fm2 header.b=NGrSQ4kY; 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Thu, 8 Dec 2022 07:26:49 -0500 (EST) From: Klaus Jensen To: qemu-devel@nongnu.org Cc: Keith Busch , Klaus Jensen , Jinhao Fan , qemu-block@nongnu.org, Klaus Jensen Subject: [PATCH v2 2/3] hw/nvme: rename shadow doorbell related trace events Date: Thu, 8 Dec 2022 13:26:41 +0100 Message-Id: <20221208122642.80574-3-its@irrelevant.dk> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208122642.80574-1-its@irrelevant.dk> References: <20221208122642.80574-1-its@irrelevant.dk> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4041; i=k.jensen@samsung.com; h=from:subject; bh=UosRnHKGmo/xC0PH2S2s2Othn36I78LHfhF8dCRCg5Q=; b=owJ4nJvAy8zAxej7cL1hrj/vS8bTakkMyRNvMJ0OdeG+WlmmvuiuRyODxodV+9MlP2RZiXItNdRh NnqaebuT0ZiFgZGLQVZMkSVIw3hV6aM7zxa5px2AGcTKBDKFgYtTACYSHsb+P63C+2xUTt/3x64d13 ojHkgHH15wZH69TZCDS8Yu0bPBnYvy8r/+vahUULeQ7+KJrTd+vnJ4XrOV6fPF7r6lpn8KRbKaa9te X7ubY60icbJlxolIY+moL4XaF1kayxlsXsfd0jiidXflhe+a6n+lOng8uSbxmb8uyUhLPhqyXlycqU yg+aa0wAerZ9w7UmwljjgsjFJNSZZWrzhz81Gv1hVFl5oP96d6Pitv7L29ZFfsn3y9qDf6rmEFz4r2 PI9J+G7qINa7/ssWqbK2iJ8MZQtTn6pNuMK8bkN76tWUl+p2OssdVPhfy3/646qU+qi8vNOMe5H1Jl vFBU4xPRONPdde33LH64AMf6xh/AMARTulgw== X-Developer-Key: i=k.jensen@samsung.com; a=openpgp; fpr=DDCA4D9C9EF931CC3468427263D56FC5E55DA838 Received-SPF: pass client-ip=66.111.4.26; envelope-from=its@irrelevant.dk; helo=out2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Klaus Jensen Rename the trace events related to writing the event index and reading the doorbell value to make it more clear that the event is associated with an actual update (write or read respectively). Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daudé --- hw/nvme/ctrl.c | 11 +++++++---- hw/nvme/trace-events | 8 ++++---- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 6b70c1e39831..cfab21b3436e 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -1337,8 +1337,9 @@ static inline void nvme_blk_write(BlockBackend *blk, int64_t offset, static void nvme_update_cq_head(NvmeCQueue *cq) { pci_dma_read(PCI_DEVICE(cq->ctrl), cq->db_addr, &cq->head, - sizeof(cq->head)); - trace_pci_nvme_shadow_doorbell_cq(cq->cqid, cq->head); + sizeof(cq->head)); + + trace_pci_nvme_update_cq_head(cq->cqid, cq->head); } static void nvme_post_cqes(void *opaque) @@ -6147,16 +6148,18 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req) static void nvme_update_sq_eventidx(const NvmeSQueue *sq) { + trace_pci_nvme_update_sq_eventidx(sq->sqid, sq->tail); + pci_dma_write(PCI_DEVICE(sq->ctrl), sq->ei_addr, &sq->tail, sizeof(sq->tail)); - trace_pci_nvme_eventidx_sq(sq->sqid, sq->tail); } static void nvme_update_sq_tail(NvmeSQueue *sq) { pci_dma_read(PCI_DEVICE(sq->ctrl), sq->db_addr, &sq->tail, sizeof(sq->tail)); - trace_pci_nvme_shadow_doorbell_sq(sq->sqid, sq->tail); + + trace_pci_nvme_update_sq_tail(sq->sqid, sq->tail); } static void nvme_process_sq(void *opaque) diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events index fccb79f48973..b16f2260b4fd 100644 --- a/hw/nvme/trace-events +++ b/hw/nvme/trace-events @@ -84,8 +84,8 @@ pci_nvme_enqueue_event_noqueue(int queued) "queued %d" pci_nvme_enqueue_event_masked(uint8_t typ) "type 0x%"PRIx8"" pci_nvme_no_outstanding_aers(void) "ignoring event; no outstanding AERs" pci_nvme_enqueue_req_completion(uint16_t cid, uint16_t cqid, uint32_t dw0, uint32_t dw1, uint16_t status) "cid %"PRIu16" cqid %"PRIu16" dw0 0x%"PRIx32" dw1 0x%"PRIx32" status 0x%"PRIx16"" -pci_nvme_eventidx_cq(uint16_t cqid, uint16_t new_eventidx) "cqid %"PRIu16" new_eventidx %"PRIu16"" -pci_nvme_eventidx_sq(uint16_t sqid, uint16_t new_eventidx) "sqid %"PRIu16" new_eventidx %"PRIu16"" +pci_nvme_update_cq_eventidx(uint16_t cqid, uint16_t new_eventidx) "cqid %"PRIu16" new_eventidx %"PRIu16"" +pci_nvme_update_sq_eventidx(uint16_t sqid, uint16_t new_eventidx) "sqid %"PRIu16" new_eventidx %"PRIu16"" pci_nvme_mmio_read(uint64_t addr, unsigned size) "addr 0x%"PRIx64" size %d" pci_nvme_mmio_write(uint64_t addr, uint64_t data, unsigned size) "addr 0x%"PRIx64" data 0x%"PRIx64" size %d" pci_nvme_mmio_doorbell_cq(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16" new_head %"PRIu16"" @@ -102,8 +102,8 @@ pci_nvme_mmio_start_success(void) "setting controller enable bit succeeded" pci_nvme_mmio_stopped(void) "cleared controller enable bit" pci_nvme_mmio_shutdown_set(void) "shutdown bit set" pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" -pci_nvme_shadow_doorbell_cq(uint16_t cqid, uint16_t new_shadow_doorbell) "cqid %"PRIu16" new_shadow_doorbell %"PRIu16"" -pci_nvme_shadow_doorbell_sq(uint16_t sqid, uint16_t new_shadow_doorbell) "sqid %"PRIu16" new_shadow_doorbell %"PRIu16"" +pci_nvme_update_cq_head(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16" new_head %"PRIu16"" +pci_nvme_update_sq_tail(uint16_t sqid, uint16_t new_tail) "sqid %"PRIu16" new_tail %"PRIu16"" pci_nvme_open_zone(uint64_t slba, uint32_t zone_idx, int all) "open zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" pci_nvme_close_zone(uint64_t slba, uint32_t zone_idx, int all) "close zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" pci_nvme_finish_zone(uint64_t slba, uint32_t zone_idx, int all) "finish zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" From patchwork Thu Dec 8 12:26:42 2022 Content-Type: text/plain; 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Thu, 8 Dec 2022 07:26:50 -0500 (EST) From: Klaus Jensen To: qemu-devel@nongnu.org Cc: Keith Busch , Klaus Jensen , Jinhao Fan , qemu-block@nongnu.org, Klaus Jensen , qemu-stable@nongnu.org, qemu-riscv@nongnu.org, Guenter Roeck Subject: [PATCH v2 3/3] hw/nvme: fix missing cq eventidx update Date: Thu, 8 Dec 2022 13:26:42 +0100 Message-Id: <20221208122642.80574-4-its@irrelevant.dk> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208122642.80574-1-its@irrelevant.dk> References: <20221208122642.80574-1-its@irrelevant.dk> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1401; i=k.jensen@samsung.com; h=from:subject; bh=HpbZnq35xbrUDphMGVz1enWTo7nx3csjTn0hDhTamJA=; b=owJ4nAFtAZL+kA0DAAoBTeGvMW1PDekByyZiAGOR2ALDL6JcvDCNqfcAGwYxC/WJi7YP5bM7N7e8 I6wmKo58YIkBMwQAAQoAHRYhBFIoM6p14tzmokdmwE3hrzFtTw3pBQJjkdgCAAoJEE3hrzFtTw3pB9 gH/A3SfMXiQLE53U32NvvUL4o6Zv0m22QSdhT/caNRYnhlbIMQ6jlNNf3uPrWMptq0hP8RziRUl9NA U9jDXdJN8KVCNQFl6Yi0Sl9CL3LHgUl2/ZjB+GSE4bkLxIhFGCW2CAxoxsD0nmQ1N+0eARzk0S3WOs 5qNjxRG3LYBDcFFISBYfzu6wjuuWrcL8EYhAvGsRyKQopzPXN5xqq11a+ED5wSn/7xxDWyacFWkdcz r4yG2BE5JTfRKB2XdaLofAQQo1wVFJEQHEOZZnE7U957WRLB/Rztom1peWoQagkvEV0hrHNshK2JMp W2vkXga6jPRlbbDT1jqBvydCQKVpboKp/SC6Ls X-Developer-Key: i=k.jensen@samsung.com; a=openpgp; fpr=DDCA4D9C9EF931CC3468427263D56FC5E55DA838 Received-SPF: pass client-ip=66.111.4.26; envelope-from=its@irrelevant.dk; helo=out2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Klaus Jensen Prior to reading the shadow doorbell cq head, we have to update the eventidx. Otherwise, we risk that the driver will skip an mmio doorbell write. This happens on riscv64, as reported by Guenter. Adding the missing update to the cq eventidx fixes the issue. Fixes: 3f7fe8de3d49 ("hw/nvme: Implement shadow doorbell buffer support") Cc: qemu-stable@nongnu.org Cc: qemu-riscv@nongnu.org Reported-by: Guenter Roeck Signed-off-by: Klaus Jensen Tested-by: Guenter Roeck --- hw/nvme/ctrl.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index cfab21b3436e..f6cc766aba4a 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -1334,6 +1334,14 @@ static inline void nvme_blk_write(BlockBackend *blk, int64_t offset, } } +static void nvme_update_cq_eventidx(const NvmeCQueue *cq) +{ + trace_pci_nvme_update_cq_eventidx(cq->cqid, cq->head); + + pci_dma_write(PCI_DEVICE(cq->ctrl), cq->ei_addr, &cq->head, + sizeof(cq->head)); +} + static void nvme_update_cq_head(NvmeCQueue *cq) { pci_dma_read(PCI_DEVICE(cq->ctrl), cq->db_addr, &cq->head, @@ -1355,6 +1363,7 @@ static void nvme_post_cqes(void *opaque) hwaddr addr; if (n->dbbuf_enabled) { + nvme_update_cq_eventidx(cq); nvme_update_cq_head(cq); }