From patchwork Mon Mar 12 05:25:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 884312 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40060h22fzz9sRW for ; Mon, 12 Mar 2018 16:26:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751602AbeCLF0O (ORCPT ); Mon, 12 Mar 2018 01:26:14 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:31679 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751312AbeCLFZu (ORCPT ); Mon, 12 Mar 2018 01:25:50 -0400 X-UUID: 35f840c5283940dbaaf5576f5258dbfb-20180312 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 701671233; Mon, 12 Mar 2018 13:25:46 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 12 Mar 2018 13:25:44 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 12 Mar 2018 13:25:43 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Matthias Brugger , Rob Herring , Mark Rutland , Ian Campbell , Ryder Lee , "Chunfeng Yun" , , , , , Subject: [PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate Date: Mon, 12 Mar 2018 13:25:40 +0800 Message-ID: <94a7d3b1240297cd0cac82df52954d0a53d50d36.1520832210.git.chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.5042-8.2.9001-23714.005 X-TM-AS-Result: No-2.578600-8.000000-10 X-TMASE-MatchedRID: y/MOm6ldwRIoMmKpHm2CtdBX0gKZ7oz4KhNpTcvbdULfUZT83lbkEKML LA0X7NGu00qMv6F9X+5OSWjh7PrRHyjrjvzj49dingIgpj8eDcAZ1CdBJOsoY8RB0bsfrpPIadN +LNryVbvbFSuvRidU3PQvhLmRdgshLSG2HXYsKN/Mtxao5UbE9uKcm7/7fIIacKewl4qmyozv3B Pf2eyVbaamblpDwGRJaP/4Bex22oXw7JxwU0EvZMqEROLb/+yO4/0Jvn0rwAJmtL4Dw+zNb5hXf xzgoU6P X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.578600-8.000000 X-TMASE-Version: SMEX-12.5.0.5042-8.2.9001-23714.005 X-TMASE-POSTMAN: 2-d; X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add two properties of ref_clk and coefficient used by U2 slew rate calibrate which may vary on different SoCs Signed-off-by: Chunfeng Yun Reviewed-by: Matthias Brugger --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index 41e09ed..0d34b2b 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): - reg : offset and length of register shared by multiple ports, exclude port's private register. It is needed on mt2701 and mt8173, but not on mt2712. + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate + calibrate + - mediatek,src-coef : coefficient for slew rate calibrate, depends on + SoC process Required properties (port (child) node): - reg : address and length of the register set for the port.