From patchwork Sun Mar 11 11:19:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Gilboa X-Patchwork-Id: 884236 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mellanox.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zzfp75XjPzB3XC for ; Sun, 11 Mar 2018 23:00:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932220AbeCKMAq (ORCPT ); Sun, 11 Mar 2018 08:00:46 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:54453 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932217AbeCKMAq (ORCPT ); Sun, 11 Mar 2018 08:00:46 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from talgi@mellanox.com) with ESMTPS (AES256-SHA encrypted); 11 Mar 2018 13:20:39 +0200 Received: from gen-l-vrt-178.mtl.labs.mlnx (gen-l-vrt-178.mtl.labs.mlnx [10.137.178.1]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w2BBK4dI002763; Sun, 11 Mar 2018 13:20:04 +0200 Received: from gen-l-vrt-178.mtl.labs.mlnx (localhost [127.0.0.1]) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7) with ESMTP id w2BBK4gs011186; Sun, 11 Mar 2018 13:20:04 +0200 Received: (from talgi@localhost) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7/Submit) id w2BBK4TR011185; Sun, 11 Mar 2018 13:20:04 +0200 From: Tal Gilboa To: Bjorn Helgaas Cc: Linux PCI , Tariq Toukan , Tal Gilboa Subject: [PATCH next V2 1/5] PCI: Add a query function for PCI device's speed cap Date: Sun, 11 Mar 2018 13:19:29 +0200 Message-Id: <1520767173-11090-2-git-send-email-talgi@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1520767173-11090-1-git-send-email-talgi@mellanox.com> References: <1520767173-11090-1-git-send-email-talgi@mellanox.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org pcie_get_speed_cap() implements the logic for querying a PCI device's maximum speed capability. Change max_link_speed_show() function to use pcie_get_speed_cap(). Signed-off-by: Tal Gilboa --- drivers/pci/pci-sysfs.c | 22 +++++----------------- drivers/pci/pci.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 7 +++++++ 3 files changed, 54 insertions(+), 17 deletions(-) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 4933f027..c8b4854 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -159,29 +159,17 @@ static ssize_t max_link_speed_show(struct device *dev, struct device_attribute *attr, char *buf) { struct pci_dev *pci_dev = to_pci_dev(dev); - u32 linkcap; + enum pci_bus_speed speed; + const char *speed_str; int err; - const char *speed; - err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap); + err = pcie_get_speed_cap(pci_dev, &speed); if (err) return -EINVAL; - switch (linkcap & PCI_EXP_LNKCAP_SLS) { - case PCI_EXP_LNKCAP_SLS_8_0GB: - speed = "8 GT/s"; - break; - case PCI_EXP_LNKCAP_SLS_5_0GB: - speed = "5 GT/s"; - break; - case PCI_EXP_LNKCAP_SLS_2_5GB: - speed = "2.5 GT/s"; - break; - default: - speed = "Unknown speed"; - } + speed_str = PCIE_SPEED2STR(speed); - return sprintf(buf, "%s\n", speed); + return sprintf(buf, "%s\n", speed_str); } static DEVICE_ATTR_RO(max_link_speed); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8c71d1a..7620cc9 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5164,6 +5164,48 @@ int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, EXPORT_SYMBOL(pcie_get_minimum_link); /** + * pcie_get_speed_cap - queries for the PCI device's link speed capability + * @dev: PCI device to query + * @speed: storage for link speed + * + * This function queries the PCI device speed capability. + */ +int pcie_get_speed_cap(struct pci_dev *dev, enum pci_bus_speed *speed) +{ + u32 lnkcap; + int err1, err2; + + *speed = PCI_SPEED_UNKNOWN; + + err1 = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, + &lnkcap); + if (!err1 && lnkcap) { + if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) + *speed = PCIE_SPEED_8_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) + *speed = PCIE_SPEED_5_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) + *speed = PCIE_SPEED_2_5GT; + return 0; + } + + err2 = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, + &lnkcap); + if (!err2 && lnkcap) { /* PCIe r3.0-compliant */ + if (lnkcap & PCI_EXP_LNKCAP2_SLS_8_0GB) + *speed = PCIE_SPEED_8_0GT; + else if (lnkcap & PCI_EXP_LNKCAP2_SLS_5_0GB) + *speed = PCIE_SPEED_5_0GT; + else if (lnkcap & PCI_EXP_LNKCAP2_SLS_2_5GB) + *speed = PCIE_SPEED_2_5GT; + return 0; + } + + return err1 ? err1 : err2; +} +EXPORT_SYMBOL(pcie_get_speed_cap); + +/** * pci_select_bars - Make BAR mask from the type of resource * @dev: the PCI device for which BAR mask is made * @flags: resource type mask to be selected diff --git a/include/linux/pci.h b/include/linux/pci.h index e057e8c..54443e4 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -259,6 +259,12 @@ enum pci_bus_speed { PCI_SPEED_UNKNOWN = 0xff, }; +#define PCIE_SPEED2STR(speed) \ + ((speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ + (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ + (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ + "Unknown speed") + struct pci_cap_saved_data { u16 cap_nr; bool cap_extended; @@ -1077,6 +1083,7 @@ static inline int pci_is_managed(struct pci_dev *pdev) int pcie_set_mps(struct pci_dev *dev, int mps); int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, enum pcie_link_width *width); +int pcie_get_speed_cap(struct pci_dev *dev, enum pci_bus_speed *speed); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); From patchwork Sun Mar 11 11:19:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Gilboa X-Patchwork-Id: 884237 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mellanox.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zzfp83jw3zB3XD for ; Sun, 11 Mar 2018 23:00:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932217AbeCKMAr (ORCPT ); Sun, 11 Mar 2018 08:00:47 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:54463 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932126AbeCKMAq (ORCPT ); Sun, 11 Mar 2018 08:00:46 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from talgi@mellanox.com) with ESMTPS (AES256-SHA encrypted); 11 Mar 2018 13:20:40 +0200 Received: from gen-l-vrt-178.mtl.labs.mlnx (gen-l-vrt-178.mtl.labs.mlnx [10.137.178.1]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w2BBK6o8002862; Sun, 11 Mar 2018 13:20:06 +0200 Received: from gen-l-vrt-178.mtl.labs.mlnx (localhost [127.0.0.1]) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7) with ESMTP id w2BBK5ub011191; Sun, 11 Mar 2018 13:20:05 +0200 Received: (from talgi@localhost) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7/Submit) id w2BBK5lg011190; Sun, 11 Mar 2018 13:20:05 +0200 From: Tal Gilboa To: Bjorn Helgaas Cc: Linux PCI , Tariq Toukan , Tal Gilboa Subject: [PATCH next V2 2/5] PCI: Add a query function for PCI device's width cap Date: Sun, 11 Mar 2018 13:19:30 +0200 Message-Id: <1520767173-11090-3-git-send-email-talgi@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1520767173-11090-1-git-send-email-talgi@mellanox.com> References: <1520767173-11090-1-git-send-email-talgi@mellanox.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org pcie_get_width_cap() implements the logic for querying a PCI device's maximum width capability. Change max_link_width_show() function to use pcie_get_width_cap(). Signed-off-by: Tal Gilboa --- drivers/pci/pci-sysfs.c | 6 +++--- drivers/pci/pci.c | 23 +++++++++++++++++++++++ include/linux/pci.h | 1 + 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index c8b4854..ae30ba2 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -177,14 +177,14 @@ static ssize_t max_link_width_show(struct device *dev, struct device_attribute *attr, char *buf) { struct pci_dev *pci_dev = to_pci_dev(dev); - u32 linkcap; + enum pcie_link_width width; int err; - err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap); + err = pcie_get_width_cap(pci_dev, &width); if (err) return -EINVAL; - return sprintf(buf, "%u\n", (linkcap & PCI_EXP_LNKCAP_MLW) >> 4); + return sprintf(buf, "%u\n", width); } static DEVICE_ATTR_RO(max_link_width); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7620cc9..48b9fd6 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5206,6 +5206,29 @@ int pcie_get_speed_cap(struct pci_dev *dev, enum pci_bus_speed *speed) EXPORT_SYMBOL(pcie_get_speed_cap); /** + * pcie_get_width_cap - queries for the PCI device's link width capability. + * @dev: PCI device to query + * @width: storage for link width + * + * This function queries the PCI device width capability. + */ +int pcie_get_width_cap(struct pci_dev *dev, enum pcie_link_width *width) +{ + u32 lnkcap; + int err; + + *width = PCIE_LNK_WIDTH_UNKNOWN; + + err = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (!err && lnkcap) + /* Shift start of width mask by 4 to get actual speed cap */ + *width = (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; + + return err; +} +EXPORT_SYMBOL(pcie_get_width_cap); + +/** * pci_select_bars - Make BAR mask from the type of resource * @dev: the PCI device for which BAR mask is made * @flags: resource type mask to be selected diff --git a/include/linux/pci.h b/include/linux/pci.h index 54443e4..8242d3d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1084,6 +1084,7 @@ static inline int pci_is_managed(struct pci_dev *pdev) int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, enum pcie_link_width *width); int pcie_get_speed_cap(struct pci_dev *dev, enum pci_bus_speed *speed); +int pcie_get_width_cap(struct pci_dev *dev, enum pcie_link_width *width); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); From patchwork Sun Mar 11 11:19:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Gilboa X-Patchwork-Id: 884238 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mellanox.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zzfp965pPzB3X5 for ; Sun, 11 Mar 2018 23:00:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932214AbeCKMAs (ORCPT ); Sun, 11 Mar 2018 08:00:48 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:54486 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932126AbeCKMAs (ORCPT ); Sun, 11 Mar 2018 08:00:48 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from talgi@mellanox.com) with ESMTPS (AES256-SHA encrypted); 11 Mar 2018 13:20:41 +0200 Received: from gen-l-vrt-178.mtl.labs.mlnx (gen-l-vrt-178.mtl.labs.mlnx [10.137.178.1]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w2BBK7mN002892; Sun, 11 Mar 2018 13:20:07 +0200 Received: from gen-l-vrt-178.mtl.labs.mlnx (localhost [127.0.0.1]) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7) with ESMTP id w2BBK6pp011197; Sun, 11 Mar 2018 13:20:06 +0200 Received: (from talgi@localhost) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7/Submit) id w2BBK6Yu011196; Sun, 11 Mar 2018 13:20:06 +0200 From: Tal Gilboa To: Bjorn Helgaas Cc: Linux PCI , Tariq Toukan , Tal Gilboa Subject: [PATCH next V2 3/5] PCI: Print PCI device link status in kernel log Date: Sun, 11 Mar 2018 13:19:31 +0200 Message-Id: <1520767173-11090-4-git-send-email-talgi@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1520767173-11090-1-git-send-email-talgi@mellanox.com> References: <1520767173-11090-1-git-send-email-talgi@mellanox.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add pcie_print_link_status() function for querying and verifying a PCI device link status. The PCI speed and width are reported in kernel log. This provides a unified method for all PCI devices to report status and issues, instead of each device reporting in a different way, using different code. Signed-off-by: Tal Gilboa --- drivers/pci/pci.c | 25 +++++++++++++++++++++++++ include/linux/pci.h | 1 + 2 files changed, 26 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 48b9fd6..ac876c4 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5229,6 +5229,31 @@ int pcie_get_width_cap(struct pci_dev *dev, enum pcie_link_width *width) EXPORT_SYMBOL(pcie_get_width_cap); /** + * pcie_print_link_status - Reports the PCI device's link speed and width. + * @dev: PCI device to query + * + * This function checks whether the PCI device current speed and width are equal + * to the maximum PCI device capabilities. + */ +void pcie_print_link_status(struct pci_dev *dev) +{ + enum pcie_link_width width, width_cap; + enum pci_bus_speed speed, speed_cap; + + pcie_get_speed_cap(dev, &speed_cap); + pcie_get_width_cap(dev, &width_cap); + pcie_get_minimum_link(dev, &speed, &width); + + if (speed == speed_cap && width == width_cap) + pci_info(dev, "%s x%d link\n", PCIE_SPEED2STR(speed), width); + else + pci_info(dev, "%s x%d link (capable of %s x%d)\n", + PCIE_SPEED2STR(speed), width, + PCIE_SPEED2STR(speed_cap), width_cap); +} +EXPORT_SYMBOL(pcie_print_link_status); + +/** * pci_select_bars - Make BAR mask from the type of resource * @dev: the PCI device for which BAR mask is made * @flags: resource type mask to be selected diff --git a/include/linux/pci.h b/include/linux/pci.h index 8242d3d..4a20870 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1085,6 +1085,7 @@ int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, enum pcie_link_width *width); int pcie_get_speed_cap(struct pci_dev *dev, enum pci_bus_speed *speed); int pcie_get_width_cap(struct pci_dev *dev, enum pcie_link_width *width); +void pcie_print_link_status(struct pci_dev *dev); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); From patchwork Sun Mar 11 11:19:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Gilboa X-Patchwork-Id: 884239 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mellanox.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zzfpD5DvJzB3XC for ; Sun, 11 Mar 2018 23:00:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932222AbeCKMAv (ORCPT ); Sun, 11 Mar 2018 08:00:51 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:54528 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932126AbeCKMAv (ORCPT ); Sun, 11 Mar 2018 08:00:51 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from talgi@mellanox.com) with ESMTPS (AES256-SHA encrypted); 11 Mar 2018 13:20:42 +0200 Received: from gen-l-vrt-178.mtl.labs.mlnx (gen-l-vrt-178.mtl.labs.mlnx [10.137.178.1]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w2BBK8LL002936; Sun, 11 Mar 2018 13:20:08 +0200 Received: from gen-l-vrt-178.mtl.labs.mlnx (localhost [127.0.0.1]) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7) with ESMTP id w2BBK7Y7011202; Sun, 11 Mar 2018 13:20:07 +0200 Received: (from talgi@localhost) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7/Submit) id w2BBK7vW011201; Sun, 11 Mar 2018 13:20:07 +0200 From: Tal Gilboa To: Bjorn Helgaas Cc: Linux PCI , Tariq Toukan , Tal Gilboa Subject: [PATCH next V2 4/5] net/mlx4_core: Report PCI properties using dedicated function Date: Sun, 11 Mar 2018 13:19:32 +0200 Message-Id: <1520767173-11090-5-git-send-email-talgi@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1520767173-11090-1-git-send-email-talgi@mellanox.com> References: <1520767173-11090-1-git-send-email-talgi@mellanox.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Change mlx4 method of checking and reporting PCI status and maximum capabilities to use the pci driver functions instead of implementing them in the driver code. Signed-off-by: Tal Gilboa --- drivers/net/ethernet/mellanox/mlx4/main.c | 81 +------------------------------ 1 file changed, 1 insertion(+), 80 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c index 4d84cab..30cacac 100644 --- a/drivers/net/ethernet/mellanox/mlx4/main.c +++ b/drivers/net/ethernet/mellanox/mlx4/main.c @@ -623,85 +623,6 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) return 0; } -static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev, - enum pci_bus_speed *speed, - enum pcie_link_width *width) -{ - u32 lnkcap1, lnkcap2; - int err1, err2; - -#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ - - *speed = PCI_SPEED_UNKNOWN; - *width = PCIE_LNK_WIDTH_UNKNOWN; - - err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP, - &lnkcap1); - err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2, - &lnkcap2); - if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ - if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) - *speed = PCIE_SPEED_8_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) - *speed = PCIE_SPEED_5_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) - *speed = PCIE_SPEED_2_5GT; - } - if (!err1) { - *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; - if (!lnkcap2) { /* pre-r3.0 */ - if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) - *speed = PCIE_SPEED_5_0GT; - else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) - *speed = PCIE_SPEED_2_5GT; - } - } - - if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) { - return err1 ? err1 : - err2 ? err2 : -EINVAL; - } - return 0; -} - -static void mlx4_check_pcie_caps(struct mlx4_dev *dev) -{ - enum pcie_link_width width, width_cap; - enum pci_bus_speed speed, speed_cap; - int err; - -#define PCIE_SPEED_STR(speed) \ - (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ - speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ - speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ - "Unknown") - - err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap); - if (err) { - mlx4_warn(dev, - "Unable to determine PCIe device BW capabilities\n"); - return; - } - - err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width); - if (err || speed == PCI_SPEED_UNKNOWN || - width == PCIE_LNK_WIDTH_UNKNOWN) { - mlx4_warn(dev, - "Unable to determine PCI device chain minimum BW\n"); - return; - } - - if (width != width_cap || speed != speed_cap) - mlx4_warn(dev, - "PCIe BW is different than device's capability\n"); - - mlx4_info(dev, "PCIe link speed is %s, device supports %s\n", - PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); - mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n", - width, width_cap); - return; -} - /*The function checks if there are live vf, return the num of them*/ static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) { @@ -3475,7 +3396,7 @@ static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, * express device capabilities are under-satisfied by the bus. */ if (!mlx4_is_slave(dev)) - mlx4_check_pcie_caps(dev); + pcie_print_link_status(dev->persist->pdev); /* In master functions, the communication channel must be initialized * after obtaining its address from fw */ From patchwork Sun Mar 11 11:19:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Gilboa X-Patchwork-Id: 884240 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mellanox.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zzfpG6c89zB3XC for ; Sun, 11 Mar 2018 23:00:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932224AbeCKMAy (ORCPT ); Sun, 11 Mar 2018 08:00:54 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:54550 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932126AbeCKMAx (ORCPT ); Sun, 11 Mar 2018 08:00:53 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from talgi@mellanox.com) with ESMTPS (AES256-SHA encrypted); 11 Mar 2018 13:20:43 +0200 Received: from gen-l-vrt-178.mtl.labs.mlnx (gen-l-vrt-178.mtl.labs.mlnx [10.137.178.1]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w2BBK9gI002975; Sun, 11 Mar 2018 13:20:09 +0200 Received: from gen-l-vrt-178.mtl.labs.mlnx (localhost [127.0.0.1]) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7) with ESMTP id w2BBK9La011208; Sun, 11 Mar 2018 13:20:09 +0200 Received: (from talgi@localhost) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7/Submit) id w2BBK9iT011207; Sun, 11 Mar 2018 13:20:09 +0200 From: Tal Gilboa To: Bjorn Helgaas Cc: Linux PCI , Tariq Toukan , Tal Gilboa Subject: [PATCH next V2 5/5] net/mlx5: Report device PCI link status and issues Date: Sun, 11 Mar 2018 13:19:33 +0200 Message-Id: <1520767173-11090-6-git-send-email-talgi@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1520767173-11090-1-git-send-email-talgi@mellanox.com> References: <1520767173-11090-1-git-send-email-talgi@mellanox.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add a kernel log print for mlx5 PCI device's link status. Signed-off-by: Tal Gilboa --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 2ef641c9..6adad72 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1043,6 +1043,8 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); + pcie_print_link_status(dev->pdev); + /* on load removing any previous indication of internal error, device is * up */