From patchwork Mon Nov 28 07:40:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tobias Burnus X-Patchwork-Id: 1709585 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NLHTZ6RtTz23nT for ; Mon, 28 Nov 2022 18:41:21 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CFCB73854540 for ; Mon, 28 Nov 2022 07:41:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa1.mentor.iphmx.com (esa1.mentor.iphmx.com [68.232.129.153]) by sourceware.org (Postfix) with ESMTPS id A6B863858D3C for ; Mon, 28 Nov 2022 07:41:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A6B863858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com X-IronPort-AV: E=Sophos;i="5.96,199,1665475200"; d="diff'?scan'208";a="90998745" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa1.mentor.iphmx.com with ESMTP; 27 Nov 2022 23:41:04 -0800 IronPort-SDR: 25xxLddYNqGIhW3tmWSLhA0kDapDRPJ5tGmTyYYtIe+FYTKV74WIqydVzBu2EwrTkCpDCX8ygB 6ispHrEVlzxER1wDnmHJ6W5pUEWpuWjv5/SimQUmybvS/Od44j1nzaKHZ3ZukHtrzYe5ZQXG4r W3WSd6IUrxzOM67bdny0i+FE3BunW8NRN/2pxUoUwRQSJvyBUdOR5N0S5qcb0lYXEDS8Kc9jwl YXARBZT1C/SRihm/pcD6A0JALAmbjW3mFQMSDsZAyCUxlmmPomq7hoes5/lSCuqig/CqGXZLin zmk= Message-ID: <54ee69be-7101-c4e0-fbca-3c7c3f1101b8@codesourcery.com> Date: Mon, 28 Nov 2022 08:40:47 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Content-Language: en-US To: gcc-patches , Andrew Stubbs From: Tobias Burnus Subject: [Patch] gcn: Fix __builtin_gcn_first_call_this_thread_p X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-07.mgc.mentorg.com (139.181.222.7) To svr-ies-mbx-12.mgc.mentorg.com (139.181.222.12) X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" It turned out that cprop cleverly propagated the unspec_volatile to the preceding (pseudo)register, permitting to remove the 'set (s0) (pseudoregister)' at -O2. Unfortunately, it does matter whether the assignment is done to 's2' (previously: pseudoregister) or to s1. – Just having a hard register is not enough ... Solution: Use USE (alias gen_rtx_USE) instead. Additionally, I removed the s0 modification (that should lead to the unchanged result) by adding 'gcn_operand_part (DImode, reg, 1)' and then working with SImode. Result: if (__builtin_gcn_first_call_this_thread_p()) x = 42; becomes now (with -O2) the following; the builtin code is up to to (and including) '.L2', the rest is the 'if' and 'x=42': s_lshr_b32 s2, s1, 16 s_cmpk_lg_u32 s2, 12345 s_mov_b32 s12, scc s_mov_b32 vcc_lo, scc s_mov_b32 vcc_hi, 0 s_cbranch_vccz .L2 s_and_b32 s2, s1, 65535 (= 0xFFFF) s_or_b32 s1, s2, 809041920 (= 0x30390000 = (12345 << 16)) .L2: s_getpc_b64 s[2:3] s_add_u32 s2, s2, x@rel32@lo+4 s_addc_u32 s3, s3, x@rel32@hi+4 s_mov_b32 vcc_lo, s12 s_mov_b32 vcc_hi, 0 s_cbranch_vccz .L3 s_mov_b32 s12, 42 v_writelane_b32 v0, s12, 0 s_mov_b64 exec, 1 global_store_dword v1, v0, s[2:3] .L3: OK for mainline? Tobias ----------------- Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht München, HRB 106955 gcn: Fix __builtin_gcn_first_call_this_thread_p Contrary naive expectation, unspec_volatile (via prologue_use) did not prevent the cprop pass (at -O2) to remove the access to the s[0:1] (PRIVATE_SEGMENT_BUFFER_ARG) register as the volatile got just put on the preceeding pseudoregister. Solution: Use gen_rtx_USE instead. Additionally, this patch removes (gen_)prologue_use_di as it is then no longer used. Finally, as we already do bit manipulation, instead of using the full 64bit side - and then just keeping the value of 's0', just move directly to use only s1 of s[0:1] and do the bit manipulations there, generating more readable assembly code and better matching the '#else' branch. gcc/ChangeLog: * config/gcn/gcn.cc (gcn_expand_builtin_1): Work on s1 instead of s[0:1] and use USE to prevent removal of setting that register. * config/gcn/gcn.md (prologue_use_di): Remove. gcc/config/gcn/gcn.cc | 16 ++++++++-------- gcc/config/gcn/gcn.md | 13 ------------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index 6fb261318c4..c74fa007a21 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -4556,8 +4556,9 @@ gcn_expand_builtin_1 (tree exp, rtx target, rtx /*subtarget */ , rtx not_first = gen_label_rtx (); rtx reg = gen_rtx_REG (DImode, cfun->machine->args.reg[PRIVATE_SEGMENT_BUFFER_ARG]); - rtx cmp = force_reg (DImode, - gen_rtx_LSHIFTRT (DImode, reg, GEN_INT (48))); + reg = gcn_operand_part (DImode, reg, 1); + rtx cmp = force_reg (SImode, + gen_rtx_LSHIFTRT (SImode, reg, GEN_INT (16))); emit_insn (gen_cstoresi4 (result, gen_rtx_NE (BImode, cmp, GEN_INT(12345)), cmp, GEN_INT(12345))); @@ -4565,12 +4566,11 @@ gcn_expand_builtin_1 (tree exp, rtx target, rtx /*subtarget */ , const0_rtx), result)); emit_move_insn (reg, - force_reg (DImode, - gen_rtx_IOR (DImode, - gen_rtx_AND (DImode, reg, - GEN_INT (0x0000ffffffffffffL)), - GEN_INT (12345L << 48)))); - emit_insn (gen_prologue_use (reg)); + force_reg (SImode, + gen_rtx_IOR (SImode, + gen_rtx_AND (SImode, reg, GEN_INT (0x0000ffff)), + GEN_INT (12345L << 16)))); + emit_insn (gen_rtx_USE (VOIDmode, reg)); emit_label (not_first); } return result; diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index a8b9c28d115..92e9892c4f7 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -697,19 +697,6 @@ "" [(set_attr "length" "0")]) -(define_insn_and_split "prologue_use_di" - [(unspec_volatile [(match_operand:DI 0 "register_operand")] UNSPECV_PROLOGUE_USE)] - "" - "#" - "reload_completed" - [(unspec_volatile [(match_dup 0)] UNSPECV_PROLOGUE_USE) - (unspec_volatile [(match_dup 1)] UNSPECV_PROLOGUE_USE)] - { - operands[1] = gcn_operand_part (DImode, operands[0], 1); - operands[0] = gcn_operand_part (DImode, operands[0], 0); - } - [(set_attr "length" "0")]) - (define_expand "prologue" [(const_int 0)] ""