From patchwork Fri Mar 9 23:25:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 884056 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="A1i7v3kE"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="XSLwzb/q"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zyk7p6JYyz9shg for ; Sat, 10 Mar 2018 10:27:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932768AbeCIXZ4 (ORCPT ); Fri, 9 Mar 2018 18:25:56 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:53564 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932706AbeCIXZx (ORCPT ); Fri, 9 Mar 2018 18:25:53 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A04EE6050D; Fri, 9 Mar 2018 23:25:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520637952; bh=N8JvlhJb2C9rCSFDQBCQFNvGCLrWFyO0ZJqqybi7ZKI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A1i7v3kEF8MYzy4kgEuLEcI33GtpAmmIYVC1OPZrp3t8PjKIG+yrvmCIAaHLIQRXH JeiW3M1bU5Nrs+aSFPd+2lWEpAZr1KHjX6fLma7yOy+OEnwjYErWJd21Ky60DkZEf6 +CIx2GBjzxAFvZ4+h+j97y7Uh0ZDKFqntAWSxs5s= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9DD4D6050D; Fri, 9 Mar 2018 23:25:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520637951; bh=N8JvlhJb2C9rCSFDQBCQFNvGCLrWFyO0ZJqqybi7ZKI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XSLwzb/qVU02Cx1ow/zNcKENjicar0l7SvktZT6PT2uKE5Phn0cIPI3MeWXD5pYtq pOj5l7Y21GPcIap6fvHBgEMFyKTlmD/2BGPUmkEzoiUA7OiG1TPpFWI1s+lu3x3+6D MFtuXaZ6rANbecefSisGYJplzPhU1vQfnh5Q2Ujs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9DD4D6050D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: andy.gross@linaro.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org, rnayak@codeaurora.org, bjorn.andersson@linaro.org, linux-kernel@vger.kernel.org, sboyd@kernel.org, Lina Iyer , devicetree@vger.kernel.org Subject: [PATCH v4 02/10] dt-bindings: introduce RPMH RSC bindings for Qualcomm SoCs Date: Fri, 9 Mar 2018 16:25:35 -0700 Message-Id: <20180309232543.24636-3-ilina@codeaurora.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180309232543.24636-1-ilina@codeaurora.org> References: <20180309232543.24636-1-ilina@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device binding documentation for Qualcomm Technology Inc's RPMH RSC driver. The driver is used for communicating resource state requests for shared resources. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer Reviewed-by: Rob Herring --- Changes in v3: - Move to soc/qcom - Amend text per Stephen's suggestions Changes in v2: - Amend text to describe the registers in reg property - Add reg-names for the registers - Update examples to use GIC_SPI in interrupts instead of 0 - Rephrase incorrect description Changes in v3: - Fix unwanted capitalization - Remove clients from the examples, this doc does not describe them - Rephrase introductory paragraph - Remove hardware specifics from DT bindings --- .../devicetree/bindings/soc/qcom/rpmh-rsc.txt | 127 +++++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt diff --git a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt b/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt new file mode 100644 index 000000000000..dcf71a5b302f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt @@ -0,0 +1,127 @@ +RPMH RSC: +------------ + +Resource Power Manager Hardened (RPMH) is the mechanism for communicating with +the hardened resource accelerators on Qualcomm SoCs. Requests to the resources +can be written to the Trigger Command Set (TCS) registers and using a (addr, +val) pair and triggered. Messages in the TCS are then sent in sequence over an +internal bus. + +The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity +(Resource State Coordinator a.k.a RSC) that can handle a multiple sleep and +active/wake resource requests. Multiple such DRVs can exist in a SoC and can +be written to from Linux. The structure of each DRV follows the same template +with a few variations that are captured by the properties here. + +A TCS may be triggered from Linux or triggered by the F/W after all the CPUs +have powered off to facilitate idle power saving. TCS could be classified as - + + SLEEP, /* Triggered by F/W */ + WAKE, /* Triggered by F/W */ + ACTIVE, /* Triggered by Linux */ + CONTROL /* Triggered by F/W */ + +The order in which they are described in the DT, should match the hardware +configuration. + +Requests can be made for the state of a resource, when the subsystem is active +or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state +will be an aggregate of the sleep votes from each of those subsystems. Clients +may request a sleep value for their shared resources in addition to the active +mode requests. + +Properties: + +- compatible: + Usage: required + Value type: + Definition: Should be "qcom,rpmh-rsc". + +- reg: + Usage: required + Value type: + Definition: The first register specifies the base address of the DRV. + The second register specifies the start address of the + TCS. + +- reg-names: + Usage: required + Value type: + Definition: Maps the register specified in the reg property. Must be + "drv" and "tcs". + +- interrupts: + Usage: required + Value type: + Definition: The interrupt that trips when a message complete/response + is received for this DRV from the accelerators. + +- qcom,drv-id: + Usage: required + Value type: + Definition: the id of the DRV in the RSC block. + +- qcom,tcs-config: + Usage: required + Value type: + Definition: the tuple defining the configuration of TCS. + Must have 2 cells which describe each TCS type. + . + The order of the TCS must match the hardware + configuration. + - Cell #1 (TCS Type): TCS types to be specified - + SLEEP_TCS + WAKE_TCS + ACTIVE_TCS + CONTROL_TCS + - Cell #2 (Number of TCS): + +- label: + Usage: optional + Value type: + Definition: Name for the RSC. The name would be used in trace logs. + +Drivers that want to use the RSC to communicate with RPMH must specify their +bindings as child of the RSC controllers they wish to communicate with. + +Example 1: + +For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the +register offsets for DRV2 start at 0D00, the register calculations are like +this - +First tuple: 0x179C0000 + 0x10000 * 2 = 0x179E0000 +Second tuple: 0x179E0000 + 0xD00 = 0x179E0D00 + + apps_rsc: rsc@179e000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x179e0000 0x10000>, <0x179e0d00 0x3000>; + reg-names = "drv", "tcs"; + interrupts = ; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + }; + +Example 2: + +For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the +register offsets for DRV0 start at 01C00, the register calculations are like +this - +First tuple: 0xAF20000 +Second tuple: 0xAF20000 + 0x1C00 = 0xAF21C00 + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>, <0xaf21c00 0x3000>; + reg-names = "drv", "tcs"; + interrupts = ; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + };