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Signed-off-by: Vadym Kochan Acked-by: Krzysztof Kozlowski --- v2: no changes Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index ff25a134befa..b272fa4f08b5 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -4,7 +4,9 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. Required properties: -- compatible: "marvell,armada8k-pcie" +- compatible: Should be set to one of the following: + - "marvell,armada8k-pcie" : For A7K/8K family of SoCs + - "marvell,ac5-pcie" : For AC5 family of SoCs - reg: must contain two register regions - the control register region - the config space region From patchwork Thu Nov 24 13:58:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadym Kochan X-Patchwork-Id: 1708747 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=plvision.eu header.i=@plvision.eu header.a=rsa-sha256 header.s=selector2 header.b=ZjKA5tva; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XjU8RDiPQHCdi3l9hhfHqN3xS8n6YzRkV6hQE/tSShwOLMNW+nirPv5rOQBaW7epBTXRYq9pKH+FqXKmI14qHO6TrNC/X49W+JoS2hlH3ceO2xqzAecsV4k2ykM8tOxFD1J6rpf996mJz3FK60qSDeleSlR0lzcSTQRfpC9BSyQa67+2y803jGqt527ZrVat3pIJAjcyuDOO6TVT7Q4CF2g1dOf3q+F4x4MQUNBonuJGityUcOdm2xah5e1CQn4wWOSBnTDEJfGzW4+AypZM9KcBeoe2q+mu8tefyi9/faGon8xJoy0HTdUGLTWqEwUhKG4tJslhQa5+qnHodMm5Q7Lj8dECkuu5DdbTd3MBSE/qpRxFMpM1r3Ay60DPeu4vK4XL3r8/W3gVtT1MlWuh+J61xLqFkEcGQAclkYUw7Qp3z3K6FsHCy3VJ78beZ6lDs4kl/HaKAhyV4pVnVseJbJOBSGPVffd72V8RkZ7uiyk+UEPXq1rPsvnVyCsnxMFjaJFKnJOgHvNtnUHJiRmg735xILsZIUhaJGxqCr2htQmDJZP7xB0IPpQ9ex5NVbJM6NONVHomKIGKTDnBTA21+0dDuTi+s2tQq98hIzL5Vm8RpZx5V2d8EofVskTqBJ349v6rkarxRZMA3Yz1tM054SlY4Q4DkufhuOcCMOGgA2+toPpaXUT2LEjtgYSrVvFU8yL6X4EkOCD4rcwCHxGO8Ut79oifBWfM5xK/t8Vs8dZF/1wIDNnxyVy3a6pAuOC0292G2Cyo9ng6yzfHGPD91xPpOqgg0du/SmmBV6JCdnV+/mw7vgvQSvueiJJmOmr6Xg4DWGfS5ULYgH13XPKh4sHx4raGyAZIjm0tixrnNt9VB4iuSld6y1QdXfB2SMdnZa22HUevY4tfdt17uUjkyBUfDFf0uV6+ArB4H0EU8lCNdRvEMiQ1+FvBEAWdPC++sp3FU08/R0zO9lW/BjhMgfxFdnAMGDPaftCh31PU0veBy22nOsxZ9o2eu7nb+QIW+HE5SdotwaMonEeM8LUsqUINkFTpImGKGo8ZOrod4RUcK7xtccBkSOb/OxYuFV3115Fbv8tvE0tkQFOx+L2pVnWSYCh4BLw7iE664kR+tNr8VGYyE7SuDw/0zD8bM0QOBhxs1DE0xAg3hcHqZZzWsQUmceqKfB4dg4EIy7rc5DnplQgvQhcxsJ1aXGM/5il/1WvBSsmDNhDGoz/RrKSZl5/gImH9IcA6Fnoixranz5fARRh2EzPEY3QGHztdUiOj4rAmq/coc6Xx0louW+bxXBvBmu8KJtnV04cLeUs4WNinZIzjY4C1fLbQvK00L2mnhleMF13jCLIXW0mHTRC7AmhFyzQAFlG0CoFx9QYUzx+kFCO66YTZfODkAFvq0vbQTP4nvMc1o03bjSt6CibdL87wC9AbCHziqobmu2QnI09Yp2N+Om5fNF1ORlyiOduqrYhlEd0DQrWA39pGD1zfU0QBkciUuCq3bNM87BGNdWLsuKjARFpTuQ3Y2XakNaY9l8MP/sfH/m6dCqExR3g7NnB8Rr51Ld7BvNwjZQ9SqE/yp6mMcDwmNbITvxqdQebBhpRYnpoLkrohYf9VidpoYw== X-OriginatorOrg: plvision.eu X-MS-Exchange-CrossTenant-Network-Message-Id: 29010f78-bcd3-432c-ce1c-08dace240653 X-MS-Exchange-CrossTenant-AuthSource: VI1P190MB0317.EURP190.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2022 13:58:54.7740 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 03707b74-30f3-46b6-a0e0-ff0a7438c9c4 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OtuIh/UkBizsyZ97i68/aAtIPdurpoYDHjawOBcF0NBpXuQSDGBlh0sfRqqocxbUnAPdx1OCAk183ZbdFagjGq4Q/QZ+MRnEyeql4cWlPTc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7P190MB0758 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Raz Adashi pcie-armada8k driver is utilized to serve also AC5. Driver assumes interrupt mask registers are located in the same address inboth CPUs. This assumption is incorrect - fix it for AC5. Co-developed-by: Yuval Shaia Signed-off-by: Yuval Shaia Signed-off-by: Raz Adashi Signed-off-by: Vadym Kochan --- v2: 1) fix W1 warnings which caused by unused leftover code 2) Use one xlate function to translate ac5 dbi access. Also add mode description in comments about this translation. 3) Use correct name of Raz 4) Use matching data to pass the SoC specific params (type & ops) drivers/pci/controller/dwc/pcie-armada8k.c | 157 ++++++++++++++++----- 1 file changed, 119 insertions(+), 38 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index 5c999e15c357..bbe9a1750d0d 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -26,15 +27,26 @@ #define ARMADA8K_PCIE_MAX_LANES PCIE_LNK_X4 +enum armada8k_pcie_type { + ARMADA8K_PCIE_TYPE_A8K, + ARMADA8K_PCIE_TYPE_AC5 +}; + struct armada8k_pcie { struct dw_pcie *pci; struct clk *clk; struct clk *clk_reg; struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; unsigned int phy_count; + enum armada8k_pcie_type pcie_type; }; -#define PCIE_VENDOR_REGS_OFFSET 0x8000 +struct armada8k_pcie_of_data { + enum armada8k_pcie_type pcie_type; + const struct dw_pcie_ops *pcie_ops; +}; + +#define PCIE_VENDOR_REGS_OFFSET 0x8000 /* in ac5 is 0x10000 */ #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) #define PCIE_APP_LTSSM_EN BIT(2) @@ -48,10 +60,17 @@ struct armada8k_pcie { #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C) #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20) +#define PCIE_GLOBAL_INT_MASK2_REG (PCIE_VENDOR_REGS_OFFSET + 0x28) #define PCIE_INT_A_ASSERT_MASK BIT(9) #define PCIE_INT_B_ASSERT_MASK BIT(10) #define PCIE_INT_C_ASSERT_MASK BIT(11) #define PCIE_INT_D_ASSERT_MASK BIT(12) +#define PCIE_INT_A_ASSERT_MASK_AC5 BIT(12) +#define PCIE_INT_B_ASSERT_MASK_AC5 BIT(13) +#define PCIE_INT_C_ASSERT_MASK_AC5 BIT(14) +#define PCIE_INT_D_ASSERT_MASK_AC5 BIT(15) + +#define PCIE_ATU_ACCESS_MASK_AC5 GENMASK(21, 20) #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50) #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54) @@ -153,22 +172,11 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci) return 0; } -static int armada8k_pcie_start_link(struct dw_pcie *pci) -{ - u32 reg; - - /* Start LTSSM */ - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg |= PCIE_APP_LTSSM_EN; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); - - return 0; -} - static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) { u32 reg; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct armada8k_pcie *pcie = to_armada8k_pcie(pci); if (!dw_pcie_link_up(pci)) { /* Disable LTSSM state machine to enable configuration */ @@ -177,32 +185,41 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); } - /* Set the device to root complex mode */ - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); - reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); + if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_A8K) { + /* Set the device to root complex mode */ + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); + reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); + reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); - /* Set the PCIe master AxCache attributes */ - dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); - dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); + /* Set the PCIe master AxCache attributes */ + dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); + dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); - /* Set the PCIe master AxDomain attributes */ - reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); - reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); - reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); + /* Set the PCIe master AxDomain attributes */ + reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); + reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); + reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; + dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); - reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); - reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); - reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); + reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); + reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); + reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; + dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); + } /* Enable INT A-D interrupts */ - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); - reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | - PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); + if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5) { + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG); + reg |= PCIE_INT_A_ASSERT_MASK_AC5 | PCIE_INT_B_ASSERT_MASK_AC5 | + PCIE_INT_C_ASSERT_MASK_AC5 | PCIE_INT_D_ASSERT_MASK_AC5; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG, reg); + } else { + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); + reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | + PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); + } return 0; } @@ -258,9 +275,59 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie, return 0; } -static const struct dw_pcie_ops dw_pcie_ops = { +static u32 ac5_xlate_dbi_reg(u32 reg) +{ + /* Handle AC5 ATU access */ + if ((reg & ~0xfffff) == PCIE_ATU_ACCESS_MASK_AC5) { + reg &= 0xfffff; + /* ATU registers offset is 0xC00 + 0x200 * n, + * from RFU registers. + */ + reg = 0xc000 | (0x200 * (reg >> 9)) | (reg & 0xff); + } else if ((reg & 0xfffff000) == PCIE_VENDOR_REGS_OFFSET) { + /* PCIe RFU registers in A8K are at offset 0x8000 from base + * (0xf2600000) while in AC5 offset is 0x10000 from base + * (0x800a0000) therefore need the addition of 0x8000. + */ + reg += PCIE_VENDOR_REGS_OFFSET; + } + + return reg; +} + +static u32 ac5_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + u32 val; + + dw_pcie_read(base + ac5_xlate_dbi_reg(reg), size, &val); + return val; +} + +static void ac5_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + dw_pcie_write(base + ac5_xlate_dbi_reg(reg), size, val); +} + +static const struct dw_pcie_ops armada8k_dw_pcie_ops = { + .link_up = armada8k_pcie_link_up, +}; + +static const struct dw_pcie_ops ac5_dw_pcie_ops = { .link_up = armada8k_pcie_link_up, - .start_link = armada8k_pcie_start_link, + .read_dbi = ac5_pcie_read_dbi, + .write_dbi = ac5_pcie_write_dbi, +}; + +static const struct armada8k_pcie_of_data a8k_pcie_of_data = { + .pcie_type = ARMADA8K_PCIE_TYPE_A8K, + .pcie_ops = &armada8k_dw_pcie_ops, +}; + +static const struct armada8k_pcie_of_data ac5_pcie_of_data = { + .pcie_type = ARMADA8K_PCIE_TYPE_AC5, + .pcie_ops = &ac5_dw_pcie_ops, }; static int armada8k_pcie_probe(struct platform_device *pdev) @@ -268,9 +335,15 @@ static int armada8k_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct armada8k_pcie *pcie; struct device *dev = &pdev->dev; + const struct armada8k_pcie_of_data *data; struct resource *base; int ret; + data = of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; @@ -279,9 +352,10 @@ static int armada8k_pcie_probe(struct platform_device *pdev) if (!pci) return -ENOMEM; + pci->ops = data->pcie_ops; pci->dev = dev; - pci->ops = &dw_pcie_ops; + pcie->pcie_type = data->pcie_type; pcie->pci = pci; pcie->clk = devm_clk_get(dev, NULL); @@ -334,7 +408,14 @@ static int armada8k_pcie_probe(struct platform_device *pdev) } static const struct of_device_id armada8k_pcie_of_match[] = { - { .compatible = "marvell,armada8k-pcie", }, + { + .compatible = "marvell,armada8k-pcie", + .data = &a8k_pcie_of_data, + }, + { + .compatible = "marvell,ac5-pcie", + .data = &ac5_pcie_of_data, + }, {}, }; From patchwork Thu Nov 24 13:58:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadym Kochan X-Patchwork-Id: 1708748 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 24 Nov 2022 13:58:56 +0000 From: Vadym Kochan To: Thomas Petazzoni , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Elad Nachman , Vadym Kochan , Yuval Shaia Subject: [PATCH v2 3/3] PCI: armada8k: Add MSI support for AC5 SoC Date: Thu, 24 Nov 2022 15:58:28 +0200 Message-Id: <20221124135829.2551873-4-vadym.kochan@plvision.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221124135829.2551873-1-vadym.kochan@plvision.eu> References: <20221124135829.2551873-1-vadym.kochan@plvision.eu> X-ClientProxiedBy: FR3P281CA0120.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a3::18) To VI1P190MB0317.EURP190.PROD.OUTLOOK.COM (2603:10a6:802:38::26) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1P190MB0317:EE_|AM7P190MB0758:EE_ X-MS-Office365-Filtering-Correlation-Id: 779bcf49-8303-42fe-c21b-08dace24070d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Fix it by: 1. Enabling the relevant bits in init phase 2. Dispatch virtual IRQ handlers when MSI interrupts are received Also enable/disable PCIE_APP_LTSSM for AC5. Signed-off-by: Yuval Shaia Signed-off-by: Vadym Kochan --- v2: 1) fix W1 warnings which caused by unused leftover code 2) fix type in "requieres" word in the description drivers/pci/controller/dwc/pcie-armada8k.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index bbe9a1750d0d..7e02eddaeac0 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -50,6 +50,7 @@ struct armada8k_pcie_of_data { #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) #define PCIE_APP_LTSSM_EN BIT(2) +#define PCIE_APP_LTSSM_EN_AC5 BIT(24) #define PCIE_DEVICE_TYPE_SHIFT 4 #define PCIE_DEVICE_TYPE_MASK 0xF #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ @@ -69,6 +70,7 @@ struct armada8k_pcie_of_data { #define PCIE_INT_B_ASSERT_MASK_AC5 BIT(13) #define PCIE_INT_C_ASSERT_MASK_AC5 BIT(14) #define PCIE_INT_D_ASSERT_MASK_AC5 BIT(15) +#define PCIE_MSI_MASK_AC5 BIT(11) #define PCIE_ATU_ACCESS_MASK_AC5 GENMASK(21, 20) @@ -172,6 +174,16 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci) return 0; } +static void ac5_pcie_msi_init(struct dw_pcie *pci) +{ + u32 val; + + /* Set MSI bit in interrupt mask */ + val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); + val |= PCIE_MSI_MASK_AC5; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, val); +} + static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) { u32 reg; @@ -181,7 +193,10 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) if (!dw_pcie_link_up(pci)) { /* Disable LTSSM state machine to enable configuration */ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &= ~(PCIE_APP_LTSSM_EN); + if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5) + reg &= ~(PCIE_APP_LTSSM_EN_AC5); + else + reg &= ~(PCIE_APP_LTSSM_EN); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); } @@ -221,6 +236,9 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); } + if (IS_ENABLED(CONFIG_PCI_MSI) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)) + ac5_pcie_msi_init(pci); + return 0; } @@ -237,6 +255,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) */ val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); + if ((PCIE_MSI_MASK_AC5 & val) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)) + dw_handle_msi_irq(&pci->pp); return IRQ_HANDLED; }