From patchwork Wed Nov 23 15:36:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1708391 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=LN1IDVM5; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NHQH6717Wz23lT for ; Thu, 24 Nov 2022 02:37:21 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 705C6851F5; Wed, 23 Nov 2022 16:37:13 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LN1IDVM5"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0B5AB85537; Wed, 23 Nov 2022 16:37:12 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.9 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, SPF_HELO_NONE,SPF_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 27256851EE for ; Wed, 23 Nov 2022 16:37:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669217829; x=1700753829; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=twErDi6SQrkTc0wYwsrRNujjrZD0Fxaa63q9iHE2Ijw=; b=LN1IDVM5h462WL+9DkCeeg6lWInnwKeX1DABI4guaFNyXyulPAuTJyb7 nTuOMjMcrdVheoipf1vEEGqSgt/lfPHUuPWca42ma/mg00zjeZQW7acWa EEzhwoajTaQi03zithM0M499YRNLOFbI+PggNb8LxeCOY/yLCDPHeFS6D NF4QjRF6EncE8ebvzTMiOPFUP9CVoGCa+xZCXWkGMnKXj1KSpZSH69BKU oX3iuBEAfrwk/kWN0/h4IpeOXyYIeRKX4xsjcV+9oH9Z7RMeA9Q9ajlk5 c1ow7RAuTyE5QRBbWQKko9rh0JGnamuGX0Xlzzk3ID0+jWSIQWguHpNOP Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="315912542" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="315912542" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 07:37:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="710625540" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="710625540" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga004.fm.intel.com with ESMTP; 23 Nov 2022 07:36:53 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 50C30482B; Wed, 23 Nov 2022 23:36:53 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 4E82EE0095B; Wed, 23 Nov 2022 23:36:53 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Yau Wai Gan Subject: [PATCH] drivers: fpga: Add FPGA configuration during bootm for Intel SOCFPGA Date: Wed, 23 Nov 2022 23:36:52 +0800 Message-Id: <20221123153652.12241-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Yau Wai Gan This enable the capability to automatically perform FPGA configuration when booting Linux FIT image via bootm command. The FPGA configuration bitstream shall be packed within the FIT image. Signed-off-by: Yau Wai Gan Signed-off-by: Jit Loon Lim --- drivers/fpga/altera.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 10c0475d25..35eb95544d 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -10,6 +10,10 @@ /* * Altera FPGA support */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include +#endif #include #include #include @@ -49,6 +53,43 @@ static const struct altera_fpga { #endif }; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +int fpga_is_partial_data(int devnum, size_t img_len) +{ + /* + * The FPGA data (full or partial) is checked by + * the SDM hardware, for Intel SDM Mailbox based + * devices. Hence always return full bitstream. + * + * For Cyclone V and Arria 10 family, the bitstream + * type paramater is not handled by the driver. + */ + return 0; +} + +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) +{ + int ret_val; + int flags = 0; + + ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype, flags); + + /* + * Enable the HPS to FPGA bridges when FPGA load is completed + * successfully. This is to ensure the FPGA is accessible + * by the HPS. + */ + if (!ret_val) { + printf("Enable FPGA bridges\n"); + do_bridge_reset(1, ~0); + } + + return ret_val; +} +#endif + static int altera_validate(Altera_desc *desc, const char *fn) { if (!desc) {