From patchwork Wed Nov 23 14:27:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1708337 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=HvJW/YBU; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NHNkJ4jv0z23lT for ; Thu, 24 Nov 2022 01:27:20 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 39D91806E8; Wed, 23 Nov 2022 15:27:16 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="HvJW/YBU"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6E5B7806E8; Wed, 23 Nov 2022 15:27:15 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.9 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, SPF_HELO_NONE,SPF_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A6D7D8039E for ; Wed, 23 Nov 2022 15:27:12 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669213633; x=1700749633; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=SWBGe8f5Z6h2301MP/rU+Tl4k/kLbJ8tp87FASwqNGc=; b=HvJW/YBUVqY18W80mXavOkIY+2xOs1azpqa0gB0FnmbALOYbH3Uk6zhM gT4jB8qmc+u8jeIR8IEmuESmCxVLVVmui6fawCVkN2ECGCn4EJVBPirZL 9veZEe9hRX06uGGIyUlmu+oSg0lfyFrF24zUijLD1HPIrfpjedsuBOgfw GjEkjARFKDkGodV6uDa7N/eIIICp4lBTk7hnVDL/zQJxwVsvfZjx2rhjQ A15UQbMk+HvZytLUA/QGFr1qXyVCAlRXh9RcpwmNghjrERB7KArHW/zu0 JdA20G4msbFRWLwiF0oqYDYNHgcm+7h14KTeNP1CuZiwhjQ9maTnRuOWi A==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="294464605" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="294464605" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 06:27:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="592532717" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="592532717" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga003.jf.intel.com with ESMTP; 23 Nov 2022 06:27:05 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 3BB412B28; Wed, 23 Nov 2022 22:27:05 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 35100E0095B; Wed, 23 Nov 2022 22:27:05 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH] ddr: altera: n5x: Checking DDR init hang before reset due to watchdog Date: Wed, 23 Nov 2022 22:27:04 +0800 Message-Id: <20221123142704.26987-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee DDR need to be initialized and running calibration if DDR init hang before reset due to watchdog. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 7d4225e471..5117a5c4cf 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -428,6 +428,17 @@ enum data_process { LOADING }; +bool is_ddr_init_hang(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK) + return true; + + return false; +} + bool is_ddr_dbe_triggered(void) { u32 reg = readl(socfpga_get_sysmgr_addr() + @@ -491,13 +502,13 @@ void reset_type_print(enum reset_type reset_t) } } -bool is_ddr_init_skipped(u32 reg) +bool is_ddr_init_skipped(u32 reg, bool is_ddr_hang_be4_rst) { enum reset_type reset_t = get_reset_type(reg); reset_type_print(reset_t); - if (!is_ddr_dbe_triggered()) { + if (!is_ddr_dbe_triggered() && !is_ddr_hang_be4_rst) { if (reset_t == WARM_RESET) { debug("%s: DDR init is skipped\n", __func__); return true; @@ -517,13 +528,13 @@ bool is_ddr_init_skipped(u32 reg) return false; } -bool is_ddr_calibration_skipped(u32 reg) +bool is_ddr_calibration_skipped(u32 reg, bool is_ddr_hang_be4_rst) { enum reset_type reset_t = get_reset_type(reg); if ((reset_t == NCONFIG || reset_t == JTAG_CONFIG || reset_t == RSU_RECONFIG) && is_ddr_retention_enabled(reg) && - !is_ddr_dbe_triggered()) { + !is_ddr_dbe_triggered() && !is_ddr_hang_be4_rst) { debug("%s: DDR retention bit is set\n", __func__); return true; } @@ -1579,7 +1590,8 @@ static bool is_cal_bak_data_valid(void) return true; } -static int init_phy(struct ddr_handoff *ddr_handoff_info) +static int init_phy(struct ddr_handoff *ddr_handoff_info, + bool *need_calibrate, bool is_ddr_hang_be4_rst) { u32 handoff_table[ddr_handoff_info->phy_handoff_length]; u32 i, value; @@ -1609,7 +1621,7 @@ static int init_phy(struct ddr_handoff *ddr_handoff_info) handoff_process(ddr_handoff_info, ddr_handoff_info->phy_handoff_base, ddr_handoff_info->phy_handoff_length, ddr_handoff_info->phy_base); - if (is_ddr_calibration_skipped(reg)) { + if (is_ddr_calibration_skipped(reg, is_ddr_hang_be4_rst)) { if (is_cal_bak_data_valid()) *need_calibrate = false; else @@ -2848,6 +2860,7 @@ int sdram_mmr_init_full(struct udevice *dev) u32 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); int ret; + bool is_ddr_hang_be4_rst = is_ddr_init_hang(); bool need_calibrate = true; ulong ddr_offset; char *endptr; @@ -2873,7 +2886,7 @@ int sdram_mmr_init_full(struct udevice *dev) */ writel(SOC64_CRAM_PHY_BACKUP_SKIP_MAGIC, SOC64_OCRAM_PHY_BACKUP_BASE); - if (!is_ddr_init_skipped(reg)) { + if (!is_ddr_init_skipped(reg, is_ddr_hang_be4_rst)) { printf("SDRAM init in progress ...\n"); ddr_init_inprogress(true); @@ -2915,7 +2928,8 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR controller configuration is completed\n"); /* Initialize DDR PHY */ - ret = init_phy(&ddr_handoff_info, &need_calibrate); + ret = init_phy(&ddr_handoff_info, &need_calibrate, + is_ddr_hang_be4_rst); if (ret) { debug("%s: Failed to inilialize DDR PHY\n", __func__); return ret;