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20221121104719epcas5p2f87febfba74a4ca6807b3095acf507d0~pk8uvGQtc1633716337epcas5p2u; Mon, 21 Nov 2022 10:47:19 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20221121104719epsmtrp11863a397d22de0bcf2b74a8827f3141e~pk8uuGUbI2438624386epsmtrp1S; Mon, 21 Nov 2022 10:47:19 +0000 (GMT) X-AuditID: b6c32a4b-5f7fe7000001dc20-01-637b63e2d78b Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 82.5B.14392.7375B736; Mon, 21 Nov 2022 19:47:19 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221121104716epsmtip1939538519be9bfffb3d07318ec139ca9~pk8rNwdSR1012210122epsmtip1_; Mon, 21 Nov 2022 10:47:16 +0000 (GMT) From: Shradha Todi To: bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, kishon@ti.com, vkoul@kernel.org, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, alim.akhtar@samsung.com, ajaykumar.rs@samsung.com, rcsekar@samsung.com, sriranjani.p@samsung.com, bharat.uppal@samsung.com, s.prashar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, p.rajanbabu@samsung.com, niyas.ahmed@samsung.com, chanho61.park@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Shradha Todi Subject: [PATCH 1/6] dt-bindings: phy: Add PCIe PHY bindings for FSD Date: Mon, 21 Nov 2022 16:22:05 +0530 Message-Id: <20221121105210.68596-2-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221121105210.68596-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VTe0xTVxjf6X30gqne8BgH5lhznVlgAemE7vDSRZl2c1nINEycE7v2piCl rb3Fx4gCii5rBHmqcaUjFsPADZUCltfKa1AQHI6OkGkQCFtgw+E6rJs8tkLL9t/vfN/v9/2+ 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X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the PCIe PHY device tree bindings for Tesla FSD SoC Signed-off-by: Shradha Todi --- .../bindings/phy/phy-tesla-pcie.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml b/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml new file mode 100644 index 000000000000..8fa9a050af7a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-tesla-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD SoC PCIe PHY + +maintainers: + - Shradha Todi + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - tesla,fsd-pcie-phy + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + minItems: 2 + maxItems: 2 + items: + enum: [phy, pcs] + description: | + phy is the register access to PMA layer + pcs is the register access to PCS layer + + phy-mode: + description: | + Defines the bifurcation mode of the PHY + + tesla,pmureg-phandle: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for PMU system controller interface used to + control PMU register bits for PCIe PHY + + tesla,pcie-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for system control registers, used to + control phy signals at system level + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - phy-mode + - tesla,pmureg-phandle + - tesla,pcie-sysreg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie_phy0: pcie-phy@15080000 { + compatible = "tesla,fsd-pcie-phy"; + #phy-cells = <0>; + reg = <0x0 0x15080000 0x0 0x2000>, <0x0 0x150A0000 0x0 0x1000>; + reg-names = "phy", "pcs"; + tesla,pmureg-phandle = <&pmu_system_controller>; + tesla,pcie-sysreg = <&sysreg_fsys0>; + phy-mode = <0>; + status = "disabled"; + }; + }; +... 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lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, alim.akhtar@samsung.com, ajaykumar.rs@samsung.com, rcsekar@samsung.com, sriranjani.p@samsung.com, bharat.uppal@samsung.com, s.prashar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, p.rajanbabu@samsung.com, niyas.ahmed@samsung.com, chanho61.park@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Shradha Todi Subject: [PATCH 2/6] dt-bindings: PCI: Add PCIe controller bindings for FSD Date: Mon, 21 Nov 2022 16:22:06 +0530 Message-Id: <20221121105210.68596-3-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221121105210.68596-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTa0yTVxjHd/q2bwtJ3cvF7dg5ZEU+UAZtoa2HCkic28qckQSybM6tNOVd i72mF0DRUEWMojCGbiDYgoImlItSLqsCk5Wbc2GSwBgBjGDYsoE6AhUXwW0tr2zffuc5/+f5 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RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the PCIe controller device tree bindings for Tesla FSD SoC for both RC and EP Signed-off-by: Shradha Todi --- .../bindings/pci/tesla,pcie-fsd-ep.yaml | 107 ++++++++++++++++ .../bindings/pci/tesla,pcie-fsd.yaml | 117 ++++++++++++++++++ 2 files changed, 224 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/tesla,pcie-fsd-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/tesla,pcie-fsd.yaml diff --git a/Documentation/devicetree/bindings/pci/tesla,pcie-fsd-ep.yaml b/Documentation/devicetree/bindings/pci/tesla,pcie-fsd-ep.yaml new file mode 100644 index 000000000000..07308cb9a35c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/tesla,pcie-fsd-ep.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/tesla,pcie-fsd-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare based PCIe EP controller on FSD SoCs + +maintainers: + - Shradha Todi + +description: | + FSD PCIe EP controller is based on Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml. The controller instance is dual mode and + can work in Root port mode or Endpoint mode at a time. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +properties: + compatible: + enum: + - tesla,fsd-pcie-ep + + reg: + items: + - description: controller's application logic registers + - description: controller's own configuration registers + are available. + - description: controller's own configuration shadow registers + are available. + - description: Map the remote Root Complex slave address space + + reg-names: + items: + - const: appl + - const: dbi + - const: dbi2 + - const: addr_space + + clocks: + items: + - description: Auxiliary clock for PCIe + - description: AHB clock for PCIe dbi + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + + clock-names: + items: + - const: aux_clk + - const: dbi_clk + - const: mstr_clk + - const: slv_clk + + interrupts: + items: + - description: Controller interrupt + + interrupt-names: + items: + - const: sub_ctrl_intr + + tesla,pcie-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: phandle for system control registers, used to + control signals at system level + +required: + + - compatible + - reg + - reg-names + - clocks + - clock-names + - ranges + - num-lanes + - tesla,pcie-sysreg + +additionalProperties: true + +examples: + - | + #include + #include + + pcie4_ep: pcie-ep@15400000 { + compatible = "tesla,fsd-pcie-ep"; + clocks = <&clock_fsys0 PCIE_SUBCTRL_INST0_AUX_CLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_DBI_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_SLV_ACLK_SOC>; + clock-names = "aux_clk", "dbi_clk", "mstr_clk", "slv_clk"; + interrupts = ; + interrupt-names = "sub_ctrl_intr"; + reg = <0x15090000 0x1000>, + <0x15400000 0x1000>, + <0x15401000 0x80>, + <0x15800000 0xFF0000>; + reg-names = "appl", "dbi", "dbi2", "addr_space"; + num-lanes = <4>; + tesla,pcie-sysreg = <&sysreg_fsys0 0x434>; + phys = <&pcie_phy0>; + phy-names = "pcie_phy0"; + status = "disabled"; + }; +... diff --git a/Documentation/devicetree/bindings/pci/tesla,pcie-fsd.yaml b/Documentation/devicetree/bindings/pci/tesla,pcie-fsd.yaml new file mode 100644 index 000000000000..85648e5c7d27 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/tesla,pcie-fsd.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/pci/tesla,pcie-fsd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare based PCIe controller on FSD SoCs + +maintainers: + - Shradha Todi + +description: | + FSD PCIe controller is based on Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in + designware-pcie.txt. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: tesla,fsd-pcie + + reg: + items: + - description: controller's application logic registers + - description: controller's own configuration registers + are available. + - description: configuration registers + + reg-names: + items: + - const: appl + - const: dbi + - const: config + + clocks: + items: + - description: Auxiliary clock for PCIe + - description: AHB clock for PCIe dbi + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + + clock-names: + items: + - const: aux_clk + - const: dbi_clk + - const: mstr_clk + - const: slv_clk + + interrupts: + minItems: 1 + items: + - description: MSI interrupt + - description: Controller interrupt + + interrupt-names: + minItems: 1 + items: + - const: msi + - const: sub_ctrl_intr + + tesla,pcie-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: phandle for system control registers, used to + control signals at system level + +required: + + - compatible + - reg + - reg-names + - clocks + - clock-names + - ranges + - num-lanes + - tesla,pcie-sysreg + +additionalProperties: true + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie4_rc: pcie@15400000 { + compatible = "tesla,fsd-pcie"; + clocks = <&clock_fsys0 PCIE_SUBCTRL_INST0_AUX_CLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_DBI_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_SLV_ACLK_SOC>; + clock-names = "aux_clk", "dbi_clk", "mstr_clk", "slv_clk"; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + interrupts = ; + interrupt-names = "msi"; + num-lanes = <4>; + reg = <0x0 0x15090000 0x0 0x1000>, + <0x0 0x15400000 0x0 0x1000>, + <0x0 0x15800000 0x0 0x1000>; + reg-names = "appl", "dbi", "config"; + ranges = <0x82000000 0 0x15801000 0 0x15801000 0 0xffefff>; + tesla,pcie-sysreg = <&sysreg_fsys0 0x434>; + phys = <&pcie_phy0>; + phy-names = "pcie_phy0"; + iommu-map = <0x0 &smmu_fsys0 0x4 0x10000>; + iommu-map-mask = <0x0>; + status = "disabled"; + }; + }; +...