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spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 2AG6Gdql046436; Wed, 16 Nov 2022 14:16:39 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 16 Nov 2022 14:16:38 +0800 Date: Wed, 16 Nov 2022 06:16:25 +0000 From: Leo Liang To: CC: , , Subject: [PULL] u-boot-riscv/master Message-ID: MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 2AG6Gdql046436 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Tom, The following changes since commit c4ee4fe92e9be120be6d12718273dec6b63cc7d9: Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-11-14 09:33:36 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 591e0f878083925e7afff82e1774ba295a7767aa: riscv: enable reset via SBI on PolarFire Icicle Kit (2022-11-15 15:37:17 +0800) CI shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14105 ---------------------------------------------------------------- - Fix and improve microchip's clock driver to allow sync'ing DTS with linux - Improve the help message in "SBI_V02" Kconfig - Improve DTS property "isa-string" parsing rule ---------------------------------------------------------------- Conor Dooley (6): dt-bindings: clk: add missing clk ids for microchip mpfs clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() clk: microchip: mpfs: fix reference clock handling clk: microchip: mpfs: fix periph clk parentage clk: microchip: mpfs: fix criticality of peripheral clocks riscv: dts: fix the mpfs's reference clock frequency Heinrich Schuchardt (2): riscv: clarify meaning of CONFIG_SBI_V02 riscv: enable reset via SBI on PolarFire Icicle Kit Yu Chien Peter Lin (1): riscv: Fix detecting FPU support in standard extension arch/riscv/Kconfig | 14 +++++++------- arch/riscv/cpu/cpu.c | 14 +++++++++++--- arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 ++++ arch/riscv/dts/microchip-mpfs.dtsi | 14 ++++++-------- configs/microchip_mpfs_icicle_defconfig | 2 ++ drivers/clk/microchip/Makefile | 2 +- drivers/clk/microchip/mpfs_clk.c | 37 +++++++++++++++++++++++++++---------- drivers/clk/microchip/mpfs_clk.h | 20 ++++++++++++-------- drivers/clk/microchip/mpfs_clk_cfg.c | 7 +++---- drivers/clk/microchip/mpfs_clk_msspll.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/microchip/mpfs_clk_periph.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------------------------ include/dt-bindings/clock/microchip-mpfs-clock.h | 3 +++ 12 files changed, 249 insertions(+), 83 deletions(-) create mode 100644 drivers/clk/microchip/mpfs_clk_msspll.c Best regards, Leo