From patchwork Thu Nov 10 14:34:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1702164 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Z/spyWCn; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N7PX56LgMz23mT for ; Fri, 11 Nov 2022 01:35:49 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ot8e8-0001Mi-CS; Thu, 10 Nov 2022 09:35:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ot8e3-0001LW-UP for qemu-devel@nongnu.org; Thu, 10 Nov 2022 09:35:10 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ot8e1-0003e6-1P for qemu-devel@nongnu.org; Thu, 10 Nov 2022 09:35:07 -0500 Received: by mail-wr1-x433.google.com with SMTP id bk15so2500619wrb.13 for ; Thu, 10 Nov 2022 06:35:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gh3FqphZHkPJ2RSd/jkhg3VQ5KjokR5mr4nkEYamX0w=; b=Z/spyWCnl/TlrU9BD10Mp+l6S8WFHMgWWOONx5xjVKdIko7xcLivDX3nV8tAw8TRYS vY0l2fyVT8UmLaVxXhVzlsIw3iGMJMLsWfxndm8vUgaUe0j03PJyJgfN6sywymYNsfE7 HFr/+JFqyopBhQJYVu/R/ZteAiHYr4wwpadTduei8AUuubgENI7p3pq5RxzGgIIP8gG1 O/KdpWfXDCjHuJJlTWiP2XyW82r37irhLQhMrKmY5aZr2cqmL4HzMFSfJIwysrUtbwgj 5eATWZyHtMnEpokOcrmC6YyP03+1yHrxNGKS5DvRjdoOCr9LbmhEVNZC5ZQ4D3/H1DCe vOlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gh3FqphZHkPJ2RSd/jkhg3VQ5KjokR5mr4nkEYamX0w=; b=Qtf2ttBDBYIH8UZkFJZ3dSX82C284X2KWqaOR7o5A5AbsqnZzhhhOTKL93/+3B4KJt +UWMx2ljLLR/EMcrlwQWZd16CIrnDmdCJyEuTXiUG1mUWUXPj3WX/jbsgfUqzdTaWCPX H5Ua854uBYGD7U4ACjpCRLZ1UHDyhN1hA+sEB6CxWYI1CLlA0LR88/8OozRpaQGUrCWD cTppJb/pnQTiUhPwvGFMgilmni3krkstg3oxLkmTv34Jl68kZiDJenhro50KCVGT/WHj VAfOp+M9tThtud6RWLJFwyMyK0RktUHsM6uFs0VZ9IFniCA+l95MRMtANRwwey46SZeQ 8P9Q== X-Gm-Message-State: ACrzQf2Pk9Z60dcOyU+qR0+9P0WH/magQOz8W6U9Wg3XArm3wisqucN6 KSxSN5RiLl7xZS6a7snpGt3p15DzqgHXVA== X-Google-Smtp-Source: AMsMyM6TT5MtiJ2qqCifJ37TYeaegkDj+8pFIlkKaWuclRAFkOKbARj8GsozpS7oIFZQ+N9ajPsxfA== X-Received: by 2002:a5d:50ca:0:b0:236:776c:3075 with SMTP id f10-20020a5d50ca000000b00236776c3075mr42127368wrt.656.1668090903565; Thu, 10 Nov 2022 06:35:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bq21-20020a5d5a15000000b00231ed902a4esm16666803wrb.5.2022.11.10.06.35.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 06:35:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland Subject: [PATCH for-8.0 1/2] hw/misc/mos6522: Convert TYPE_MOS6522 to 3-phase reset Date: Thu, 10 Nov 2022 14:34:58 +0000 Message-Id: <20221110143459.3833425-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221110143459.3833425-1-peter.maydell@linaro.org> References: <20221110143459.3833425-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Convert the TYPE_MOS6522 parent class to use 3-phase reset. This is a prerequisite for converting its subclasses. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/misc/mos6522.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index fe38c44426b..0ed631186c3 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -643,9 +643,9 @@ const VMStateDescription vmstate_mos6522 = { } }; -static void mos6522_reset(DeviceState *dev) +static void mos6522_reset_hold(Object *obj) { - MOS6522State *s = MOS6522(dev); + MOS6522State *s = MOS6522(obj); s->b = 0; s->a = 0; @@ -705,9 +705,10 @@ static Property mos6522_properties[] = { static void mos6522_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); - dc->reset = mos6522_reset; + rc->phases.hold = mos6522_reset_hold; dc->vmsd = &vmstate_mos6522; device_class_set_props(dc, mos6522_properties); mdc->portB_write = mos6522_portB_write; From patchwork Thu Nov 10 14:34:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1702166 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=lI78HYzz; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N7PXR6Nj7z23lW for ; Fri, 11 Nov 2022 01:36:07 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ot8eK-0001Pq-5W; Thu, 10 Nov 2022 09:35:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ot8eG-0001PV-Pm for qemu-devel@nongnu.org; Thu, 10 Nov 2022 09:35:20 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ot8e2-0003eh-VA for qemu-devel@nongnu.org; Thu, 10 Nov 2022 09:35:13 -0500 Received: by mail-wm1-x32d.google.com with SMTP id m7-20020a05600c090700b003cf8a105d9eso1260039wmp.5 for ; Thu, 10 Nov 2022 06:35:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8C8vvEsGnHci6G0b2uCW9lNCRb924RsDFkFCBVRQ1RY=; b=lI78HYzzzWEsW9dgC/GSFMnjSvdiXrOXceeqwoYy3zqGPXxqzGrL/bhePN16VBdoOx t2bvz5EPvIk8DH1acedXQE9bIXHKSIXERoZiQ58jBwv4IiJRVWLj953PQOuMP8x5h5VA sCRMbcCuCA6P68EmI/Pi1+9+tRGUtgEJy/9bq71Rd02+qQXfH4PPkufG9JPzIF6oRV1b nOwbMP2gmWUkd85ssK0Cf8g9N+NB+MXgbumjHLoTeEItzUxT4MpdsSNwBH6qNFySncya vBPNJUGDvCRYJ5ncfH6b4Tk1seZsOa0vXuj0KLQDmtql83ji3/R1NiZdiuKihr2WlKRK 8ppQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8C8vvEsGnHci6G0b2uCW9lNCRb924RsDFkFCBVRQ1RY=; b=Y5VGzHHkgMDpBVWs3r1mQMCb+ZxzZZKdbM8Iz1sDN0euDDkCPcKWPidtawv97297Ze K/HizH346qdQgUf8+UGMQo+xDwbj9zzlKb1EyWcnbG60Y0s9jywqF/nzUTiPLQg29DtQ 6ZGNHbP6g743MdWpJ4MJMmWFmpWyRuDodMER1tl7aBc+niOwxC2A5wZ4r04/sp1rYrg7 1KChEbXS74Hu5moYjeQ7cMoFIl4ghw6m7LLe6wDp/iwImmRciGZ6WQW+ay/zpc31te2d xV8Rj3+DzipHcK8RVVdst2ANjblJ1nEUH6/yS4Qwdx3lr37ZFWQqckI8bfoV1OIPZw8L FWxw== X-Gm-Message-State: ANoB5pmQfil4zw8EMjhTHnbNXgEd3Z3eHBQSV/1Qyg5S/y7thhNI/JWU IvIOGTWxHKTCQfHf2rbztsPGjL5dGOokxA== X-Google-Smtp-Source: AA0mqf6aDCBC76EsLIGd7okDwFKmeK+P/nJi9431/upEUeNqXJkmDUwudS69URQqF8pR+jHogGM33w== X-Received: by 2002:a7b:c301:0:b0:3cf:a85d:2ab2 with SMTP id k1-20020a7bc301000000b003cfa85d2ab2mr624253wmj.43.1668090905027; Thu, 10 Nov 2022 06:35:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bq21-20020a5d5a15000000b00231ed902a4esm16666803wrb.5.2022.11.10.06.35.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 06:35:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland Subject: [PATCH for-8.0 2/2] hw/misc: Convert TYPE_MOS6522 subclasses to 3-phase reset Date: Thu, 10 Nov 2022 14:34:59 +0000 Message-Id: <20221110143459.3833425-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221110143459.3833425-1-peter.maydell@linaro.org> References: <20221110143459.3833425-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Convert the various subclasses of TYPE_MOS6522 to 3-phase reset. This removes some uses of device_class_set_parent_reset(), which we would eventually like to be able to get rid of. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/hw/misc/mos6522.h | 2 +- hw/misc/mac_via.c | 26 ++++++++++++++++---------- hw/misc/macio/cuda.c | 14 ++++++++------ hw/misc/macio/pmu.c | 14 ++++++++------ 4 files changed, 33 insertions(+), 23 deletions(-) diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index 0bc22a83957..05872fffc92 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -157,7 +157,7 @@ OBJECT_DECLARE_TYPE(MOS6522State, MOS6522DeviceClass, MOS6522) struct MOS6522DeviceClass { DeviceClass parent_class; - DeviceReset parent_reset; + ResettablePhases parent_phases; void (*portB_write)(MOS6522State *dev); void (*portA_write)(MOS6522State *dev); /* These are used to influence the CUDA MacOS timebase calibration */ diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index f42c12755a9..076d18e5fd9 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -975,14 +975,16 @@ static int via1_post_load(void *opaque, int version_id) } /* VIA 1 */ -static void mos6522_q800_via1_reset(DeviceState *dev) +static void mos6522_q800_via1_reset_hold(Object *obj) { - MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(dev); + MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj); MOS6522State *ms = MOS6522(v1s); MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); ADBBusState *adb_bus = &v1s->adb_bus; - mdc->parent_reset(dev); + if (mdc->parent_phases.hold) { + mdc->parent_phases.hold(obj); + } ms->timers[0].frequency = VIA_TIMER_FREQ; ms->timers[1].frequency = VIA_TIMER_FREQ; @@ -1097,11 +1099,12 @@ static Property mos6522_q800_via1_properties[] = { static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); dc->realize = mos6522_q800_via1_realize; - device_class_set_parent_reset(dc, mos6522_q800_via1_reset, - &mdc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, mos6522_q800_via1_reset_hold, + NULL, &mdc->parent_phases); dc->vmsd = &vmstate_q800_via1; device_class_set_props(dc, mos6522_q800_via1_properties); } @@ -1123,12 +1126,14 @@ static void mos6522_q800_via2_portB_write(MOS6522State *s) } } -static void mos6522_q800_via2_reset(DeviceState *dev) +static void mos6522_q800_via2_reset_hold(Object *obj) { - MOS6522State *ms = MOS6522(dev); + MOS6522State *ms = MOS6522(obj); MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); - mdc->parent_reset(dev); + if (mdc->parent_phases.hold) { + mdc->parent_phases.hold(obj); + } ms->timers[0].frequency = VIA_TIMER_FREQ; ms->timers[1].frequency = VIA_TIMER_FREQ; @@ -1183,10 +1188,11 @@ static const VMStateDescription vmstate_q800_via2 = { static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); - device_class_set_parent_reset(dc, mos6522_q800_via2_reset, - &mdc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, mos6522_q800_via2_reset_hold, + NULL, &mdc->parent_phases); dc->vmsd = &vmstate_q800_via2; mdc->portB_write = mos6522_q800_via2_portB_write; } diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 0d4c13319a8..853e88bfedd 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -589,12 +589,14 @@ static void mos6522_cuda_portB_write(MOS6522State *s) cuda_update(cs); } -static void mos6522_cuda_reset(DeviceState *dev) +static void mos6522_cuda_reset_hold(Object *obj) { - MOS6522State *ms = MOS6522(dev); + MOS6522State *ms = MOS6522(obj); MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); - mdc->parent_reset(dev); + if (mdc->parent_phases.hold) { + mdc->parent_phases.hold(obj); + } ms->timers[0].frequency = CUDA_TIMER_FREQ; ms->timers[1].frequency = (SCALE_US * 6000) / 4700; @@ -602,11 +604,11 @@ static void mos6522_cuda_reset(DeviceState *dev) static void mos6522_cuda_class_init(ObjectClass *oc, void *data) { - DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); - device_class_set_parent_reset(dc, mos6522_cuda_reset, - &mdc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, mos6522_cuda_reset_hold, + NULL, &mdc->parent_phases); mdc->portB_write = mos6522_cuda_portB_write; mdc->get_timer1_counter_value = cuda_get_counter_value; mdc->get_timer2_counter_value = cuda_get_counter_value; diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index 70562ed8d07..97ef8c771b6 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -797,14 +797,16 @@ static void mos6522_pmu_portB_write(MOS6522State *s) pmu_update(ps); } -static void mos6522_pmu_reset(DeviceState *dev) +static void mos6522_pmu_reset_hold(Object *obj) { - MOS6522State *ms = MOS6522(dev); + MOS6522State *ms = MOS6522(obj); MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj); PMUState *s = container_of(mps, PMUState, mos6522_pmu); MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); - mdc->parent_reset(dev); + if (mdc->parent_phases.hold) { + mdc->parent_phases.hold(obj); + } ms->timers[0].frequency = VIA_TIMER_FREQ; ms->timers[1].frequency = (SCALE_US * 6000) / 4700; @@ -814,11 +816,11 @@ static void mos6522_pmu_reset(DeviceState *dev) static void mos6522_pmu_class_init(ObjectClass *oc, void *data) { - DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); - device_class_set_parent_reset(dc, mos6522_pmu_reset, - &mdc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, mos6522_pmu_reset_hold, + NULL, &mdc->parent_phases); mdc->portB_write = mos6522_pmu_portB_write; }