From patchwork Sun Nov 6 22:25:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1700335 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=y56ortIL; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4N588K2Sbzz23mB for ; Mon, 7 Nov 2022 09:25:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230112AbiKFWZt (ORCPT ); Sun, 6 Nov 2022 17:25:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230137AbiKFWZr (ORCPT ); Sun, 6 Nov 2022 17:25:47 -0500 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D4A4FAE6 for ; Sun, 6 Nov 2022 14:25:45 -0800 (PST) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 7609184576; Sun, 6 Nov 2022 23:25:42 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1667773543; bh=Qf7Wpy7mcQmFNB1qxVFd1OuH0ex9tOqpQ8RTnF6DU1Q=; h=From:To:Cc:Subject:Date:From; b=y56ortILIhoVhdvsJ37YM00tXjnoLcp0tijpT9NkbtwU/Izj8K74FO+7msGoDzR8t 5aECHyyZOv+GIg0Xgph2sYGYjADFxTAEoHNJ+bSX2ZzeGhrR2O44lmuzrjmA4cvX/n rrqQzJafaooEw6HURb3eYOw2JKCr4rSIhtC4SoMa8nEhSjAd4xS4Yva+ZWVoSzJIKg EgdKm2Y9g03nDnpKrDYnww7NTLDnvxWQ+cgSoZX9B0rXSCMJF5bW3RaEwJZQwDjlLc Q4NDBObvLu2nNRCtDPsMaI9/DIZi+0AMSUgCMD6YhRgvC5HornkEtBBHR+ng64tnEP ZmaDLAoH3sKwQ== From: Marek Vasut To: devicetree@vger.kernel.org Cc: Marek Vasut , Alexander Stein , Fabio Estevam , Krzysztof Kozlowski , Lucas Stach , Richard Zhu , Rob Herring , Shawn Guo , linux-arm-kernel@lists.infradead.org, NXP Linux Team Subject: [PATCH v4 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations Date: Sun, 6 Nov 2022 23:25:22 +0100 Message-Id: <20221106222524.223188-1-marex@denx.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The i.MX SoCs have various clock configurations routed into the PCIe IP, the list of clock is below. Document all those configurations in the DT binding document. All SoCs: pcie, pcie_bus 6QDL, 7D: + pcie_phy 6SX: + pcie_phy pcie_inbound_axi 8MQ: + pcie_phy pcie_aux 8MM, 8MP: + pcie_aux Acked-by: Alexander Stein Signed-off-by: Marek Vasut --- Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Lucas Stach Cc: Richard Zhu Cc: Rob Herring Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team To: devicetree@vger.kernel.org --- V2: - Add AB from Alex V3: - Duplicate clock-names maxItems to mx6sx and mx8mq compatibles - Flatten the if-else structure - The validation no longer works and introduces errors like these: arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: clock-names:2: 'pcie_phy' was expected V4: - Reinstate minItems: for clock-names in main section, turn the last two clock-names items into enums to cover all IP variants. - Add another allOf entry for mx6q/mx6qp/mx7d clock-names list. - Adjust clock maxItems in the allOf section. --- .../bindings/pci/fsl,imx6q-pcie.yaml | 73 +++++++++++++++++-- 1 file changed, 68 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 376e739bcad40..2df73be0ffbea 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -14,9 +14,6 @@ description: |+ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. -allOf: - - $ref: /schemas/pci/snps,dw-pcie.yaml# - properties: compatible: enum: @@ -60,8 +57,8 @@ properties: items: - const: pcie - const: pcie_bus - - const: pcie_phy - - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie + - enum: [ pcie_phy, pcie_aux ] + - enum: [ pcie_aux, pcie_inbound_axi ] num-lanes: const: 1 @@ -177,6 +174,72 @@ required: unevaluatedProperties: false +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_phy + + - if: + properties: + compatible: + contains: + const: fsl,imx6sx-pcie + then: + properties: + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_phy + - const: pcie_inbound_axi + + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-pcie + then: + properties: + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_phy + - const: pcie_aux + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_aux + examples: - | #include From patchwork Sun Nov 6 22:25:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1700336 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=xeaikqVU; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4N588K5s1Xz23mD for ; Mon, 7 Nov 2022 09:25:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230137AbiKFWZu (ORCPT ); Sun, 6 Nov 2022 17:25:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230143AbiKFWZr (ORCPT ); Sun, 6 Nov 2022 17:25:47 -0500 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 587F5FADD for ; Sun, 6 Nov 2022 14:25:45 -0800 (PST) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 1638084C36; Sun, 6 Nov 2022 23:25:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1667773543; bh=1xgyqXWQfpkqHvlL9c01hLqNXSCsKsA2h41m/I00J9g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xeaikqVUWixnDXwHPXARc0bQwkc+d3i49xMGhlLJZcwYypIsizp1RYMkLJXWYbRhe Gxxeb9ntg3X2y9OY6Vpi2RuReYlrhdH+LoRIbsN1qVU5ojbG9vqy582DyWyaXqar7p xZvFiHHyCcFVyce66+4cF3lWXKoqCWriNfE9wvmtkkqPALdPieePYXltFx9dIacUnT Ehl9RlR2hmXn+Jna2hxxfizwi2jIna1R901mPkV3oUU4F1+v2M8a8rvHfpicOFAYDC 6yLXVoic4dmMjy0/2NpO+Ma3/jqPLDzFq1/rK8RCZv+dDoZremHlrtliJR26w5WK51 WinsvNRn0QtiA== From: Marek Vasut To: devicetree@vger.kernel.org Cc: Marek Vasut , Fabio Estevam , Krzysztof Kozlowski , Lucas Stach , Richard Zhu , Rob Herring , Shawn Guo , linux-arm-kernel@lists.infradead.org, NXP Linux Team Subject: [PATCH v4 2/3] dt-bindings: imx6q-pcie: Handle various PD configurations Date: Sun, 6 Nov 2022 23:25:23 +0100 Message-Id: <20221106222524.223188-2-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221106222524.223188-1-marex@denx.de> References: <20221106222524.223188-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The i.MX SoCs have various power domain configurations routed into the PCIe IP. MX6SX is the only one which contains 2 domains and also uses power-domain-names. MX6QDL do not use any domains. All the rest uses one domain and does not use power-domain-names anymore. Document all those configurations in the DT binding document. Signed-off-by: Marek Vasut Reviewed-by: Krzysztof Kozlowski --- Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Lucas Stach Cc: Richard Zhu Cc: Rob Herring Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team To: devicetree@vger.kernel.org --- V2: - Keep the power-domains description in the main section V3: - Move power-domains back where they were originally (fixes V2) - Do not use else: in allOf section V4: - Special-case MX6Q and MX6QP in allOf section since they dont use PDs - Drop minItems: from power-domains main section - Handle anything which is not MX6SX,MX6Q,MX6QP as having one PD --- .../bindings/pci/fsl,imx6q-pcie.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 2df73be0ffbea..b14c12a47cc1c 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -69,6 +69,7 @@ properties: required properties for imx7d-pcie and imx8mq-pcie. power-domains: + minItems: 1 items: - description: The phandle pointing to the DISPLAY domain for imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and @@ -77,6 +78,7 @@ properties: for imx6sx-pcie. power-domain-names: + minItems: 1 items: - const: pcie - const: pcie_phy @@ -240,6 +242,47 @@ allOf: - const: pcie_bus - const: pcie_aux + - if: + properties: + compatible: + contains: + const: fsl,imx6sx-pcie + then: + properties: + power-domains: + minItems: 2 + maxItems: 2 + power-domain-names: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + then: + properties: + power-domains: false + power-domain-names: false + + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,imx6sx-pcie + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + then: + properties: + power-domains: + maxItems: 1 + power-domain-names: false + examples: - | #include From patchwork Sun Nov 6 22:25:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1700334 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=IhlEl/LS; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4N588H5szxz23lb for ; Mon, 7 Nov 2022 09:25:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229452AbiKFWZs (ORCPT ); Sun, 6 Nov 2022 17:25:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230112AbiKFWZr (ORCPT ); Sun, 6 Nov 2022 17:25:47 -0500 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57BC2FACB for ; Sun, 6 Nov 2022 14:25:45 -0800 (PST) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 6F0DC84CB2; Sun, 6 Nov 2022 23:25:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1667773543; bh=6HMYLNzS6hiuEbEeV/hiMaMt4431AzHnBB/XVh36REo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IhlEl/LS0KePNJVhCjuzGmvKAj6Rq8frOT0ub0KA4Fxo5TMp+cLbgxpbf1rhDsjOX BAw8Lg+qRWBRe4VmfHHOqI2vpi4MXEPeCvHH1GmIx2FsF6Qtdxf9kwpnK9s3uoCJCu hYk9/eB6IA+6EtsxlsosKi/P4SDejeup4xdijVjNlTx7YUORHJeMmJ5FkNLd9qTloN UaeIM69Z9CEW/ZXdShWWXxJn9gikJtQb6GhAei9I6pKL57reAkKbgINAIi5HwQ9lNN oqEn2URL58+bVUJZHuc/4e3KJlRaxmJa4HzdwQ/ZBjfHru5JId7WLrR0GvJSjGv7O/ QeDqUXnQKzjiQ== From: Marek Vasut To: devicetree@vger.kernel.org Cc: Marek Vasut , Fabio Estevam , Krzysztof Kozlowski , Lucas Stach , Richard Zhu , Rob Herring , Shawn Guo , linux-arm-kernel@lists.infradead.org, NXP Linux Team Subject: [PATCH v4 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms Date: Sun, 6 Nov 2022 23:25:24 +0100 Message-Id: <20221106222524.223188-3-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221106222524.223188-1-marex@denx.de> References: <20221106222524.223188-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The i.MX6 and i.MX7D does not use block controller to toggle PCIe reset, hence the PCIe DT description contains three reset entries on these older SoCs. Add this exception into the binding document. Signed-off-by: Marek Vasut --- Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Lucas Stach Cc: Richard Zhu Cc: Rob Herring Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team To: devicetree@vger.kernel.org --- V2: - Add mx8mq to 3-reset PCIe core variant - Handle the resets in allOf section V3: - Reinstate reset: maxItems:3 and add minItems:2 - Move reset-names back to main section - The validation no longer works and introduces errors like these: arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: reset-names:0: 'pciephy' was expected V4: - Reinstate reset minItems and maxItems - Turn the first two reset-names items into enums to cover all the various name combinations, sort the rest in allOf section --- .../bindings/pci/fsl,imx6q-pcie.yaml | 34 +++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index b14c12a47cc1c..46fc29384ed34 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -84,14 +84,16 @@ properties: - const: pcie_phy resets: + minItems: 2 maxItems: 3 description: Phandles to PCIe-related reset lines exposed by SRC IP block. Additional required by imx7d-pcie and imx8mq-pcie. reset-names: + minItems: 2 items: - - const: pciephy - - const: apps + - enum: [ pciephy, apps ] + - enum: [ apps, turnoff ] - const: turnoff fsl,tx-deemph-gen1: @@ -283,6 +285,34 @@ allOf: maxItems: 1 power-domain-names: false + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mq-pcie + then: + properties: + resets: + minItems: 3 + reset-names: + items: + - const: pciephy + - const: apps + - const: turnoff + else: + properties: + resets: + maxItems: 2 + reset-names: + items: + - const: apps + - const: turnoff + examples: - | #include