From patchwork Wed Mar 7 21:51:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882811 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="tWqJnRtg"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSBq6fLjz9s1p for ; Thu, 8 Mar 2018 08:56:03 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4F91AC22036; Wed, 7 Mar 2018 21:55:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 100FCC21E79; Wed, 7 Mar 2018 21:55:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 98D5CC21E79; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 36A90C21C4A for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id E611E6256D; Wed, 7 Mar 2018 22:55:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=qlDMTLSdjUQtzoBn5P4SkyPAkFWDf/E1SpSPrMbFbrA=; h=From:To:Date; b=tWqJnRtgygvuXvi7FVROh+oDbdBUjP03FlWUgwmWhsSThTocLaESykhBOghszH9tG NzWpvMp36qvB0naJiFgc0tS00eRAvaboLVpXTD5K4ZEjkFrJV2w0ytVGxgSExHzJ2c dw5rBtgxX8JfGxfLQIqB9uog9VjcNvj6Zm2+l2CU= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:51:58 +0100 Message-Id: <20180307215216.10418-2-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 01/19] phy: marvell: a3700: Change return type of macro MVEBU_REG X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" All the calls to reg_set and friends have to cast the first argument to void __iomem *. Lets change the return type of the MVEBU_REG macro instead. Signed-off-by: Marek Behun --- drivers/phy/marvell/comphy_a3700.c | 205 ++++++++++++++++--------------------- drivers/phy/marvell/comphy_a3700.h | 8 +- 2 files changed, 95 insertions(+), 118 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 5afd23c052..8285b8b107 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -141,78 +141,72 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) /* * 1. Enable max PLL. */ - reg_set16((void __iomem *)LANE_CFG1_ADDR(PCIE), - bf_use_max_pll_rate, 0); + reg_set16(LANE_CFG1_ADDR(PCIE), bf_use_max_pll_rate, 0); /* * 2. Select 20 bit SERDES interface. */ - reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(PCIE), - bf_cfg_sel_20b, 0); + reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE), bf_cfg_sel_20b, 0); /* * 3. Force to use reg setting for PCIe mode */ - reg_set16((void __iomem *)MISC_REG1_ADDR(PCIE), - bf_sel_bits_pcie_force, 0); + reg_set16(MISC_REG1_ADDR(PCIE), bf_sel_bits_pcie_force, 0); /* * 4. Change RX wait */ - reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF); + reg_set16(PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF); /* * 5. Enable idle sync */ - reg_set16((void __iomem *)UNIT_CTRL_ADDR(PCIE), - 0x60 | rb_idle_sync_en, 0xFFFF); + reg_set16(UNIT_CTRL_ADDR(PCIE), 0x60 | rb_idle_sync_en, 0xFFFF); /* * 6. Enable the output of 100M/125M/500M clock */ - reg_set16((void __iomem *)MISC_REG0_ADDR(PCIE), + reg_set16(MISC_REG0_ADDR(PCIE), 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); /* * 7. Enable TX */ - reg_set((void __iomem *)PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); + reg_set(PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); /* * 8. Check crystal jumper setting and program the Power and PLL * Control accordingly */ if (get_ref_clk() == 40) { - reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE), + reg_set16(PWR_PLL_CTRL_ADDR(PCIE), 0xFC63, 0xFFFF); /* 40 MHz */ } else { - reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE), + reg_set16(PWR_PLL_CTRL_ADDR(PCIE), 0xFC62, 0xFFFF); /* 25 MHz */ } /* * 9. Override Speed_PLL value and use MAC PLL */ - reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(PCIE), - 0x0040 | rb_use_max_pll_rate, 0xFFFF); + reg_set16(KVCO_CAL_CTRL_ADDR(PCIE), 0x0040 | rb_use_max_pll_rate, + 0xFFFF); /* * 10. Check the Polarity invert bit */ if (invert & PHY_POLARITY_TXD_INVERT) { - reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE), - phy_txd_inv, 0); + reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_txd_inv, 0); } if (invert & PHY_POLARITY_RXD_INVERT) { - reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE), - phy_rxd_inv, 0); + reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_rxd_inv, 0); } /* * 11. Release SW reset */ - reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(PCIE), + reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE), rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32, bf_soft_rst | bf_mode_refdiv); @@ -220,11 +214,11 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) udelay(PLL_SET_DELAY_US); /* Assert PCLK enabled */ - ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(PCIE), /* address */ - rb_txdclk_pclk_en, /* value */ - rb_txdclk_pclk_en, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ - POLL_16B_REG); /* 16bit */ + ret = comphy_poll_reg(LANE_STAT1_ADDR(PCIE), /* address */ + rb_txdclk_pclk_en, /* value */ + rb_txdclk_pclk_en, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_16B_REG); /* 16bit */ if (ret == 0) printf("Failed to lock PCIe PLL\n"); @@ -248,57 +242,53 @@ static int comphy_sata_power_up(void) /* * 0. Swap SATA TX lines */ - reg_set((void __iomem *)rh_vsreg_addr, - vphy_sync_pattern_reg, 0xFFFFFFFF); - reg_set((void __iomem *)rh_vsreg_data, bs_txd_inv, bs_txd_inv); + reg_set(rh_vsreg_addr, vphy_sync_pattern_reg, 0xFFFFFFFF); + reg_set(rh_vsreg_data, bs_txd_inv, bs_txd_inv); /* * 1. Select 40-bit data width width */ - reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); - reg_set((void __iomem *)rh_vsreg_data, 0x800, bs_phyintf_40bit); + reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); + reg_set(rh_vsreg_data, 0x800, bs_phyintf_40bit); /* * 2. Select reference clock and PHY mode (SATA) */ - reg_set((void __iomem *)rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF); + reg_set(rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF); if (get_ref_clk() == 40) { - reg_set((void __iomem *)rh_vsreg_data, - 0x3, 0x00FF); /* 40 MHz */ + reg_set(rh_vsreg_data, 0x3, 0x00FF); /* 40 MHz */ } else { - reg_set((void __iomem *)rh_vsreg_data, - 0x1, 0x00FF); /* 25 MHz */ + reg_set(rh_vsreg_data, 0x1, 0x00FF); /* 25 MHz */ } /* * 3. Use maximum PLL rate (no power save) */ - reg_set((void __iomem *)rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF); - reg_set((void __iomem *)rh_vsreg_data, - bs_max_pll_rate, bs_max_pll_rate); + reg_set(rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF); + reg_set(rh_vsreg_data, bs_max_pll_rate, bs_max_pll_rate); /* * 4. Reset reserved bit (??) */ - reg_set((void __iomem *)rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF); - reg_set((void __iomem *)rh_vsreg_data, 0, bs_phyctrl_frm_pin); + reg_set(rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF); + reg_set(rh_vsreg_data, 0, bs_phyctrl_frm_pin); /* * 5. Set vendor-specific configuration (??) */ - reg_set((void __iomem *)rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); - reg_set((void __iomem *)rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); + reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); + reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); /* Wait for > 55 us to allow PLL be enabled */ udelay(PLL_SET_DELAY_US); /* Assert SATA PLL enabled */ - reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); - ret = comphy_poll_reg((void *)rh_vsreg_data, /* address */ - bs_pll_ready_tx, /* value */ - bs_pll_ready_tx, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ - POLL_32B_REG); /* 32bit */ + reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); + ret = comphy_poll_reg(rh_vsreg_data, /* address */ + bs_pll_ready_tx, /* value */ + bs_pll_ready_tx, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_32B_REG); /* 32bit */ if (ret == 0) printf("Failed to lock SATA PLL\n"); @@ -321,19 +311,18 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) /* * 1. Power up OTG module */ - reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); + reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); /* * 2. Set counter for 100us pulse in USB3 Host and Device * restore default burst size limit (Reference Clock 31:24) */ - reg_set((void __iomem *)USB3_CTRPUL_VAL_REG, - 0x8 << 24, rb_usb3_ctr_100ns); + reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns); /* 0xd005c300 = 0x1001 */ /* set PRD_TXDEEMPH (3.5db de-emph) */ - reg_set16((void __iomem *)LANE_CFG0_ADDR(USB3), 0x1, 0xFF); + reg_set16(LANE_CFG0_ADDR(USB3), 0x1, 0xFF); /* * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in @@ -341,91 +330,81 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) */ /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */ /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */ - reg_set16((void __iomem *)LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF); + reg_set16(LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF); /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ - reg_set16((void __iomem *)LANE_CFG4_ADDR(USB3), - bf_spread_spectrum_clock_en, 0x80); + reg_set16(LANE_CFG4_ADDR(USB3), bf_spread_spectrum_clock_en, 0x80); /* * set Override Margining Controls From the MAC: Use margining signals * from lane configuration */ - reg_set16((void __iomem *)TEST_MODE_CTRL_ADDR(USB3), - rb_mode_margin_override, 0xFFFF); + reg_set16(TEST_MODE_CTRL_ADDR(USB3), rb_mode_margin_override, 0xFFFF); /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ /* set Mode Clock Source = PCLK is generated from REFCLK */ - reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF); + reg_set16(GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF); /* set G2 Spread Spectrum Clock Amplitude at 4K */ - reg_set16((void __iomem *)GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp, - 0xF000); + reg_set16(GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp, 0xF000); /* * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register * Master Current Select */ - reg_set16((void __iomem *)GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF); + reg_set16(GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF); /* * 3. Check crystal jumper setting and program the Power and PLL * Control accordingly */ if (get_ref_clk() == 40) { - reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA3, - 0xFFFF); /* 40 MHz */ + reg_set16(PWR_PLL_CTRL_ADDR(USB3), 0xFCA3, 0xFFFF); /* 40 MHz */ } else { - reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA2, - 0xFFFF); /* 25 MHz */ + reg_set16(PWR_PLL_CTRL_ADDR(USB3), 0xFCA2, 0xFFFF); /* 25 MHz */ } /* * 4. Change RX wait */ - reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF); + reg_set16(PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF); /* * 5. Enable idle sync */ - reg_set16((void __iomem *)UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en, - 0xFFFF); + reg_set16(UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en, 0xFFFF); /* * 6. Enable the output of 500M clock */ - reg_set16((void __iomem *)MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en, - 0xFFFF); + reg_set16(MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en, 0xFFFF); /* * 7. Set 20-bit data width */ - reg_set16((void __iomem *)DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF); + reg_set16(DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF); /* * 8. Override Speed_PLL value and use MAC PLL */ - reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(USB3), - 0x0040 | rb_use_max_pll_rate, 0xFFFF); + reg_set16(KVCO_CAL_CTRL_ADDR(USB3), 0x0040 | rb_use_max_pll_rate, 0xFFFF); /* * 9. Check the Polarity invert bit */ if (invert & PHY_POLARITY_TXD_INVERT) { - reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3), - phy_txd_inv, 0); + reg_set16(SYNC_PATTERN_ADDR(USB3), phy_txd_inv, 0); } if (invert & PHY_POLARITY_RXD_INVERT) { - reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3), - phy_rxd_inv, 0); + reg_set16(SYNC_PATTERN_ADDR(USB3), phy_rxd_inv, 0); } /* * 10. Release SW reset */ - reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(USB3), + reg_set16(GLOB_PHY_CTRL0_ADDR(USB3), rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20, 0xFFFF); @@ -433,11 +412,11 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) udelay(PLL_SET_DELAY_US); /* Assert PCLK enabled */ - ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(USB3), /* address */ - rb_txdclk_pclk_en, /* value */ - rb_txdclk_pclk_en, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ - POLL_16B_REG); /* 16bit */ + ret = comphy_poll_reg(LANE_STAT1_ADDR(USB3), /* address */ + rb_txdclk_pclk_en, /* value */ + rb_txdclk_pclk_en, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_16B_REG); /* 16bit */ if (ret == 0) printf("Failed to lock USB3 PLL\n"); @@ -455,7 +434,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) * INT_MODE=ID in order to avoid unexpected * behaviour or both interrupts together */ - reg_set((void __iomem *)USB32_CTRL_BASE, + reg_set(USB32_CTRL_BASE, usb32_ctrl_id_mode | usb32_ctrl_int_mode, usb32_ctrl_id_mode | usb32_ctrl_soft_id | usb32_ctrl_int_mode); @@ -489,32 +468,32 @@ static int comphy_usb2_power_up(u8 usb32) * See "PLL Settings for Typical REFCLK" table */ if (get_ref_clk() == 25) { - reg_set((void __iomem *)USB2_PHY_BASE(usb32), - 5 | (96 << 16), 0x3F | (0xFF << 16) | (0x3 << 28)); + reg_set(USB2_PHY_BASE(usb32), 5 | (96 << 16), + 0x3F | (0xFF << 16) | (0x3 << 28)); } /* * 1. PHY pull up and disable USB2 suspend */ - reg_set((void __iomem *)USB2_PHY_CTRL_ADDR(usb32), + reg_set(USB2_PHY_CTRL_ADDR(usb32), RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0); if (usb32 != 0) { /* * 2. Power up OTG module */ - reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); + reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); /* * 3. Configure PHY charger detection */ - reg_set((void __iomem *)USB2_PHY_CHRGR_DET_ADDR, 0, + reg_set(USB2_PHY_CHRGR_DET_ADDR, 0, rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto | rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc); } /* Assert PLL calibration done */ - ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32), + ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32), rb_usb2phy_pllcal_done, /* value */ rb_usb2phy_pllcal_done, /* mask */ PLL_LOCK_TIMEOUT, /* timeout */ @@ -523,7 +502,7 @@ static int comphy_usb2_power_up(u8 usb32) printf("Failed to end USB2 PLL calibration\n"); /* Assert impedance calibration done */ - ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32), + ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32), rb_usb2phy_impcal_done, /* value */ rb_usb2phy_impcal_done, /* mask */ PLL_LOCK_TIMEOUT, /* timeout */ @@ -532,7 +511,7 @@ static int comphy_usb2_power_up(u8 usb32) printf("Failed to end USB2 impedance calibration\n"); /* Assert squetch calibration done */ - ret = comphy_poll_reg((void *)USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32), + ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32), rb_usb2phy_sqcal_done, /* value */ rb_usb2phy_sqcal_done, /* mask */ PLL_LOCK_TIMEOUT, /* timeout */ @@ -541,7 +520,7 @@ static int comphy_usb2_power_up(u8 usb32) printf("Failed to end USB2 unknown calibration\n"); /* Assert PLL is ready */ - ret = comphy_poll_reg((void *)USB2_PHY_PLL_CTRL0_ADDR(usb32), + ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32), rb_usb2phy_pll_ready, /* value */ rb_usb2phy_pll_ready, /* mask */ PLL_LOCK_TIMEOUT, /* timeout */ @@ -567,35 +546,34 @@ static int comphy_emmc_power_up(void) /* * 1. Bus power ON, Bus voltage 1.8V */ - reg_set((void __iomem *)SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00); + reg_set(SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00); /* * 2. Set FIFO parameters */ - reg_set((void __iomem *)SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF); + reg_set(SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF); /* * 3. Set Capabilities 1_2 */ - reg_set((void __iomem *)SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF); + reg_set(SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF); /* * 4. Set Endian */ - reg_set((void __iomem *)SDIO_ENDIAN_ADDR, 0x00c00000, 0); + reg_set(SDIO_ENDIAN_ADDR, 0x00c00000, 0); /* * 4. Init PHY */ - reg_set((void __iomem *)SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000); - reg_set((void __iomem *)SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, - 0xF0000000); + reg_set(SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000); + reg_set(SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 0xF0000000); /* * 5. DLL reset */ - reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0); - reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0x00010000, 0); + reg_set(SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0); + reg_set(SDIO_DLL_RST_ADDR, 0x00010000, 0); debug_exit(); @@ -650,7 +628,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) /* * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 */ - reg_set((void __iomem *)COMPHY_SEL_ADDR, 0, rf_compy_select(lane)); + reg_set(COMPHY_SEL_ADDR, 0, rf_compy_select(lane)); /* * 2. Reset PHY by setting PHY input port PIN_RESET=1. @@ -658,7 +636,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * PHY TXP/TXN output to idle state during PHY initialization * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. */ - reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), + reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref, rb_pin_reset_core | rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx); @@ -666,21 +644,20 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) /* * 5. Release reset to the PHY by setting PIN_RESET=0. */ - reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), - 0, rb_pin_reset_comphy); + reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy); /* * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide * COMPHY bit rate */ if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ - reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), + reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x8 << rf_gen_rx_sel_shift) | (0x8 << rf_gen_tx_sel_shift), rf_gen_rx_select | rf_gen_tx_select); } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ - reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), + reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x6 << rf_gen_rx_sel_shift) | (0x6 << rf_gen_tx_sel_shift), rf_gen_rx_select | rf_gen_tx_select); @@ -785,7 +762,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * programming should be done before PIN_PU_PLL=1. There should be * no register programming for normal PHY operation from this point. */ - reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), + reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx, rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx); @@ -793,7 +770,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * 20. Wait for PHY power up sequence to finish by checking output ports * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. */ - ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */ + ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */ rb_pll_ready_tx | rb_pll_ready_rx, /* value */ rb_pll_ready_tx | rb_pll_ready_rx, /* mask */ PLL_LOCK_TIMEOUT, /* timeout */ @@ -804,8 +781,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) /* * 21. Set COMPHY input port PIN_TX_IDLE=0 */ - reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), - 0x0, rb_pin_tx_idle); + reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle); /* * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. @@ -815,10 +791,9 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * PIN_RX_INIT_DONE= 1. * Please refer to RX initialization part for details. */ - reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, - 0x0); + reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0); - ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */ + ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */ rb_rx_init_done, /* value */ rb_rx_init_done, /* mask */ PLL_LOCK_TIMEOUT, /* timeout */ diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index dd60b882dd..f993ad9c84 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -10,7 +10,8 @@ #include "comphy.h" #include "comphy_hpipe.h" -#define MVEBU_REG(offs) ((uintptr_t)MVEBU_REGISTER(offs)) +#define MVEBU_REG(offs) \ + ((void __iomem *) (ulong) MVEBU_REGISTER(offs)) #define DEFAULT_REFCLK_MHZ 25 #define PLL_SET_DELAY_US 600 @@ -61,11 +62,12 @@ #define USB3PHY_SHFT 2 #define SGMIIPHY_BASE(l) (l == 1 ? USB3PHY_BASE : PCIEPHY_BASE) -#define SGMIIPHY_ADDR(l, a) (((a & 0x00007FF) * 2) | SGMIIPHY_BASE(l)) +#define SGMIIPHY_ADDR(l, a) \ + ((void __iomem *) (((a & 0x00007FF) * 2) + SGMIIPHY_BASE(l))) #define phy_read16(l, a) read16((void __iomem *)SGMIIPHY_ADDR(l, a)) #define phy_write16(l, a, data, mask) \ - reg_set16((void __iomem *)SGMIIPHY_ADDR(l, a), data, mask) + reg_set16(SGMIIPHY_ADDR(l, a), data, mask) /* units */ #define PCIE 1 From patchwork Wed Mar 7 21:51:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882815 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="ZPy7EoTj"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSFV57rtz9sh0 for ; Thu, 8 Mar 2018 08:58:22 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 509CDC21E68; Wed, 7 Mar 2018 21:56:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BAA84C21F62; Wed, 7 Mar 2018 21:55:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E020EC21E62; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 4971DC21DB6 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 098C4625B4; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=DYKcRvJxFbxwKZAHL/aIyzs3B1B0uns+mXtmOG0uGxs=; h=From:To:Date; b=ZPy7EoTjxHNe65xRWS0ZMLAmnBuwL1WWj85933SHHwTQjP3rPtUNeDYlfiPNtodJW qLS2qadMQRFvGrks9uwAL8171uueS2ULKco8OIdoBwcBFiCcPGUDtQ2aYXF/F2m81k P4/fcuC+hyq3eNonBcLSfv/n5olkzmMDuPSDH4rY= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:51:59 +0100 Message-Id: <20180307215216.10418-3-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 02/19] phy: marvell: a3700: Use reg_set16 instead of phy_write16 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The macro phy_write16 is not used by the rest of the code, phy_read16 is not used at all. We also change the macro SGMIIPHY_ADDR to a static inline function. Signed-off-by: Marek Behun --- drivers/phy/marvell/comphy_a3700.c | 22 +++++++++++----------- drivers/phy/marvell/comphy_a3700.h | 15 ++++++++------- 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 8285b8b107..505e0933a3 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -610,7 +610,7 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) val = sgmii_phy_init[addr]; } - phy_write16(lane, addr, val, 0xFFFF); + reg_set16(SGMIIPHY_ADDR(lane, addr), val, 0xFFFF); } } @@ -673,26 +673,26 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) mdelay(10); /* 9. Program COMPHY register PHY_MODE */ - phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, - PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask); + reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR), + PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask); /* * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK * source */ - phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel); + reg_set16(SGMIIPHY_ADDR(lane, PHY_MISC_REG0_ADDR), 0, rb_ref_clk_sel); /* * 11. Set correct reference clock frequency in COMPHY register * REF_FREF_SEL. */ if (get_ref_clk() == 40) { - phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, - 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); + reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR), + 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); } else { /* 25MHz */ - phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, - 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); + reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR), + 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); } /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */ @@ -708,7 +708,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * bus width */ /* 10bit */ - phy_write16(lane, PHY_DIG_LB_EN_ADDR, 0, rf_data_width_mask); + reg_set16(SGMIIPHY_ADDR(lane, PHY_DIG_LB_EN_ADDR), 0, rf_data_width_mask); /* * 14. As long as DFE function needs to be enabled in any mode, @@ -751,10 +751,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * 18. Check the PHY Polarity invert bit */ if (invert & PHY_POLARITY_TXD_INVERT) - phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_txd_inv, 0); + reg_set16(SGMIIPHY_ADDR(lane, PHY_SYNC_PATTERN_ADDR), phy_txd_inv, 0); if (invert & PHY_POLARITY_RXD_INVERT) - phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_rxd_inv, 0); + reg_set16(SGMIIPHY_ADDR(lane, PHY_SYNC_PATTERN_ADDR), phy_rxd_inv, 0); /* * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index f993ad9c84..a315bf2647 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -61,13 +61,14 @@ #define USB32_CTRL_BASE MVEBU_REG(0x05D800) #define USB3PHY_SHFT 2 -#define SGMIIPHY_BASE(l) (l == 1 ? USB3PHY_BASE : PCIEPHY_BASE) -#define SGMIIPHY_ADDR(l, a) \ - ((void __iomem *) (((a & 0x00007FF) * 2) + SGMIIPHY_BASE(l))) - -#define phy_read16(l, a) read16((void __iomem *)SGMIIPHY_ADDR(l, a)) -#define phy_write16(l, a, data, mask) \ - reg_set16(SGMIIPHY_ADDR(l, a), data, mask) +static inline void __iomem *SGMIIPHY_ADDR(u32 lane, u32 addr) +{ + addr = (addr & 0x00007FF) * 2; + if (lane == 1) + return USB3PHY_BASE + addr; + else + return PCIEPHY_BASE + addr; +} /* units */ #define PCIE 1 From patchwork Wed Mar 7 21:52:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882831 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="IJvLF/su"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSQS4WVqz9s4Z for ; Thu, 8 Mar 2018 09:06:08 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 50B2BC21F58; Wed, 7 Mar 2018 21:58:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2D377C21FE4; Wed, 7 Mar 2018 21:55:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8931CC21BE5; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 60D10C21E52 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 121E962604; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=NZD8EpDyoda3eeOD7s6u3r32dHxRlg8S+mZ+W213jqw=; h=From:To:Date; b=IJvLF/su0ViV0vay2ZIA0ltXFZCdvXfGM1M74Ty0Kw/O5y3t0Svb/T+2L0d2uf4SH AC7wvX2uFDYgSAPjTfurpw+ezzR5l2acRHfLfd0izYudh1boMmWttQ4zKzDIC+RJgE CnnKjXBvFD7lgO86GtKI6lh7r3IA+mUIpBlc6LmE= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:00 +0100 Message-Id: <20180307215216.10418-4-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 03/19] phy: marvell: a3700: Don't create functional macro for each register X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently there is for each register special functional macro, ie: LANE_CFG1_ADDR(u) GLOB_CLK_SRC_LO_ADDR(u) ... where can be either PCIE or USB3. Change this to one function PHY_ADDR(unit, addr). The code becomes: PHY_ADDR(PCIE, LANE_CFG1) PHY_ADDR(PCIE, GLOB_CLK_SRC_LO) ... Signed-off-by: Marek Behun --- drivers/phy/marvell/comphy_a3700.c | 105 ++++++++++++++++++------------------- drivers/phy/marvell/comphy_a3700.h | 92 +++++++++++++------------------- 2 files changed, 89 insertions(+), 108 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 505e0933a3..6506c134e2 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -141,72 +141,70 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) /* * 1. Enable max PLL. */ - reg_set16(LANE_CFG1_ADDR(PCIE), bf_use_max_pll_rate, 0); + reg_set16(PHY_ADDR(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); /* * 2. Select 20 bit SERDES interface. */ - reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE), bf_cfg_sel_20b, 0); + reg_set16(PHY_ADDR(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); /* * 3. Force to use reg setting for PCIe mode */ - reg_set16(MISC_REG1_ADDR(PCIE), bf_sel_bits_pcie_force, 0); + reg_set16(PHY_ADDR(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0); /* * 4. Change RX wait */ - reg_set16(PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF); + reg_set16(PHY_ADDR(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); /* * 5. Enable idle sync */ - reg_set16(UNIT_CTRL_ADDR(PCIE), 0x60 | rb_idle_sync_en, 0xFFFF); + reg_set16(PHY_ADDR(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); /* * 6. Enable the output of 100M/125M/500M clock */ - reg_set16(MISC_REG0_ADDR(PCIE), + reg_set16(PHY_ADDR(PCIE, MISC_REG0), 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); /* * 7. Enable TX */ - reg_set(PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); + reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); /* * 8. Check crystal jumper setting and program the Power and PLL * Control accordingly */ if (get_ref_clk() == 40) { - reg_set16(PWR_PLL_CTRL_ADDR(PCIE), - 0xFC63, 0xFFFF); /* 40 MHz */ + /* 40 MHz */ + reg_set16(PHY_ADDR(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); } else { - reg_set16(PWR_PLL_CTRL_ADDR(PCIE), - 0xFC62, 0xFFFF); /* 25 MHz */ + /* 25 MHz */ + reg_set16(PHY_ADDR(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); } /* * 9. Override Speed_PLL value and use MAC PLL */ - reg_set16(KVCO_CAL_CTRL_ADDR(PCIE), 0x0040 | rb_use_max_pll_rate, + reg_set16(PHY_ADDR(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, 0xFFFF); /* * 10. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) { - reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_txd_inv, 0); - } + if (invert & PHY_POLARITY_TXD_INVERT) + reg_set16(PHY_ADDR(PCIE, SYNC_PATTERN), phy_txd_inv, 0); - if (invert & PHY_POLARITY_RXD_INVERT) { - reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_rxd_inv, 0); - } + if (invert & PHY_POLARITY_RXD_INVERT) + reg_set16(PHY_ADDR(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); /* * 11. Release SW reset */ - reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE), + reg_set16(PHY_ADDR(PCIE, GLOB_PHY_CTRL0), rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32, bf_soft_rst | bf_mode_refdiv); @@ -214,11 +212,11 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) udelay(PLL_SET_DELAY_US); /* Assert PCLK enabled */ - ret = comphy_poll_reg(LANE_STAT1_ADDR(PCIE), /* address */ - rb_txdclk_pclk_en, /* value */ - rb_txdclk_pclk_en, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ - POLL_16B_REG); /* 16bit */ + ret = comphy_poll_reg(PHY_ADDR(PCIE, LANE_STAT1), /* address */ + rb_txdclk_pclk_en, /* value */ + rb_txdclk_pclk_en, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_16B_REG); /* 16bit */ if (ret == 0) printf("Failed to lock PCIe PLL\n"); @@ -322,7 +320,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) /* 0xd005c300 = 0x1001 */ /* set PRD_TXDEEMPH (3.5db de-emph) */ - reg_set16(LANE_CFG0_ADDR(USB3), 0x1, 0xFF); + reg_set16(PHY_ADDR(USB3, LANE_CFG0), 0x1, 0xFF); /* * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in @@ -330,81 +328,82 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) */ /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */ /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */ - reg_set16(LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF); + reg_set16(PHY_ADDR(USB3, LANE_CFG1), 0x0, 0xFFFF); /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ - reg_set16(LANE_CFG4_ADDR(USB3), bf_spread_spectrum_clock_en, 0x80); + reg_set16(PHY_ADDR(USB3, LANE_CFG4), bf_spread_spectrum_clock_en, 0x80); /* * set Override Margining Controls From the MAC: Use margining signals * from lane configuration */ - reg_set16(TEST_MODE_CTRL_ADDR(USB3), rb_mode_margin_override, 0xFFFF); + reg_set16(PHY_ADDR(USB3, TEST_MODE_CTRL), rb_mode_margin_override, 0xFFFF); /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ /* set Mode Clock Source = PCLK is generated from REFCLK */ - reg_set16(GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF); + reg_set16(PHY_ADDR(USB3, GLOB_CLK_SRC_LO), 0x0, 0xFF); /* set G2 Spread Spectrum Clock Amplitude at 4K */ - reg_set16(GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp, 0xF000); + reg_set16(PHY_ADDR(USB3, GEN2_SETTINGS_2), g2_tx_ssc_amp, 0xF000); /* * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register * Master Current Select */ - reg_set16(GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF); + reg_set16(PHY_ADDR(USB3, GEN2_SETTINGS_3), 0x0, 0xFFFF); /* * 3. Check crystal jumper setting and program the Power and PLL * Control accordingly */ if (get_ref_clk() == 40) { - reg_set16(PWR_PLL_CTRL_ADDR(USB3), 0xFCA3, 0xFFFF); /* 40 MHz */ + /* 40 MHz */ + reg_set16(PHY_ADDR(USB3, PWR_PLL_CTRL), 0xFCA3, 0xFFFF); } else { - reg_set16(PWR_PLL_CTRL_ADDR(USB3), 0xFCA2, 0xFFFF); /* 25 MHz */ + /* 25 MHz */ + reg_set16(PHY_ADDR(USB3, PWR_PLL_CTRL), 0xFCA2, 0xFFFF); } /* * 4. Change RX wait */ - reg_set16(PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF); + reg_set16(PHY_ADDR(USB3, PWR_MGM_TIM1), 0x10C, 0xFFFF); /* * 5. Enable idle sync */ - reg_set16(UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en, 0xFFFF); + reg_set16(PHY_ADDR(USB3, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); /* * 6. Enable the output of 500M clock */ - reg_set16(MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en, 0xFFFF); + reg_set16(PHY_ADDR(USB3, MISC_REG0), 0xA00D | rb_clk500m_en, 0xFFFF); /* * 7. Set 20-bit data width */ - reg_set16(DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF); + reg_set16(PHY_ADDR(USB3, DIG_LB_EN), 0x0400, 0xFFFF); /* * 8. Override Speed_PLL value and use MAC PLL */ - reg_set16(KVCO_CAL_CTRL_ADDR(USB3), 0x0040 | rb_use_max_pll_rate, 0xFFFF); + reg_set16(PHY_ADDR(USB3, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, + 0xFFFF); /* * 9. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) { - reg_set16(SYNC_PATTERN_ADDR(USB3), phy_txd_inv, 0); - } + if (invert & PHY_POLARITY_TXD_INVERT) + reg_set16(PHY_ADDR(USB3, SYNC_PATTERN), phy_txd_inv, 0); - if (invert & PHY_POLARITY_RXD_INVERT) { - reg_set16(SYNC_PATTERN_ADDR(USB3), phy_rxd_inv, 0); - } + if (invert & PHY_POLARITY_RXD_INVERT) + reg_set16(PHY_ADDR(USB3, SYNC_PATTERN), phy_rxd_inv, 0); /* * 10. Release SW reset */ - reg_set16(GLOB_PHY_CTRL0_ADDR(USB3), + reg_set16(PHY_ADDR(USB3, GLOB_PHY_CTRL0), rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20, 0xFFFF); @@ -412,7 +411,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) udelay(PLL_SET_DELAY_US); /* Assert PCLK enabled */ - ret = comphy_poll_reg(LANE_STAT1_ADDR(USB3), /* address */ + ret = comphy_poll_reg(PHY_ADDR(USB3, LANE_STAT1), /* address */ rb_txdclk_pclk_en, /* value */ rb_txdclk_pclk_en, /* mask */ PLL_LOCK_TIMEOUT, /* timeout */ @@ -673,25 +672,25 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) mdelay(10); /* 9. Program COMPHY register PHY_MODE */ - reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR), + reg_set16(SGMIIPHY_ADDR(lane, PWR_PLL_CTRL), PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask); /* * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK * source */ - reg_set16(SGMIIPHY_ADDR(lane, PHY_MISC_REG0_ADDR), 0, rb_ref_clk_sel); + reg_set16(SGMIIPHY_ADDR(lane, MISC_REG0), 0, rb_ref_clk_sel); /* * 11. Set correct reference clock frequency in COMPHY register * REF_FREF_SEL. */ if (get_ref_clk() == 40) { - reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR), + reg_set16(SGMIIPHY_ADDR(lane, PWR_PLL_CTRL), 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); } else { /* 25MHz */ - reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR), + reg_set16(SGMIIPHY_ADDR(lane, PWR_PLL_CTRL), 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); } @@ -708,7 +707,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * bus width */ /* 10bit */ - reg_set16(SGMIIPHY_ADDR(lane, PHY_DIG_LB_EN_ADDR), 0, rf_data_width_mask); + reg_set16(SGMIIPHY_ADDR(lane, DIG_LB_EN), 0, rf_data_width_mask); /* * 14. As long as DFE function needs to be enabled in any mode, @@ -751,10 +750,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * 18. Check the PHY Polarity invert bit */ if (invert & PHY_POLARITY_TXD_INVERT) - reg_set16(SGMIIPHY_ADDR(lane, PHY_SYNC_PATTERN_ADDR), phy_txd_inv, 0); + reg_set16(SGMIIPHY_ADDR(lane, SYNC_PATTERN), phy_txd_inv, 0); if (invert & PHY_POLARITY_RXD_INVERT) - reg_set16(SGMIIPHY_ADDR(lane, PHY_SYNC_PATTERN_ADDR), phy_rxd_inv, 0); + reg_set16(SGMIIPHY_ADDR(lane, SYNC_PATTERN), phy_rxd_inv, 0); /* * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index a315bf2647..5031c25eb1 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -71,116 +71,98 @@ static inline void __iomem *SGMIIPHY_ADDR(u32 lane, u32 addr) } /* units */ -#define PCIE 1 -#define USB3 2 +enum phy_unit { + PCIE = 1, + USB3 = 2, +}; -#define PHY_BASE(unit) ((unit == PCIE) ? PCIEPHY_BASE : USB3PHY_BASE) -#define PHY_SHFT(unit) ((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT) +static inline void __iomem *PHY_ADDR(enum phy_unit unit, u32 addr) +{ + if (unit == PCIE) + return PCIEPHY_BASE + addr * PCIEPHY_SHFT; + else + return USB3PHY_BASE + addr * USB3PHY_SHFT; +} /* bit definition for USB32_CTRL_BASE (USB32 Control Mode) */ #define usb32_ctrl_id_mode BIT(0) #define usb32_ctrl_soft_id BIT(1) #define usb32_ctrl_int_mode BIT(4) - -#define PHY_PWR_PLL_CTRL_ADDR 0x01 /* for phy_read16 and phy_write16 */ -#define PWR_PLL_CTRL_ADDR(unit) \ - (PHY_PWR_PLL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define PWR_PLL_CTRL 0x01 #define rf_phy_mode_shift 5 #define rf_phy_mode_mask (0x7 << rf_phy_mode_shift) #define rf_ref_freq_sel_shift 0 #define rf_ref_freq_sel_mask (0x1F << rf_ref_freq_sel_shift) #define PHY_MODE_SGMII 0x4 -/* for phy_read16 and phy_write16 */ -#define PHY_REG_KVCO_CAL_CTRL_ADDR 0x02 -#define KVCO_CAL_CTRL_ADDR(unit) \ - (PHY_REG_KVCO_CAL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define KVCO_CAL_CTRL 0x02 #define rb_use_max_pll_rate BIT(12) #define rb_force_calibration_done BIT(9) -/* for phy_read16 and phy_write16 */ -#define PHY_DIG_LB_EN_ADDR 0x23 -#define DIG_LB_EN_ADDR(unit) \ - (PHY_DIG_LB_EN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define DIG_LB_EN 0x23 #define rf_data_width_shift 10 #define rf_data_width_mask (0x3 << rf_data_width_shift) -/* for phy_read16 and phy_write16 */ -#define PHY_SYNC_PATTERN_ADDR 0x24 -#define SYNC_PATTERN_ADDR(unit) \ - (PHY_SYNC_PATTERN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define SYNC_PATTERN 0x24 #define phy_txd_inv BIT(10) #define phy_rxd_inv BIT(11) -/* for phy_read16 and phy_write16 */ -#define PHY_REG_UNIT_CTRL_ADDR 0x48 -#define UNIT_CTRL_ADDR(unit) \ - (PHY_REG_UNIT_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define SYNC_MASK_GEN 0x25 #define rb_idle_sync_en BIT(12) -/* for phy_read16 and phy_write16 */ -#define PHY_REG_GEN2_SETTINGS_2 0x3e -#define GEN2_SETTING_2_ADDR(unit) \ - (PHY_REG_GEN2_SETTINGS_2 * PHY_SHFT(unit) + PHY_BASE(unit)) +#define UNIT_CTRL 0x48 + +#define GEN2_SETTINGS_2 0x3e #define g2_tx_ssc_amp BIT(14) -/* for phy_read16 and phy_write16 */ -#define PHY_REG_GEN2_SETTINGS_3 0x3f -#define GEN2_SETTING_3_ADDR(unit) \ - (PHY_REG_GEN2_SETTINGS_3 * PHY_SHFT(unit) + PHY_BASE(unit)) +#define GEN2_SETTINGS_3 0x3f + +#define GEN3_SETTINGS_3 0x112 -/* for phy_read16 and phy_write16 */ -#define PHY_MISC_REG0_ADDR 0x4f -#define MISC_REG0_ADDR(unit) \ - (PHY_MISC_REG0_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define MISC_REG0 0x4f #define rb_clk100m_125m_en BIT(4) #define rb_clk500m_en BIT(7) #define rb_ref_clk_sel BIT(10) -/* for phy_read16 and phy_write16 */ -#define PHY_REG_IFACE_REF_CLK_CTRL_ADDR 0x51 -#define UNIT_IFACE_REF_CLK_CTRL_ADDR(unit) \ - (PHY_REG_IFACE_REF_CLK_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define UNIT_IFACE_REF_CLK_CTRL 0x51 #define rb_ref1m_gen_div_force BIT(8) #define rf_ref1m_gen_div_value_shift 0 #define rf_ref1m_gen_div_value_mask (0xFF << rf_ref1m_gen_div_value_shift) -/* for phy_read16 and phy_write16 */ -#define PHY_REG_ERR_CNT_CONST_CTRL_ADDR 0x6A -#define UNIT_ERR_CNT_CONST_CTRL_ADDR(unit) \ - (PHY_REG_ERR_CNT_CONST_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define UNIT_ERR_CNT_CONST_CTRL 0x6a #define rb_fast_dfe_enable BIT(13) -#define MISC_REG1_ADDR(u) (0x73 * PHY_SHFT(u) + PHY_BASE(u)) +#define MISC_REG1 0x73 #define bf_sel_bits_pcie_force BIT(15) -#define LANE_CFG0_ADDR(u) (0x180 * PHY_SHFT(u) + PHY_BASE(u)) +#define LANE_CFG0 0x180 #define bf_use_max_pll_rate BIT(9) -#define LANE_CFG1_ADDR(u) (0x181 * PHY_SHFT(u) + PHY_BASE(u)) + +#define LANE_CFG1 0x181 #define bf_use_max_pll_rate BIT(9) -/* 0x5c310 = 0x93 (set BIT7) */ -#define LANE_CFG4_ADDR(u) (0x188 * PHY_SHFT(u) + PHY_BASE(u)) + +#define LANE_CFG4 0x188 #define bf_spread_spectrum_clock_en BIT(7) -#define LANE_STAT1_ADDR(u) (0x183 * PHY_SHFT(u) + PHY_BASE(u)) +#define LANE_STAT1 0x183 #define rb_txdclk_pclk_en BIT(0) -#define GLOB_PHY_CTRL0_ADDR(u) (0x1c1 * PHY_SHFT(u) + PHY_BASE(u)) +#define GLOB_PHY_CTRL0 0x1c1 #define bf_soft_rst BIT(0) #define bf_mode_refdiv 0x30 #define rb_mode_core_clk_freq_sel BIT(9) #define rb_mode_pipe_width_32 BIT(3) -#define TEST_MODE_CTRL_ADDR(u) (0x1c2 * PHY_SHFT(u) + PHY_BASE(u)) +#define TEST_MODE_CTRL 0x1c2 #define rb_mode_margin_override BIT(2) -#define GLOB_CLK_SRC_LO_ADDR(u) (0x1c3 * PHY_SHFT(u) + PHY_BASE(u)) +#define GLOB_CLK_SRC_LO 0x1c3 #define bf_cfg_sel_20b BIT(15) -#define PWR_MGM_TIM1_ADDR(u) (0x1d0 * PHY_SHFT(u) + PHY_BASE(u)) +#define PWR_MGM_TIM1 0x1d0 -#define PHY_REF_CLK_ADDR (0x4814 + PCIE_BASE) +#define PCIE_REF_CLK_ADDR (PCIE_BASE + 0x4814) #define USB3_CTRPUL_VAL_REG (0x20 + USB32_BASE) #define USB3H_CTRPUL_VAL_REG (0x3454 + USB32H_BASE) From patchwork Wed Mar 7 21:52:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882817 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="ZR/jMjzc"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSGB4c7Kz9sgw for ; Thu, 8 Mar 2018 08:58:58 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4AFC8C21F24; Wed, 7 Mar 2018 21:56:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 825D0C21F21; Wed, 7 Mar 2018 21:55:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 056E2C21E52; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 679A1C21E57 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 293896262A; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=MM0WpgWxWbueD6wm9sUQd5oWOgBVisftmfmyo46DHVU=; h=From:To:Date; b=ZR/jMjzcb8YY3REumAYPvR1xs5n6vmde5MpOzyC+knYoRhIv8D1ur1F0C08lM2Hsl 27E5Pr3ydXeB0scMfQ1OceV1XHTUMVHBfAtwR7EbvECedXYMbTj0tApzMRQgOfZj1D h2YUJPgZZFsmhUOyXvfuwi3CHQuMZEz5/iEGACNA= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:01 +0100 Message-Id: <20180307215216.10418-5-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 04/19] phy: marvell: a3700: Use same timeout for all register polling X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The timeout is set to PLL_LOCK_TIMEOUT in every call to comphy_poll_reg. Remove this parameter from the function. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 6506c134e2..d283604e1a 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -106,12 +106,11 @@ static u16 sgmii_phy_init[512] = { * * return: 1 on success, 0 on timeout */ -static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u32 timeout, - u8 op_type) +static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u8 op_type) { - u32 rval = 0xDEAD; + u32 rval = 0xDEAD, timeout; - for (; timeout > 0; timeout--) { + for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { if (op_type == POLL_16B_REG) rval = readw(addr); /* 16 bit */ else @@ -215,7 +214,6 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) ret = comphy_poll_reg(PHY_ADDR(PCIE, LANE_STAT1), /* address */ rb_txdclk_pclk_en, /* value */ rb_txdclk_pclk_en, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ POLL_16B_REG); /* 16bit */ if (ret == 0) printf("Failed to lock PCIe PLL\n"); @@ -285,7 +283,6 @@ static int comphy_sata_power_up(void) ret = comphy_poll_reg(rh_vsreg_data, /* address */ bs_pll_ready_tx, /* value */ bs_pll_ready_tx, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ POLL_32B_REG); /* 32bit */ if (ret == 0) printf("Failed to lock SATA PLL\n"); @@ -414,7 +411,6 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) ret = comphy_poll_reg(PHY_ADDR(USB3, LANE_STAT1), /* address */ rb_txdclk_pclk_en, /* value */ rb_txdclk_pclk_en, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ POLL_16B_REG); /* 16bit */ if (ret == 0) printf("Failed to lock USB3 PLL\n"); @@ -495,7 +491,6 @@ static int comphy_usb2_power_up(u8 usb32) ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32), rb_usb2phy_pllcal_done, /* value */ rb_usb2phy_pllcal_done, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ POLL_32B_REG); /* 32bit */ if (ret == 0) printf("Failed to end USB2 PLL calibration\n"); @@ -504,7 +499,6 @@ static int comphy_usb2_power_up(u8 usb32) ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32), rb_usb2phy_impcal_done, /* value */ rb_usb2phy_impcal_done, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ POLL_32B_REG); /* 32bit */ if (ret == 0) printf("Failed to end USB2 impedance calibration\n"); @@ -513,7 +507,6 @@ static int comphy_usb2_power_up(u8 usb32) ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32), rb_usb2phy_sqcal_done, /* value */ rb_usb2phy_sqcal_done, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ POLL_32B_REG); /* 32bit */ if (ret == 0) printf("Failed to end USB2 unknown calibration\n"); @@ -522,7 +515,6 @@ static int comphy_usb2_power_up(u8 usb32) ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32), rb_usb2phy_pll_ready, /* value */ rb_usb2phy_pll_ready, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ POLL_32B_REG); /* 32bit */ if (ret == 0) @@ -772,7 +764,6 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */ rb_pll_ready_tx | rb_pll_ready_rx, /* value */ rb_pll_ready_tx | rb_pll_ready_rx, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ POLL_32B_REG); /* 32bit */ if (ret == 0) printf("Failed to lock PLL for SGMII PHY %d\n", lane); @@ -795,7 +786,6 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */ rb_rx_init_done, /* value */ rb_rx_init_done, /* mask */ - PLL_LOCK_TIMEOUT, /* timeout */ POLL_32B_REG); /* 32bit */ if (ret == 0) printf("Failed to init RX of SGMII PHY %d\n", lane); From patchwork Wed Mar 7 21:52:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882820 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="wwy40sD0"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSHt2dYMz9sgw for ; Thu, 8 Mar 2018 09:00:26 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 130A6C21E79; Wed, 7 Mar 2018 21:57:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4A326C21FB3; Wed, 7 Mar 2018 21:55:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1B991C21C4A; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 7B15FC21E5B for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 326F662640; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=NkdGYEffRTZJ5Rs9ByuTHnReX9xVSvCWYLN8aUfjiWs=; h=From:To:Date; b=wwy40sD0RtDeutiVDkm5z0Wgym/angCfdGXXhVceLTBPwuOFslL85wHdClkoPoace 1EihLPu48fRy4D1N2O5M6icDM/WbvbAU5v74Gchaponlz3oEQeDfVTLpKnlt6D5TG+ yXgmfNUeaIjwR7V+ZSwI6bITVSrh+ZNSy2nww76E= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:02 +0100 Message-Id: <20180307215216.10418-6-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 05/19] phy: marvell: a3700: Use (!ret) instead of (ret == 0) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index d283604e1a..734d4e55b1 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -215,7 +215,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) rb_txdclk_pclk_en, /* value */ rb_txdclk_pclk_en, /* mask */ POLL_16B_REG); /* 16bit */ - if (ret == 0) + if (!ret) printf("Failed to lock PCIe PLL\n"); debug_exit(); @@ -284,7 +284,7 @@ static int comphy_sata_power_up(void) bs_pll_ready_tx, /* value */ bs_pll_ready_tx, /* mask */ POLL_32B_REG); /* 32bit */ - if (ret == 0) + if (!ret) printf("Failed to lock SATA PLL\n"); debug_exit(); @@ -412,7 +412,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) rb_txdclk_pclk_en, /* value */ rb_txdclk_pclk_en, /* mask */ POLL_16B_REG); /* 16bit */ - if (ret == 0) + if (!ret) printf("Failed to lock USB3 PLL\n"); /* @@ -492,7 +492,7 @@ static int comphy_usb2_power_up(u8 usb32) rb_usb2phy_pllcal_done, /* value */ rb_usb2phy_pllcal_done, /* mask */ POLL_32B_REG); /* 32bit */ - if (ret == 0) + if (!ret) printf("Failed to end USB2 PLL calibration\n"); /* Assert impedance calibration done */ @@ -500,7 +500,7 @@ static int comphy_usb2_power_up(u8 usb32) rb_usb2phy_impcal_done, /* value */ rb_usb2phy_impcal_done, /* mask */ POLL_32B_REG); /* 32bit */ - if (ret == 0) + if (!ret) printf("Failed to end USB2 impedance calibration\n"); /* Assert squetch calibration done */ @@ -508,7 +508,7 @@ static int comphy_usb2_power_up(u8 usb32) rb_usb2phy_sqcal_done, /* value */ rb_usb2phy_sqcal_done, /* mask */ POLL_32B_REG); /* 32bit */ - if (ret == 0) + if (!ret) printf("Failed to end USB2 unknown calibration\n"); /* Assert PLL is ready */ @@ -517,7 +517,7 @@ static int comphy_usb2_power_up(u8 usb32) rb_usb2phy_pll_ready, /* mask */ POLL_32B_REG); /* 32bit */ - if (ret == 0) + if (!ret) printf("Failed to lock USB2 PLL\n"); debug_exit(); @@ -765,7 +765,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) rb_pll_ready_tx | rb_pll_ready_rx, /* value */ rb_pll_ready_tx | rb_pll_ready_rx, /* mask */ POLL_32B_REG); /* 32bit */ - if (ret == 0) + if (!ret) printf("Failed to lock PLL for SGMII PHY %d\n", lane); /* @@ -787,7 +787,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) rb_rx_init_done, /* value */ rb_rx_init_done, /* mask */ POLL_32B_REG); /* 32bit */ - if (ret == 0) + if (!ret) printf("Failed to init RX of SGMII PHY %d\n", lane); debug_exit(); @@ -818,7 +818,7 @@ void comphy_dedicated_phys_init(void) if (node > 0) { if (fdtdec_get_is_enabled(blob, node)) { ret = comphy_usb2_power_up(usb32); - if (ret == 0) + if (!ret) printf("Failed to initialize UTMI PHY\n"); else debug("UTMI PHY init succeed\n"); @@ -836,7 +836,7 @@ void comphy_dedicated_phys_init(void) if (node > 0) { if (fdtdec_get_is_enabled(blob, node)) { ret = comphy_sata_power_up(); - if (ret == 0) + if (!ret) printf("Failed to initialize SATA PHY\n"); else debug("SATA PHY init succeed\n"); @@ -857,7 +857,7 @@ void comphy_dedicated_phys_init(void) if (node > 0) { if (fdtdec_get_is_enabled(blob, node)) { ret = comphy_emmc_power_up(); - if (ret == 0) + if (!ret) printf("Failed to initialize SDIO/eMMC PHY\n"); else debug("SDIO/eMMC PHY init succeed\n"); @@ -915,7 +915,7 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, ret = 1; break; } - if (ret == 0) + if (!ret) printf("PLL is not locked - Failed to initialize lane %d\n", lane); } From patchwork Wed Mar 7 21:52:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882812 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="YkKqWQ+C"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSDd140Gz9sgw for ; Thu, 8 Mar 2018 08:57:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C6AFDC21E68; Wed, 7 Mar 2018 21:56:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D1BAFC21F24; Wed, 7 Mar 2018 21:55:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C4A9EC21E57; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 82BB4C21E62 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 3E0D862643; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=9jwAxYZK9zXsWOmeGnsyvNabZVAck9NA25aUHtj6MsI=; h=From:To:Date; b=YkKqWQ+CEbvW22kKDBv+5+jLcV9vTfMXtRTvYLo9Ehbk7I18vXxg3iBzIRUDd2MwB 54ExEGSEeTr8lMCUlXYiLxzNtLW9Ug4OdcCI8IPLimxb2sHqDvaKkQ5nTA3Yk0zPQT 061fD2ru8YmFAs6w6uenBjdkbq4yHRos9k74r/AA= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:03 +0100 Message-Id: <20180307215216.10418-7-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 06/19] phy: marvell: a3700: Use reg_set_indirect istead of 2 reg_sets X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Create a special function for indirect register setting, reg_set_indirect, and use it instead of the two calls to reg_set. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 734d4e55b1..81d24a5b61 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -224,6 +224,17 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) return ret; } +/* + * reg_set_indirect + * + * return: void + */ +static inline void reg_set_indirect(u32 reg, u16 data, u16 mask) +{ + reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF); + reg_set(rh_vsreg_data, data, mask); +} + /* * comphy_sata_power_up * @@ -231,43 +242,40 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) */ static int comphy_sata_power_up(void) { - int ret; + int ret; debug_enter(); /* * 0. Swap SATA TX lines */ - reg_set(rh_vsreg_addr, vphy_sync_pattern_reg, 0xFFFFFFFF); - reg_set(rh_vsreg_data, bs_txd_inv, bs_txd_inv); + reg_set_indirect(vphy_sync_pattern_reg, bs_txd_inv, bs_txd_inv); /* * 1. Select 40-bit data width width */ - reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); - reg_set(rh_vsreg_data, 0x800, bs_phyintf_40bit); + reg_set_indirect(vphy_loopback_reg0, 0x800, bs_phyintf_40bit); /* * 2. Select reference clock and PHY mode (SATA) */ - reg_set(rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF); if (get_ref_clk() == 40) { - reg_set(rh_vsreg_data, 0x3, 0x00FF); /* 40 MHz */ + /* 40 MHz */ + reg_set_indirect(vphy_power_reg0, 0x3, 0x00FF); } else { - reg_set(rh_vsreg_data, 0x1, 0x00FF); /* 25 MHz */ + /* 20 MHz */ + reg_set_indirect(vphy_power_reg0, 0x1, 0x00FF); } /* * 3. Use maximum PLL rate (no power save) */ - reg_set(rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF); - reg_set(rh_vsreg_data, bs_max_pll_rate, bs_max_pll_rate); + reg_set_indirect(vphy_calctl_reg, bs_max_pll_rate, bs_max_pll_rate); /* * 4. Reset reserved bit (??) */ - reg_set(rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF); - reg_set(rh_vsreg_data, 0, bs_phyctrl_frm_pin); + reg_set_indirect(vphy_reserve_reg, 0, bs_phyctrl_frm_pin); /* * 5. Set vendor-specific configuration (??) From patchwork Wed Mar 7 21:52:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882818 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="gHZ1+/M/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSGD6BSpz9sgw for ; Thu, 8 Mar 2018 08:59:00 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 862CDC21F1F; Wed, 7 Mar 2018 21:57:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0B89CC21FCD; Wed, 7 Mar 2018 21:55:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3829DC21E62; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 930A1C21BE5 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 4FFCB62654; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=/4CElCPACgzCfveeqP9EArTCiHFN+VulA4M0LvjrzEI=; h=From:To:Date; b=gHZ1+/M/D++N2talRz2xIHuG1AbjBvLGB0zvhYi4nw0BaNRiag10tbdbhij8C+Rnn leQje2ginHScIiKe4D/mZl++16kbYPR3LtXmQT7XSQpQ2Y/w2vMYZH9RlCJRqEDUDW 8n1RWeab653Q3GSz9rRTSDu7aJYEgi88dqAD7k64= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:04 +0100 Message-Id: <20180307215216.10418-8-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 07/19] phy: marvell: a3700: Access USB3 register indirectly on lane 2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When USB3 is on comphy lane 2 on the Armada 37xx, the registers have to be accessed indirectly via SATA indirect access. Signed-off-by: Marek Behun --- drivers/phy/marvell/comphy_a3700.c | 111 +++++++++++++++++++++++++------------ drivers/phy/marvell/comphy_a3700.h | 1 + 2 files changed, 78 insertions(+), 34 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 81d24a5b61..b5f2013bbb 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -133,7 +133,7 @@ static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u8 op_type) */ static int comphy_pcie_power_up(u32 speed, u32 invert) { - int ret; + int ret; debug_enter(); @@ -300,17 +300,50 @@ static int comphy_sata_power_up(void) return ret; } +/* + * usb3_reg_set16_indirect + * + * return: void + */ +static void usb3_reg_set16_indirect(u32 reg, u16 data, u16 mask) +{ + reg_set_indirect(USB3PHY_LANE2_REG_BASE_OFFSET + reg, data, mask); +} + +/* + * usb3_reg_set16_direct + * + * return: void + */ +static void usb3_reg_set16_direct(u32 reg, u16 data, u16 mask) +{ + reg_set16(PHY_ADDR(USB3, reg), data, mask); +} + /* * comphy_usb3_power_up * * return: 1 if PLL locked (OK), 0 otherwise (FAIL) */ -static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) +static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) { - int ret; + int ret; + void (*usb3_reg_set16)(u32, u16, u16); debug_enter(); + /* + * When Lane 2 PHY is for USB3, access the PHY registers + * through indirect Address and Data registers INDIR_ACC_PHY_ADDR + * (RD00E0178h [31:0]) and INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]) + * within the SATA Host Controller registers, Lane 2 base register + * offset is 0x200 + */ + if (lane == 2) + usb3_reg_set16 = usb3_reg_set16_indirect; + else + usb3_reg_set16 = usb3_reg_set16_direct; + /* * 1. Power up OTG module */ @@ -325,38 +358,38 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) /* 0xd005c300 = 0x1001 */ /* set PRD_TXDEEMPH (3.5db de-emph) */ - reg_set16(PHY_ADDR(USB3, LANE_CFG0), 0x1, 0xFF); + usb3_reg_set16(LANE_CFG0, 0x1, 0xFF); /* * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in - * low impedance mode during electrical idle + * low impedance mode during electrical idle + * unset BIT4: set G2 Tx Datapath with no Delayed Latency + * unset BIT6: set Tx Detect Rx Mode at LoZ mode */ - /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */ - /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */ - reg_set16(PHY_ADDR(USB3, LANE_CFG1), 0x0, 0xFFFF); + usb3_reg_set16(LANE_CFG1, 0x0, 0xFFFF); - /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ - reg_set16(PHY_ADDR(USB3, LANE_CFG4), bf_spread_spectrum_clock_en, 0x80); + /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ + usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80); /* * set Override Margining Controls From the MAC: Use margining signals * from lane configuration */ - reg_set16(PHY_ADDR(USB3, TEST_MODE_CTRL), rb_mode_margin_override, 0xFFFF); + usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF); /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ /* set Mode Clock Source = PCLK is generated from REFCLK */ - reg_set16(PHY_ADDR(USB3, GLOB_CLK_SRC_LO), 0x0, 0xFF); + usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF); /* set G2 Spread Spectrum Clock Amplitude at 4K */ - reg_set16(PHY_ADDR(USB3, GEN2_SETTINGS_2), g2_tx_ssc_amp, 0xF000); + usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000); /* * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register * Master Current Select */ - reg_set16(PHY_ADDR(USB3, GEN2_SETTINGS_3), 0x0, 0xFFFF); + usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF); /* * 3. Check crystal jumper setting and program the Power and PLL @@ -364,62 +397,71 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) */ if (get_ref_clk() == 40) { /* 40 MHz */ - reg_set16(PHY_ADDR(USB3, PWR_PLL_CTRL), 0xFCA3, 0xFFFF); + usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF); } else { /* 25 MHz */ - reg_set16(PHY_ADDR(USB3, PWR_PLL_CTRL), 0xFCA2, 0xFFFF); + usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF); } /* * 4. Change RX wait */ - reg_set16(PHY_ADDR(USB3, PWR_MGM_TIM1), 0x10C, 0xFFFF); + usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF); /* * 5. Enable idle sync */ - reg_set16(PHY_ADDR(USB3, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); + usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF); /* * 6. Enable the output of 500M clock */ - reg_set16(PHY_ADDR(USB3, MISC_REG0), 0xA00D | rb_clk500m_en, 0xFFFF); + usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF); /* * 7. Set 20-bit data width */ - reg_set16(PHY_ADDR(USB3, DIG_LB_EN), 0x0400, 0xFFFF); + usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF); /* * 8. Override Speed_PLL value and use MAC PLL */ - reg_set16(PHY_ADDR(USB3, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, - 0xFFFF); + usb3_reg_set16(KVCO_CAL_CTRL, 0x0040 | rb_use_max_pll_rate, 0xFFFF); /* * 9. Check the Polarity invert bit */ if (invert & PHY_POLARITY_TXD_INVERT) - reg_set16(PHY_ADDR(USB3, SYNC_PATTERN), phy_txd_inv, 0); + usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0); if (invert & PHY_POLARITY_RXD_INVERT) - reg_set16(PHY_ADDR(USB3, SYNC_PATTERN), phy_rxd_inv, 0); + usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0); /* * 10. Release SW reset */ - reg_set16(PHY_ADDR(USB3, GLOB_PHY_CTRL0), - rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20, - 0xFFFF); + usb3_reg_set16(GLOB_PHY_CTRL0, + rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 + | 0x20, 0xFFFF); /* Wait for > 55 us to allow PCLK be enabled */ udelay(PLL_SET_DELAY_US); /* Assert PCLK enabled */ - ret = comphy_poll_reg(PHY_ADDR(USB3, LANE_STAT1), /* address */ - rb_txdclk_pclk_en, /* value */ - rb_txdclk_pclk_en, /* mask */ - POLL_16B_REG); /* 16bit */ + if (lane == 2) { + reg_set(rh_vsreg_addr, + LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET, + 0xFFFFFFFF); + ret = comphy_poll_reg(rh_vsreg_data, /* address */ + rb_txdclk_pclk_en, /* value */ + rb_txdclk_pclk_en, /* mask */ + POLL_32B_REG); /* 32bit */ + } else { + ret = comphy_poll_reg(PHY_ADDR(USB3, LANE_STAT1), /* address */ + rb_txdclk_pclk_en, /* value */ + rb_txdclk_pclk_en, /* mask */ + POLL_16B_REG); /* 16bit */ + } if (!ret) printf("Failed to lock USB3 PLL\n"); @@ -455,7 +497,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) */ static int comphy_usb2_power_up(u8 usb32) { - int ret; + int ret; debug_enter(); @@ -620,7 +662,7 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) */ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) { - int ret; + int ret; debug_enter(); @@ -906,7 +948,8 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, case PHY_TYPE_USB3_HOST0: case PHY_TYPE_USB3_DEVICE: - ret = comphy_usb3_power_up(comphy_map->type, + ret = comphy_usb3_power_up(lane, + comphy_map->type, comphy_map->speed, comphy_map->invert); break; diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index 5031c25eb1..772e86515a 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -60,6 +60,7 @@ #define USB2PHY2_BASE MVEBU_REG(0x05F000) #define USB32_CTRL_BASE MVEBU_REG(0x05D800) #define USB3PHY_SHFT 2 +#define USB3PHY_LANE2_REG_BASE_OFFSET 0x200 static inline void __iomem *SGMIIPHY_ADDR(u32 lane, u32 addr) { From patchwork Wed Mar 7 21:52:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882828 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="oRRdgT9/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSN51njBz9sgt for ; Thu, 8 Mar 2018 09:04:05 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F3555C21F1F; Wed, 7 Mar 2018 21:59:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id F0A5DC21F9B; Wed, 7 Mar 2018 21:55:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 44D38C21E3A; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id A599DC21EA2 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 62CD26266E; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=VCUy+WjThAuPONcqNcJEzXu+ivnfks/tcWfYlDNBqKU=; h=From:To:Date; b=oRRdgT9/IcQR2ABx3OJspQxe9etJHNMN5QtkuJMbye3IZBgBHTv8jDYEPus6yoJKd sHrSdW/OiaDNROKEAgtaXqMjYRKHuckvmdHGfe59KCe5f8y5pGhM+B0KadWHOlqqkE 16RRzu+BB/gRp8RRZ62NVqVBMNwTSiPHu41F6uhw= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:05 +0100 Message-Id: <20180307215216.10418-9-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 08/19] phy: marvell: a3700: Set USB3 RX wait depending on ref clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7 when reference clock is at 25 MHz. The specification (at least the version I have) does not mentoin the setting for 40 MHz reference clock, but Marvell's U-Boot sets 0xC in that case. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index b5f2013bbb..78caa96014 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -394,20 +394,18 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) /* * 3. Check crystal jumper setting and program the Power and PLL * Control accordingly + * 4. Change RX wait */ if (get_ref_clk() == 40) { /* 40 MHz */ usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF); + usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF); } else { /* 25 MHz */ usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF); + usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF); } - /* - * 4. Change RX wait - */ - usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF); - /* * 5. Enable idle sync */ From patchwork Wed Mar 7 21:52:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882827 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="GIfkXCMn"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSMx5PBnz9sgt for ; Thu, 8 Mar 2018 09:03:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6496FC21F05; Wed, 7 Mar 2018 21:59:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 24F66C21FEF; Wed, 7 Mar 2018 21:55:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A3953C21E3A; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id AFD65C21C4A for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 72A5562673; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=GSA2AFMqH6WPwgk4wZpLRwUsQ6OoccDgJyWU695cts0=; h=From:To:Date; b=GIfkXCMnJ/FMs/4lniC3jSLv7AHisnO+NBaZc4ds2I9hhvifX9juB+bTF8eWCDGah zTtFm8wSSIN4Wd7Qu26bbL/hM/uxbo4RQTcmzckzbA1sdQxiuSKdtm1v9xvQncpJ7j l9SuqxcGh8/5s2p8uQEl7Qf4sOofgJFI8FzR3LmM= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:06 +0100 Message-Id: <20180307215216.10418-10-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 09/19] phy: marvell: a3700: revise the USB3 comphy setting during power on X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit is based on commit d9899826 by zachary from u-boot-marvell, see github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/d9899826 - According to design specification, the transmitter should be set to high impedence mode during electrical idle. Thus transmitter should detect RX at high impedence mode also, and delay is needed to accommodate high impedence off latency. Otherwise the USB3 will have detection issue that most of the time the USB3 device can not be detected at all, or be detected as USB2 device sometimes. Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1 Bit 6: set to 1 to let Tx detect Rx at HiZ mode Bit [3:4]: set to 2 to be delayed by 2 clock cycles Bit 0: set to 1 to set transmitter to high impedance mode during idle. - USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2 (emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed to select 0x1(3.5dB emphasize). Thus need to override what comes from the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register 0x181 and bit0 of register 0x180). - According to USB3 application note, need to update below comphy registers: Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1) Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF) Signed-off-by: Marek Behun --- drivers/phy/marvell/comphy_a3700.c | 31 +++++++++++++++++++++++-------- drivers/phy/marvell/comphy_a3700.h | 5 +++++ 2 files changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 78caa96014..1182842609 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -361,13 +361,18 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) usb3_reg_set16(LANE_CFG0, 0x1, 0xFF); /* - * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in - * low impedance mode during electrical idle - * unset BIT4: set G2 Tx Datapath with no Delayed Latency - * unset BIT6: set Tx Detect Rx Mode at LoZ mode - */ - usb3_reg_set16(LANE_CFG1, 0x0, 0xFFFF); - + * Set BIT0: enable transmitter in high impedance mode + * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency + * Set BIT6: Tx detect Rx at HiZ mode + * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db + * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR + * register + */ + usb3_reg_set16(LANE_CFG1, + tx_det_rx_mode | gen2_tx_data_dly_deft + | tx_elec_idle_mode_en, + prd_txdeemph1_mask | tx_det_rx_mode + | gen2_tx_data_dly_mask | tx_elec_idle_mode_en); /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80); @@ -436,7 +441,17 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0); /* - * 10. Release SW reset + * 10. Set max speed generation to USB3.0 5Gbps + */ + usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00); + + /* + * 11. Set capacitor value for FFE gain peaking to 0xF + */ + usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF); + + /* + * 12. Release SW reset */ usb3_reg_set16(GLOB_PHY_CTRL0, rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index 772e86515a..ef55f719b9 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -142,6 +142,11 @@ static inline void __iomem *PHY_ADDR(enum phy_unit unit, u32 addr) #define LANE_CFG1 0x181 #define bf_use_max_pll_rate BIT(9) +#define prd_txdeemph1_mask BIT(15) +#define tx_det_rx_mode BIT(6) +#define gen2_tx_data_dly_deft (2 << 3) +#define gen2_tx_data_dly_mask (BIT(3) | BIT(4)) +#define tx_elec_idle_mode_en BIT(0) #define LANE_CFG4 0x188 #define bf_spread_spectrum_clock_en BIT(7) From patchwork Wed Mar 7 21:52:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882816 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="E8b7scLI"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSG11MtZz9sgy for ; Thu, 8 Mar 2018 08:58:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 32F99C21E62; Wed, 7 Mar 2018 21:58:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 439C5C21F47; Wed, 7 Mar 2018 21:55:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6FEABC21C4A; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id BF89CC21DB6 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 7CBB16267E; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=GJ4Q39zdOgONxVjV5Mx+2jW6b1V42gZOSOGLs66THGE=; h=From:To:Date; b=E8b7scLIbTycLdqoBY6qHOJHYCURDKOg9WKdWaAG0y+VxkKCauKLlBCGrirJNUcOO Os6nHX1MpuxnADyi/DL4E2FpoZuidv0sIu5N3vJDrw5VPYO4074VYlfXhXVn7K4VPh 9wdASc9LtDviUOK2+i7GUOK2zZQiYQsmfdLBud3g= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:07 +0100 Message-Id: <20180307215216.10418-11-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 10/19] phy: marvell: mux: Support nontrivial node order in selector register X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently comphy_mux supports only trivial order of nodes in pin selector register, that is lane N on position N*bitcount. Add support for nontrivial order, with map stored in device tree property mux-lane-order. This is needed for Armada 37xx. Signed-off-by: Marek Behun --- drivers/phy/marvell/comphy.h | 1 + drivers/phy/marvell/comphy_core.c | 4 ++++ drivers/phy/marvell/comphy_mux.c | 15 ++++++++++++--- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h index c9b94a4c5e..32e0a1e652 100644 --- a/drivers/phy/marvell/comphy.h +++ b/drivers/phy/marvell/comphy.h @@ -97,6 +97,7 @@ struct chip_serdes_phy_config { void __iomem *hpipe3_base_addr; u32 comphy_lanes_count; u32 comphy_mux_bitcount; + const fdt32_t *comphy_mux_lane_order; u32 cp_index; }; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 426db30f73..1e5664c435 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -135,6 +135,10 @@ static int comphy_probe(struct udevice *dev) return -EINVAL; } + chip_cfg->comphy_mux_lane_order = + fdtdec_locate_array(blob, node, "mux-lane-order", + chip_cfg->comphy_lanes_count); + if (device_is_compatible(dev, "marvell,comphy-armada-3700")) chip_cfg->ptr_comphy_chip_init = comphy_a3700_init; diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index b036fb13b9..a8b07fdc98 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -79,7 +79,8 @@ static u32 comphy_mux_get_mux_value(struct comphy_mux_data *mux_data, static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, struct comphy_map *comphy_map_data, int comphy_max_lanes, - void __iomem *selector_base, u32 bitcount) + void __iomem *selector_base, + const fdt32_t *mux_lane_order, u32 bitcount) { u32 lane, value, offset, mask; @@ -90,7 +91,13 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, if (comphy_map_data->type == PHY_TYPE_IGNORE) continue; - offset = lane * bitcount; + /* if the order of nodes in selector base register is + nontrivial, use mapping from mux_lane_order */ + if (mux_lane_order) + offset = fdt32_to_cpu(mux_lane_order[lane]) * bitcount; + else + offset = lane * bitcount; + mask = (((1 << bitcount) - 1) << offset); value = (comphy_mux_get_mux_value(mux_data, comphy_map_data->type, @@ -106,6 +113,7 @@ void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg, void __iomem *selector_base) { struct comphy_mux_data *mux_data; + const fdt32_t *mux_lane_order; u32 mux_bitcount; u32 comphy_max_lanes; @@ -113,13 +121,14 @@ void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg, comphy_max_lanes = chip_cfg->comphy_lanes_count; mux_data = chip_cfg->mux_data; + mux_lane_order = chip_cfg->comphy_mux_lane_order; mux_bitcount = chip_cfg->comphy_mux_bitcount; /* check if the configuration is valid */ comphy_mux_check_config(mux_data, comphy_map_data, comphy_max_lanes); /* Init COMPHY selectors */ comphy_mux_reg_write(mux_data, comphy_map_data, comphy_max_lanes, - selector_base, mux_bitcount); + selector_base, mux_lane_order, mux_bitcount); debug_exit(); } From patchwork Wed Mar 7 21:52:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882824 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="IcfvCnmY"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSLn725Yz9sgt for ; Thu, 8 Mar 2018 09:02:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 905EFC21F58; Wed, 7 Mar 2018 21:59:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 27A56C21FE3; Wed, 7 Mar 2018 21:55:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 23C1BC21C4A; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id D3616C21E68 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 8D70062691; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=R/9PXT1mFxDFsMe9OjWNMyzFdW/Ma8keI4I78iNcMcU=; h=From:To:Date; b=IcfvCnmYt+l6LkKk6bPqsZh0MK5ebUYua3aPxc3KTp1sg4L7bIPFP/4j6gP36rZW4 l334/PbnK9icjg3fRgNjfPHrd7TpRorPHUQOHhPgk/sY3N+squxGEUgHJUnJL5aat8 gsyGcJTypiYgY6MHmAvG6yOMmwTYxiPAzhDakwWE= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:08 +0100 Message-Id: <20180307215216.10418-12-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 11/19] phy: marvell: a3700: Use comphy_mux on Armada 37xx. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Lane 0 supports SGMII1 and USB3. Lane 1 supports SGMII0 and PEX0. Lane 2 supports SATA0 and USB3. This is needed for Armada 37xx. Signed-off-by: Marek Behun --- arch/arm/dts/armada-37xx.dtsi | 5 +++-- drivers/phy/marvell/comphy_a3700.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index 690234234b..d0529637f4 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -284,8 +284,9 @@ compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; reg = <0x18300 0x28>, <0x1f300 0x3d000>; - mux-bitcount = <1>; - max-lanes = <2>; + mux-bitcount = <4>; + mux-lane-order = <1 0 2>; + max-lanes = <3>; }; }; }; diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 1182842609..c665d6fde8 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -14,6 +14,38 @@ DECLARE_GLOBAL_DATA_PTR; +struct comphy_mux_data a3700_comphy_mux_data[] = { +/* Lane 0 */ + { + 4, + { + { PHY_TYPE_UNCONNECTED, 0x0 }, + { PHY_TYPE_SGMII1, 0x0 }, + { PHY_TYPE_USB3_HOST0, 0x1 }, + { PHY_TYPE_USB3_DEVICE, 0x1 } + } + }, +/* Lane 1 */ + { + 3, + { + { PHY_TYPE_UNCONNECTED, 0x0}, + { PHY_TYPE_SGMII0, 0x0}, + { PHY_TYPE_PEX0, 0x1} + } + }, +/* Lane 2 */ + { + 4, + { + { PHY_TYPE_UNCONNECTED, 0x0}, + { PHY_TYPE_SATA0, 0x0}, + { PHY_TYPE_USB3_HOST0, 0x1}, + { PHY_TYPE_USB3_DEVICE, 0x1} + } + }, +}; + struct sgmii_phy_init_data_fix { u16 addr; u16 value; @@ -943,6 +975,10 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, debug_enter(); + /* Initialize PHY mux */ + chip_cfg->mux_data = a3700_comphy_mux_data; + comphy_mux_init(chip_cfg, serdes_map, COMPHY_SEL_ADDR); + for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count; lane++, comphy_map++) { debug("Initialize serdes number %d\n", lane); From patchwork Wed Mar 7 21:52:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882819 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="u6Q/kwnR"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSH213Wyz9sgw for ; Thu, 8 Mar 2018 08:59:41 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id AD505C21F21; Wed, 7 Mar 2018 21:57:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 18F2DC21FD4; Wed, 7 Mar 2018 21:55:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4F994C21E3A; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id DA3DCC21E5B for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 9EAA0626A2; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=/L2DPNE7b7WOj+02M1Z3cEmFq+gLldWslO/epBnn4+c=; h=From:To:Date; b=u6Q/kwnRDrAcqWcd1JcMJFk+IYLy/kSLb1CTGI2HeWa6f1toIuR2qZrawae6RKvK/ /BHEmXNe7XwgvYZyVxSWCd27sKTwVEbwN+k/7KOGjbz/cWdMW1nQqq4wALen9m6UXJ kzndVTiGBsa+Dqgci0yw2H9OhkrSRiUVHXEgUqGc= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:09 +0100 Message-Id: <20180307215216.10418-13-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 12/19] phy: marvell: a3700: Save/restore selector reg in SGMII init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In SGMII initialization PIN_PIPE_SEL has to be zero when resetting the PHY. Since comphy_mux already set the selector register to correct values, we have to store it's value before setting it to 0 and restore it after SGMII init. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 9 ++++++++- drivers/phy/marvell/comphy_a3700.h | 1 - 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index c665d6fde8..71245b766f 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -708,13 +708,15 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) { int ret; + u32 saved_selector; debug_enter(); /* * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 */ - reg_set(COMPHY_SEL_ADDR, 0, rf_compy_select(lane)); + saved_selector = readl(COMPHY_SEL_ADDR); + reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF); /* * 2. Reset PHY by setting PHY input port PIN_RESET=1. @@ -885,6 +887,11 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) if (!ret) printf("Failed to init RX of SGMII PHY %d\n", lane); + /* + * Restore saved selector. + */ + reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF); + debug_exit(); return ret; diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index ef55f719b9..b674ef9064 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -23,7 +23,6 @@ * COMPHY SB definitions */ #define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC) -#define rf_compy_select(lane) (0x1 << (((lane) == 1) ? 4 : 0)) #define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (lane) * 0x28) #define rb_pin_pu_iveref BIT(1) From patchwork Wed Mar 7 21:52:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882822 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="Fod5D20y"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSKV5cyYz9s8v for ; Thu, 8 Mar 2018 09:01:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6792EC21F4E; Wed, 7 Mar 2018 21:59:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 27820C21FD6; Wed, 7 Mar 2018 21:55:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D0A51C21E3B; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id E67E7C21E79 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id A59C7626A4; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=ogmDkvcsQhC64F3wB5l6hi6gCJyKSvvByIIhzmISmn8=; h=From:To:Date; b=Fod5D20yz6kY5bLdbsuguffILP0Kcr/jhx/dg8QvM3RwTyIhIprV4BfhKwTLxcYSz 2WnMtCH8mqqDHeTHUGnLu4hpS2WvrAZeoQ8N5cPRs2ltVZsY+1RcG5BcGPYf/0E+zJ Uin3w01yxayP8rTCflHaUJ4dZIE0KhHc3V96OcXE= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:10 +0100 Message-Id: <20180307215216.10418-14-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 13/19] arm64: mvebu_armada_37xx: Use Armada 37xx pinctrl driver by default X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The driver is already in the tree and functional. Enable it by default and also remove the board_early_init_f which was a temporary fix for not having the pinctrl driver. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- board/Marvell/mvebu_armada-37xx/board.c | 32 ----------------------------- configs/mvebu_db-88f3720_defconfig | 5 ++++- configs/mvebu_espressobin-88f3720_defconfig | 5 ++++- 3 files changed, 8 insertions(+), 34 deletions(-) diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index ac3e3a392f..fdd42788d2 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -21,10 +21,6 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_IO_REG_0_SATA_OFF 2 #define I2C_IO_REG_0_USB_H_OFF 1 -/* The pin control values are the same for DB and Espressobin */ -#define PINCTRL_NB_REG_VALUE 0x000173fa -#define PINCTRL_SB_REG_VALUE 0x00007a23 - /* Ethernet switch registers */ /* SMI addresses for multi-chip mode */ #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p)) @@ -48,34 +44,6 @@ DECLARE_GLOBAL_DATA_PTR; #define MVEBU_G2_SMI_PHY_CMD_REG (24) #define MVEBU_G2_SMI_PHY_DATA_REG (25) -int board_early_init_f(void) -{ - const void *blob = gd->fdt_blob; - const char *bank_name; - const char *compat = "marvell,armada-3700-pinctl"; - int off, len; - void __iomem *addr; - - /* FIXME - * Temporary WA for setting correct pin control values - * until the real pin control driver is awailable. - */ - off = fdt_node_offset_by_compatible(blob, -1, compat); - while (off != -FDT_ERR_NOTFOUND) { - bank_name = fdt_getprop(blob, off, "bank-name", &len); - addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent( - blob, off, "reg", 0, NULL, true); - if (!strncmp(bank_name, "armada-3700-nb", len)) - writel(PINCTRL_NB_REG_VALUE, addr); - else if (!strncmp(bank_name, "armada-3700-sb", len)) - writel(PINCTRL_SB_REG_VALUE, addr); - - off = fdt_node_offset_by_compatible(blob, off, compat); - } - - return 0; -} - int board_init(void) { /* adress of boot parameters */ diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 1d6233a6ff..338d764d84 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -12,7 +12,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_EARLY_INIT_R=y -CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -38,6 +37,10 @@ CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_XENON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_GENERIC=y +CONFIG_PINMUX=y +CONFIG_PINCTRL_ARMADA_37XX=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 314d405ea3..28005e6131 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -12,7 +12,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_EARLY_INIT_R=y -CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -35,6 +34,10 @@ CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_XENON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_GENERIC=y +CONFIG_PINMUX=y +CONFIG_PINCTRL_ARMADA_37XX=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y From patchwork Wed Mar 7 21:52:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882832 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="CWzYh+eH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSSX6lX0z9rxj for ; Thu, 8 Mar 2018 09:07:56 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 89EFFC21ED5; Wed, 7 Mar 2018 22:01:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 21A87C22026; Wed, 7 Mar 2018 21:55:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D94C7C21BE5; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id F33C4C21BE5 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id B7548626AE; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=8Zq8Znb0C1Z4lhSRkRZkq9ORLO8qxK9ZogTjXxKP2XQ=; h=From:To:Date; b=CWzYh+eHO5GOTejhy2KVyRJIR8gdWKoIAtAWh2Sv0cbL7mqz8dq8PKFzV/c4IBzZ8 e+f00WCtym1og4WGU9o8pDEhH0D+6sRnz6LwoSOh9YrIR80YmsnvFq6bAXVO2Sv5sH uIxppbHryCJISbLdyuVtrtMPvF5kexsdgC9FMUk8= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:11 +0100 Message-Id: <20180307215216.10418-15-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 14/19] driver: clk: Add support for clocks on Armada 37xx X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- arch/arm/dts/armada-37xx.dtsi | 20 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/mvebu/Kconfig | 11 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/armada-37xx-periph.c | 464 +++++++++++++++++++++++++++++++++ drivers/clk/mvebu/armada-37xx-tbg.c | 153 +++++++++++ 7 files changed, 651 insertions(+) diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index d0529637f4..e848812fca 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -106,6 +106,26 @@ status = "disabled"; }; + nb_periph_clk: nb-periph-clk@13000 { + compatible = "marvell,armada-3700-periph-clock-nb"; + reg = <0x13000 0x100>; + clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>; + #clock-cells = <1>; + }; + + sb_periph_clk: sb-periph-clk@18000 { + compatible = "marvell,armada-3700-periph-clock-sb"; + reg = <0x18000 0x100>; + clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>; + #clock-cells = <1>; + }; + + tbg: tbg@13200 { + compatible = "marvell,armada-3700-tbg-clock"; + reg = <0x13200 0x100>; + #clock-cells = <1>; + }; + pinctrl_nb: pinctrl-nb@13800 { compatible = "marvell,armada3710-nb-pinctrl", "syscon", "simple-mfd"; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index cdfa052c16..a40c8e5c8f 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -80,5 +80,6 @@ source "drivers/clk/uniphier/Kconfig" source "drivers/clk/exynos/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/mvebu/Kconfig" endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index dab106ab7f..094bcf5847 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -11,6 +11,7 @@ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_CLK_AT91) += at91/ +obj-$(CONFIG_CLK_MVEBU) += mvebu/ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig new file mode 100644 index 0000000000..e776a15e7b --- /dev/null +++ b/drivers/clk/mvebu/Kconfig @@ -0,0 +1,11 @@ +config CLK_MVEBU + bool "MVEBU clock drivers" + depends on CLK && ARCH_MVEBU + help + Enable support for clock present on Marvell MVEBU SoCs. + +config CLK_ARMADA_3720 + bool "Marvell Armada 3720 clock driver" + depends on CLK_MVEBU && ARM64 + help + Enable this to support the clocks on Marvell Armada 3720 SoC. diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile new file mode 100644 index 0000000000..7f80313203 --- /dev/null +++ b/drivers/clk/mvebu/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_CLK_ARMADA_3720) += armada-37xx-periph.o armada-37xx-tbg.o diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c new file mode 100644 index 0000000000..94eabe5f19 --- /dev/null +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -0,0 +1,464 @@ +/* + * Marvell Armada 37xx SoC Peripheral clocks + * + * Marek Behun + * + * Based on Linux driver by: + * Gregory CLEMENT + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TBG_SEL 0x0 +#define DIV_SEL0 0x4 +#define DIV_SEL1 0x8 +#define DIV_SEL2 0xC +#define CLK_SEL 0x10 +#define CLK_DIS 0x14 + +enum a37xx_periph_parent { + TBG_A_P = 0, + TBG_B_P = 1, + TBG_A_S = 2, + TBG_B_S = 3, + MAX_TBG_PARENTS = 4, + XTAL = 4, + MAX_PARENTS = 5, +}; + +static const struct { + const char *name; + enum a37xx_periph_parent parent; +} a37xx_periph_parent_names[] = { + { "TBG-A-P", TBG_A_P }, + { "TBG-B-P", TBG_B_P }, + { "TBG-A-S", TBG_A_S }, + { "TBG-B-S", TBG_B_S }, + { "xtal" , XTAL }, +}; + +struct clk_periph; + +struct a37xx_periphclk { + void __iomem *reg; + + ulong parents[MAX_PARENTS]; + + const struct clk_periph *clks; + bool clk_has_periph_parent[16]; + int clk_parent[16]; + + int count; +}; + +struct clk_div_table { + u32 div; + u32 val; +}; + +struct clk_periph { + const char *name; + + const char *parent_name; + + u32 disable_bit; + int mux_shift; + + const struct clk_div_table *div_table[2]; + s32 div_reg_off[2]; + u32 div_mask[2]; + int div_shift[2]; + + unsigned can_gate : 1; + unsigned can_mux : 1; + unsigned dividers : 2; +}; + +static const struct clk_div_table div_table1[] = { + { 1, 1 }, + { 2, 2 }, + { 0, 0 }, +}; + +static const struct clk_div_table div_table2[] = { + { 2, 1 }, + { 4, 2 }, + { 0, 0 }, +}; + +static const struct clk_div_table div_table6[] = { + { 1, 1 }, + { 2, 2 }, + { 3, 3 }, + { 4, 4 }, + { 5, 5 }, + { 6, 6 }, + { 0, 0 }, +}; + +#define CLK_FULL_DD(_n, _d, _mux, _r0, _r1, _s0, _s1) \ + { \ + .name = #_n, \ + .disable_bit = BIT(_d), \ + .mux_shift = _mux, \ + .div_table[0] = div_table6, \ + .div_table[1] = div_table6, \ + .div_reg_off[0] = _r0, \ + .div_reg_off[1] = _r1, \ + .div_shift[0] = _s0, \ + .div_shift[1] = _s1, \ + .div_mask[0] = 7, \ + .div_mask[1] = 7, \ + .can_gate = 1, \ + .can_mux = 1, \ + .dividers = 2, \ + } + +#define CLK_FULL(_n, _d, _mux, _r, _s, _m, _t) \ + { \ + .name = #_n, \ + .disable_bit = BIT(_d), \ + .mux_shift = _mux, \ + .div_table[0] = _t, \ + .div_reg_off[0] = _r, \ + .div_shift[0] = _s, \ + .div_mask[0] = _m, \ + .can_gate = 1, \ + .can_mux = 1, \ + .dividers = 1, \ + } + +#define CLK_GATE_DIV(_n, _d, _r, _s, _m, _t, _p) \ + { \ + .name = #_n, \ + .parent_name = _p, \ + .disable_bit = BIT(_d), \ + .div_table[0] = _t, \ + .div_reg_off[0] = _r, \ + .div_shift[0] = _s, \ + .div_mask[0] = _m, \ + .can_gate = 1, \ + .dividers = 1, \ + } + +#define CLK_GATE(_n, _d, _p) \ + { \ + .name = #_n, \ + .parent_name = _p, \ + .disable_bit = BIT(_d), \ + .can_gate = 1, \ + } + +#define CLK_MUX_DIV(_n, _mux, _r, _s, _m, _t) \ + { \ + .name = #_n, \ + .mux_shift = _mux, \ + .div_table[0] = _t, \ + .div_reg_off[0] = _r, \ + .div_shift[0] = _s, \ + .div_mask[0] = _m, \ + .can_mux = 1, \ + .dividers = 1, \ + } + +#define CLK_MUX_DD(_n, _mux, _r0, _r1, _s0, _s1) \ + { \ + .name = #_n, \ + .mux_shift = _mux, \ + .div_table[0] = div_table6, \ + .div_table[1] = div_table6, \ + .div_reg_off[0] = _r0, \ + .div_reg_off[1] = _r1, \ + .div_shift[0] = _s0, \ + .div_shift[1] = _s1, \ + .div_mask[0] = 7, \ + .div_mask[1] = 7, \ + .can_mux = 1, \ + .dividers = 2, \ + } + +/* NB periph clocks */ +static const struct clk_periph clks_nb[] ={ + CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13), + CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7), + CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0), + CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6), + CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12), + CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, 7, div_table6), + CLK_GATE(avs, 11, "xtal"), + CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24), + CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0), + CLK_GATE(i2c_2, 16, "xtal"), + CLK_GATE(i2c_1, 17, "xtal"), + CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, 1, div_table2, "TBG-A-S"), + CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12), + CLK_FULL(trace, 22, 18, DIV_SEL0, 20, 7, div_table6), + CLK_FULL(counter, 23, 20, DIV_SEL0, 23, 7, div_table6), + CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19), + CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, 7, div_table6), + { }, +}; + +/* SB periph clocks */ +static const struct clk_periph clks_sb[] = { + CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9), + CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21), + CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9), + CLK_GATE(gbe1_50, 0, "gbe_50"), + CLK_GATE(gbe0_50, 1, "gbe_50"), + CLK_GATE(gbe1_125, 2, "gbe_125"), + CLK_GATE(gbe0_125, 3, "gbe_125"), + CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, 1, div_table1, "gbe_core"), + CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, 1, div_table1, "gbe_core"), + CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, 1, div_table1, "gbe_core"), + CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6), + CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12), + CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18), + { }, +}; + +static inline int get_mux(struct a37xx_periphclk *priv, int shift) +{ + return (readl(priv->reg + TBG_SEL) >> shift) & 3; +} + +static ulong periph_clk_get_rate(struct a37xx_periphclk *priv, int id); + +static ulong get_parent_rate(struct a37xx_periphclk *priv, int id) +{ + const struct clk_periph *clk = &priv->clks[id]; + + if (clk->can_mux) { + /* parent is one of TBG clocks */ + int tbg = get_mux(priv, clk->mux_shift); + + return priv->parents[tbg]; + } else if (priv->clk_has_periph_parent[id]) { + /* parent is one of other periph clocks */ + + if (priv->clk_parent[id] >= priv->count) + return -EINVAL; + + return periph_clk_get_rate(priv, priv->clk_parent[id]); + } else { + /* otherwise parent is one of TBGs or XTAL */ + + if (priv->clk_parent[id] >= MAX_PARENTS) + return -EINVAL; + + return priv->parents[priv->clk_parent[id]]; + } +} + +static ulong get_div(struct a37xx_periphclk *priv, + const struct clk_periph *clk, int idx) +{ + const struct clk_div_table *i; + u32 reg; + + reg = readl(priv->reg + clk->div_reg_off[idx]); + reg = (reg >> clk->div_shift[idx]) & clk->div_mask[idx]; + + /* find divisor for register value val */ + for (i = clk->div_table[idx]; i && i->div != 0; ++i) + if (i->val == reg) + return i->div; + + return 0; +} + +static ulong periph_clk_get_rate(struct a37xx_periphclk *priv, int id) +{ + const struct clk_periph *clk = &priv->clks[id]; + ulong rate, div; + int i; + + rate = get_parent_rate(priv, id); + if (rate == -EINVAL) + return -EINVAL; + + /* divide the parent rate by dividers */ + div = 1; + for (i = 0; i < clk->dividers; ++i) + div *= get_div(priv, clk, i); + + if (!div) + return 0; + + return DIV_ROUND_UP(rate, div); + +} + +static ulong armada_37xx_periph_clk_get_rate(struct clk *clk) +{ + struct a37xx_periphclk *priv = dev_get_priv(clk->dev); + + if (clk->id >= priv->count) + return -EINVAL; + + return periph_clk_get_rate(priv, clk->id); +} + +static int periph_clk_enable(struct clk *clk, int enable) +{ + struct a37xx_periphclk *priv = dev_get_priv(clk->dev); + const struct clk_periph *periph_clk = &priv->clks[clk->id]; + + if (clk->id >= priv->count) + return -EINVAL; + + if (!periph_clk->can_gate) + return -ENOTSUPP; + + if (enable) + clrbits_le32(priv->reg + CLK_DIS, periph_clk->disable_bit); + else + setbits_le32(priv->reg + CLK_DIS, periph_clk->disable_bit); + + return 0; +} + +static int armada_37xx_periph_clk_enable(struct clk *clk) +{ + return periph_clk_enable(clk, 1); +} + +static int armada_37xx_periph_clk_disable(struct clk *clk) +{ + return periph_clk_enable(clk, 0); +} + +int armada_37xx_periph_clk_dump(struct udevice *dev) +{ + struct a37xx_periphclk *priv = dev_get_priv(dev); + const struct clk_periph *clks; + int i; + + if (!priv) + return -ENODEV; + + clks = priv->clks; + + for (i = 0; i < priv->count; ++i) + printf(" %s at %lu Hz\n", clks[i].name, + periph_clk_get_rate(priv, i)); + printf("\n"); + + return 0; +} + +static int armada_37xx_periph_clk_probe(struct udevice *dev) +{ + struct a37xx_periphclk *priv = dev_get_priv(dev); + const struct clk_periph *clks; + int ret, i; + + clks = (const struct clk_periph *) dev_get_driver_data(dev); + if (!clks) + return -ENODEV; + + priv->reg = dev_read_addr_ptr(dev); + if (!priv->reg) { + dev_err(dev, "no io address\n"); + return -ENODEV; + } + + /* count clk_periph nodes */ + priv->count = 0; + while (clks[priv->count].name) + priv->count++; + + priv->clks = clks; + + /* assign parent IDs to nodes which have non-NULL parent_name */ + for (i = 0; i < priv->count; ++i) { + int j; + + if (!clks[i].parent_name) + continue; + + /* first try if parent_name is one of TBGs or XTAL */ + for (j = 0; j < MAX_PARENTS; ++j) + if (!strcmp(clks[i].parent_name, + a37xx_periph_parent_names[j].name)) + break; + + if (j < MAX_PARENTS) { + priv->clk_has_periph_parent[i] = false; + priv->clk_parent[i] = + a37xx_periph_parent_names[j].parent; + continue; + } + + /* else parent_name should be one of other periph clocks */ + for (j = 0; j < priv->count; ++j) { + if (!strcmp(clks[i].parent_name, clks[j].name)) + break; + } + + if (j < priv->count) { + priv->clk_has_periph_parent[i] = true; + priv->clk_parent[i] = j; + continue; + } + + dev_err(dev, "undefined parent %s\n", clks[i].parent_name); + return -EINVAL; + } + + for (i = 0; i < MAX_PARENTS; ++i) { + struct clk clk; + + if (i == XTAL) { + priv->parents[i] = get_ref_clk() * 1000000; + continue; + } + + ret = clk_get_by_index(dev, i, &clk); + if (ret) { + dev_err(dev, "one of parent clocks (%i) missing: %i\n", + i, ret); + return -ENODEV; + } + + priv->parents[i] = clk_get_rate(&clk); + clk_free(&clk); + } + + return 0; +} + +static const struct clk_ops armada_37xx_periph_clk_ops = { + .get_rate = armada_37xx_periph_clk_get_rate, + .enable = armada_37xx_periph_clk_enable, + .disable = armada_37xx_periph_clk_disable, +}; + +static const struct udevice_id armada_37xx_periph_clk_ids[] = { + { + .compatible = "marvell,armada-3700-periph-clock-nb", + .data = (ulong) clks_nb, + }, + { + .compatible = "marvell,armada-3700-periph-clock-sb", + .data = (ulong) clks_sb, + }, + {} +}; + +U_BOOT_DRIVER(armada_37xx_periph_clk) = { + .name = "armada_37xx_periph_clk", + .id = UCLASS_CLK, + .of_match = armada_37xx_periph_clk_ids, + .ops = &armada_37xx_periph_clk_ops, + .priv_auto_alloc_size = sizeof(struct a37xx_periphclk), + .probe = armada_37xx_periph_clk_probe, +}; diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c new file mode 100644 index 0000000000..e8c654f1a6 --- /dev/null +++ b/drivers/clk/mvebu/armada-37xx-tbg.c @@ -0,0 +1,153 @@ +/* + * Marvell Armada 37xx SoC Time Base Generator clocks + * + * Marek Behun + * + * Based on Linux driver by: + * Gregory CLEMENT + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define NUM_TBG 4 + +#define TBG_CTRL0 0x4 +#define TBG_CTRL1 0x8 +#define TBG_CTRL7 0x20 +#define TBG_CTRL8 0x30 + +#define TBG_DIV_MASK 0x1FF + +#define TBG_A_REFDIV 0 +#define TBG_B_REFDIV 16 + +#define TBG_A_FBDIV 2 +#define TBG_B_FBDIV 18 + +#define TBG_A_VCODIV_SE 0 +#define TBG_B_VCODIV_SE 16 + +#define TBG_A_VCODIV_DIFF 1 +#define TBG_B_VCODIV_DIFF 17 + +struct tbg_def { + const char *name; + u32 refdiv_offset; + u32 fbdiv_offset; + u32 vcodiv_reg; + u32 vcodiv_offset; +}; + +static const struct tbg_def tbg[NUM_TBG] = { + {"TBG-A-P", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL8, TBG_A_VCODIV_DIFF}, + {"TBG-B-P", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL8, TBG_B_VCODIV_DIFF}, + {"TBG-A-S", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL1, TBG_A_VCODIV_SE}, + {"TBG-B-S", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL1, TBG_B_VCODIV_SE}, +}; + +struct a37xx_tbgclk { + ulong rates[NUM_TBG]; + unsigned int mult[NUM_TBG]; + unsigned int div[NUM_TBG]; +}; + +static unsigned int tbg_get_mult(void __iomem *reg, const struct tbg_def *ptbg) +{ + u32 val; + + val = readl(reg + TBG_CTRL0); + + return ((val >> ptbg->fbdiv_offset) & TBG_DIV_MASK) << 2; +} + +static unsigned int tbg_get_div(void __iomem *reg, const struct tbg_def *ptbg) +{ + u32 val; + unsigned int div; + + val = readl(reg + TBG_CTRL7); + + div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK; + if (div == 0) + div = 1; + val = readl(reg + ptbg->vcodiv_reg); + + div *= 1 << ((val >> ptbg->vcodiv_offset) & TBG_DIV_MASK); + + return div; +} + +static ulong armada_37xx_tbg_clk_get_rate(struct clk *clk) +{ + struct a37xx_tbgclk *priv = dev_get_priv(clk->dev); + + if (clk->id >= NUM_TBG) + return -ENODEV; + + return priv->rates[clk->id]; +} + +int armada_37xx_tbg_clk_dump(struct udevice *dev) +{ + struct a37xx_tbgclk *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < NUM_TBG; ++i) + printf(" %s at %lu Hz\n", tbg[i].name, + priv->rates[i]); + printf("\n"); + + return 0; +} + +static int armada_37xx_tbg_clk_probe(struct udevice *dev) +{ + struct a37xx_tbgclk *priv = dev_get_priv(dev); + void __iomem *reg; + ulong xtal; + int i; + + reg = dev_read_addr_ptr(dev); + if (!reg) { + dev_err(dev, "no io address\n"); + return -ENODEV; + } + + xtal = (ulong) get_ref_clk() * 1000000; + + for (i = 0; i < NUM_TBG; ++i) { + unsigned int mult, div; + + mult = tbg_get_mult(reg, &tbg[i]); + div = tbg_get_div(reg, &tbg[i]); + + priv->rates[i] = (xtal * mult) / div; + } + + return 0; +} + +static const struct clk_ops armada_37xx_tbg_clk_ops = { + .get_rate = armada_37xx_tbg_clk_get_rate, +}; + +static const struct udevice_id armada_37xx_tbg_clk_ids[] = { + { .compatible = "marvell,armada-3700-tbg-clock" }, + {} +}; + +U_BOOT_DRIVER(armada_37xx_tbg_clk) = { + .name = "armada_37xx_tbg_clk", + .id = UCLASS_CLK, + .of_match = armada_37xx_tbg_clk_ids, + .ops = &armada_37xx_tbg_clk_ops, + .priv_auto_alloc_size = sizeof(struct a37xx_tbgclk), + .probe = armada_37xx_tbg_clk_probe, +}; From patchwork Wed Mar 7 21:52:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882826 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="sC4Vc35Z"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSMF0C5Nz9s8v for ; Thu, 8 Mar 2018 09:03:20 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BB931C21F2F; Wed, 7 Mar 2018 22:00:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 66096C22038; Wed, 7 Mar 2018 21:55:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9DAD2C21E62; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 11B6CC21E57 for ; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id C3F54626BA; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=Zsco0dZgzakqQsxVbblTTpzZbhCncFoRTfMf9aBm4bk=; h=From:To:Date; b=sC4Vc35ZGaAUfCdEd5RKm8lgBqiAuBNBuO0kkszilH0BM7C1Tp28hQls6jSVYGaLo 9S7DT6TuXVoGAbzcS5/7LwOegDcM7a2a5m2xpja7ZQK6gQpcbCqSdwn2JdgxyLIcEb hItLgWV5j8Uwr7BuRTItAVCe+JEgHF7qKbieDBko= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:12 +0100 Message-Id: <20180307215216.10418-16-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 15/19] spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequency X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Since now we have driver for clocks on Armada 37xx, use it to determine SQF clock frequency for the SPI driver. Also change the default config files for Armada 37xx devices so that the clock driver is enabled by default, otherwise the SPI driver cannot be enabled. Signed-off-by: Marek Behun --- arch/arm/dts/armada-37xx.dtsi | 4 +-- configs/mvebu_db-88f3720_defconfig | 3 ++ configs/mvebu_espressobin-88f3720_defconfig | 3 ++ drivers/spi/Kconfig | 1 + drivers/spi/mvebu_a3700_spi.c | 52 ++++++++++++++++------------- 5 files changed, 37 insertions(+), 26 deletions(-) diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index e848812fca..c254c0aded 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -281,8 +281,8 @@ #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; - clock-frequency = <160000>; - spi-max-frequency = <40000>; + spi-max-frequency = <50000000>; + clocks = <&nb_periph_clk 7>; status = "disabled"; }; diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 338d764d84..c8ca06e428 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -33,6 +33,9 @@ CONFIG_DM_GPIO=y # CONFIG_MVEBU_GPIO is not set CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_CLK=y +CONFIG_CLK_MVEBU=y +CONFIG_CLK_ARMADA_3720=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 28005e6131..5f449d34ea 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -30,6 +30,9 @@ CONFIG_SCSI_AHCI=y CONFIG_BLOCK_CACHE=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_CLK=y +CONFIG_CLK_MVEBU=y +CONFIG_CLK_ARMADA_3720=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 235a8c7d73..4ea94a5f35 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -94,6 +94,7 @@ config ICH_SPI config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" + depends on CLK_ARMADA_3720 help Enable the Marvell Armada 3700 SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c index d1708a8d56..19e854945b 100644 --- a/drivers/spi/mvebu_a3700_spi.c +++ b/drivers/spi/mvebu_a3700_spi.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -22,9 +23,8 @@ DECLARE_GLOBAL_DATA_PTR; #define MVEBU_SPI_A3700_CLK_POL BIT(7) #define MVEBU_SPI_A3700_FIFO_EN BIT(17) #define MVEBU_SPI_A3700_SPI_EN_0 BIT(16) -#define MVEBU_SPI_A3700_CLK_PRESCALE_BIT 0 -#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK \ - (0x1f << MVEBU_SPI_A3700_CLK_PRESCALE_BIT) +#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK 0x1f + /* SPI registers */ struct spi_reg { @@ -36,8 +36,7 @@ struct spi_reg { struct mvebu_spi_platdata { struct spi_reg *spireg; - unsigned int frequency; - unsigned int clock; + struct clk clk; }; static void spi_cs_activate(struct spi_reg *reg, int cs) @@ -178,17 +177,18 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); struct spi_reg *reg = plat->spireg; - u32 data; + u32 data, prescale; data = readl(®->cfg); - /* Set Prescaler */ - data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK; + prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz); + if (prescale > 31) + prescale = 0x1f; + else if (prescale > 15) + prescale = 0x10 + (prescale + 1)/2; - /* Calculate Prescaler = (spi_input_freq / spi_max_freq) */ - if (hz > plat->frequency) - hz = plat->frequency; - data |= plat->clock / hz; + data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK; + data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK; writel(data, ®->cfg); @@ -252,21 +252,24 @@ static int mvebu_spi_probe(struct udevice *bus) static int mvebu_spi_ofdata_to_platdata(struct udevice *bus) { struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + int ret; plat->spireg = (struct spi_reg *)devfdt_get_addr(bus); - /* - * FIXME - * Right now, mvebu does not have a clock infrastructure in U-Boot - * which should be used to query the input clock to the SPI - * controller. Once this clock driver is integrated into U-Boot - * it should be used to read the input clock and the DT property - * can be removed. - */ - plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), - "clock-frequency", 160000); - plat->frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), - "spi-max-frequency", 40000); + ret = clk_get_by_index(bus, 0, &plat->clk); + if (ret) { + dev_err(bus, "cannot get clock\n"); + return ret; + } + + return 0; +} + +static int mvebu_spi_remove(struct udevice *bus) +{ + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + + clk_free(&plat->clk); return 0; } @@ -294,4 +297,5 @@ U_BOOT_DRIVER(mvebu_spi) = { .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata), .probe = mvebu_spi_probe, + .remove = mvebu_spi_remove, }; From patchwork Wed Mar 7 21:52:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882825 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="URpWZHdP"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSM46ZZJz9s8v for ; Thu, 8 Mar 2018 09:03:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 93C21C21F81; Wed, 7 Mar 2018 22:00:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A0317C21C4A; Wed, 7 Mar 2018 21:55:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7E6C7C21E5B; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 22394C21DB6 for ; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id D60EB626C2; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=NjrZ48/wOFFlAvTg8wwvV/0+tnJNUvOsBPOZheWRzA0=; h=From:To:Date; b=URpWZHdPZ1pbQkxTMCZHP56IO2ftnR1lMKPvnYg9aIQnQ+G8VboiSC8JeC2JlcUuI ZqP3fArqqWWtsHsAZUmpVvzNt9LVBTUdX+yMMEIgdu3oQVskdvBw93R4X3AP8RryAu cQwnRvBsGyvYusdIrX2TvHXNoscz7BiohbQA/wDA= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:13 +0100 Message-Id: <20180307215216.10418-17-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 16/19] clk: armada-37xx: Support soc_clk_dump X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add support for the clk dump command on Armada 37xx. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/clk/mvebu/armada-37xx-periph.c | 36 +++++++++++++++++++++++++++++++++- drivers/clk/mvebu/armada-37xx-tbg.c | 2 ++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index 94eabe5f19..b53521bb9f 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -336,7 +336,8 @@ static int armada_37xx_periph_clk_disable(struct clk *clk) return periph_clk_enable(clk, 0); } -int armada_37xx_periph_clk_dump(struct udevice *dev) +#if defined(CONFIG_CMD_CLK) && defined(CONFIG_CLK_ARMADA_3720) +static int armada_37xx_periph_clk_dump(struct udevice *dev) { struct a37xx_periphclk *priv = dev_get_priv(dev); const struct clk_periph *clks; @@ -355,6 +356,39 @@ int armada_37xx_periph_clk_dump(struct udevice *dev) return 0; } +static int clk_dump(const char *name, int (*func)(struct udevice *)) +{ + struct udevice *dev; + + if (uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { + printf("Cannot find device %s\n", name); + return -ENODEV; + } + + return func(dev); +} + +int armada_37xx_tbg_clk_dump(struct udevice *); + +int soc_clk_dump(void) +{ + printf(" xtal at %u000000 Hz\n\n", get_ref_clk()); + + if (clk_dump("tbg@13200", armada_37xx_tbg_clk_dump)) + return 1; + + if (clk_dump("nb-periph-clk@13000", + armada_37xx_periph_clk_dump)) + return 1; + + if (clk_dump("sb-periph-clk@18000", + armada_37xx_periph_clk_dump)) + return 1; + + return 0; +} +#endif + static int armada_37xx_periph_clk_probe(struct udevice *dev) { struct a37xx_periphclk *priv = dev_get_priv(dev); diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c index e8c654f1a6..3107d94494 100644 --- a/drivers/clk/mvebu/armada-37xx-tbg.c +++ b/drivers/clk/mvebu/armada-37xx-tbg.c @@ -94,6 +94,7 @@ static ulong armada_37xx_tbg_clk_get_rate(struct clk *clk) return priv->rates[clk->id]; } +#if defined(CONFIG_CMD_CLK) && defined(CONFIG_CLK_ARMADA_3720) int armada_37xx_tbg_clk_dump(struct udevice *dev) { struct a37xx_tbgclk *priv = dev_get_priv(dev); @@ -106,6 +107,7 @@ int armada_37xx_tbg_clk_dump(struct udevice *dev) return 0; } +#endif static int armada_37xx_tbg_clk_probe(struct udevice *dev) { From patchwork Wed Mar 7 21:52:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882829 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="Dgoz61gz"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSNG0RMTz9sgt for ; Thu, 8 Mar 2018 09:04:14 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C71E5C21F07; Wed, 7 Mar 2018 22:01:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D74F7C22051; Wed, 7 Mar 2018 21:55:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1FC1AC21BE5; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 31CCEC21E5B for ; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id E701A626C4; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=CIYorC7Kt5hEpF1AnqPF66UKriuJAZXqE+D4GJa+KmI=; h=From:To:Date; b=Dgoz61gzS92W/y8tyoj408oht0NgSfYM0+wOxOOIhuvNRguSzrCre6y12AlwQzmrU iBvQax4aw8SuFsoUdXDh3XZH5p41MxbrgTtuXXMq4pITt9g6/VjOZ5tdJCLJaPjDEk Y9EwA+ZF5UImnG2nYU79k5U49BBDtYeS+CFhF3jI= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:14 +0100 Message-Id: <20180307215216.10418-18-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 17/19] pinctrl: armada-37xx: Fix SB pinctrl groups according to new revision X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The groups pcie1, ptp and mii changed in new revision (from 2016). Also smi was added to support enabling the MDIO pins. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 2bf853eba1..8913e25c55 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -174,11 +174,12 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"), PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"), - PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"), - PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"), + PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), + PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"), + PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), - PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"), + PIN_GRP("mii_col", 23, 1, BIT(8) | BIT(14), "mii", "mii_err"), }; const struct armada_37xx_pin_data armada_37xx_pin_nb = { From patchwork Wed Mar 7 21:52:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882830 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="Seghc4EI"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSNQ6s6qz9s8v for ; Thu, 8 Mar 2018 09:04:22 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A5566C21F48; Wed, 7 Mar 2018 22:02:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B9102C2205D; Wed, 7 Mar 2018 21:55:29 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 70566C21FAB; Wed, 7 Mar 2018 21:55:19 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 455F2C21E52 for ; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 02191626C9; Wed, 7 Mar 2018 22:55:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459704; bh=TfyfOdoScsRdDsqmgRKkllosbZwzhCCG1dXY9vdo5gM=; h=From:To:Date; b=Seghc4EIwRrmP7U2aKKO0iG9kNKWrVhemsTeDKjcqmwEZLOmcACMZPJA0vRzNAxsK FFutMv3brKzf5zjlBPtu91IOaYKWCpb0KwsZPvNFOwcuZSZvKSaawA0w2CpfQDfkYB Fm8IyZEBNmTlRUzUED//6Dbq0jyzVt+g2YpwZG/E= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:15 +0100 Message-Id: <20180307215216.10418-19-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 18/19] phy: marvell: core: Cosmetic fixes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move the reg_set* functions into comphy.h as static inline functions. Change return type of get_*_string to const char *. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy.h | 41 ++++++++++++++++++++++--- drivers/phy/marvell/comphy_core.c | 64 +++++++++------------------------------ 2 files changed, 52 insertions(+), 53 deletions(-) diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h index 32e0a1e652..176bc89cac 100644 --- a/drivers/phy/marvell/comphy.h +++ b/drivers/phy/marvell/comphy.h @@ -102,10 +102,43 @@ struct chip_serdes_phy_config { }; /* Register helper functions */ -void reg_set(void __iomem *addr, u32 data, u32 mask); -void reg_set_silent(void __iomem *addr, u32 data, u32 mask); -void reg_set16(void __iomem *addr, u16 data, u16 mask); -void reg_set_silent16(void __iomem *addr, u16 data, u16 mask); +static inline void reg_set_silent(void __iomem *addr, u32 data, u32 mask) +{ + u32 reg_data; + + reg_data = readl(addr); + reg_data &= ~mask; + reg_data |= data; + writel(reg_data, addr); +} + +static inline void reg_set(void __iomem *addr, u32 data, u32 mask) +{ + debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ", + (unsigned long)addr, data, mask); + debug("old value = %#010x ==> ", readl(addr)); + reg_set_silent(addr, data, mask); + debug("new value %#010x\n", readl(addr)); +} + +static inline void reg_set_silent16(void __iomem *addr, u16 data, u16 mask) +{ + u16 reg_data; + + reg_data = readw(addr); + reg_data &= ~mask; + reg_data |= data; + writew(reg_data, addr); +} + +static inline void reg_set16(void __iomem *addr, u16 data, u16 mask) +{ + debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ", + (unsigned long)addr, data, mask); + debug("old value = %#06x ==> ", readw(addr)); + reg_set_silent16(addr, data, mask); + debug("new value %#06x\n", readw(addr)); +} /* SoC specific init functions */ #ifdef CONFIG_ARMADA_3700 diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 1e5664c435..b2fe9fca0a 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -18,11 +18,13 @@ DECLARE_GLOBAL_DATA_PTR; -static char *get_speed_string(u32 speed) +static const char *get_speed_string(u32 speed) { - char *speed_strings[] = {"1.25 Gbps", "1.5 Gbps", "2.5 Gbps", - "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps", - "6.25 Gbps", "10.31 Gbps" }; + const char *speed_strings[] = { + "1.25 Gbps", "1.5 Gbps", "2.5 Gbps", + "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps", + "6.25 Gbps", "10.31 Gbps" + }; if (speed < 0 || speed > PHY_SPEED_MAX) return "invalid"; @@ -30,14 +32,16 @@ static char *get_speed_string(u32 speed) return speed_strings[speed]; } -static char *get_type_string(u32 type) +static const char *get_type_string(u32 type) { - char *type_strings[] = {"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3", - "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0", - "SGMII1", "SGMII2", "SGMII3", "QSGMII", - "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", - "XAUI0", "XAUI1", "XAUI2", "XAUI3", - "RXAUI0", "RXAUI1", "SFI", "IGNORE"}; + const char *type_strings[] = { + "UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3", + "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0", + "SGMII1", "SGMII2", "SGMII3", "QSGMII", + "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", + "XAUI0", "XAUI1", "XAUI2", "XAUI3", + "RXAUI0", "RXAUI1", "SFI", "IGNORE" + }; if (type < 0 || type > PHY_TYPE_MAX) return "invalid"; @@ -45,44 +49,6 @@ static char *get_type_string(u32 type) return type_strings[type]; } -void reg_set(void __iomem *addr, u32 data, u32 mask) -{ - debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ", - (unsigned long)addr, data, mask); - debug("old value = %#010x ==> ", readl(addr)); - reg_set_silent(addr, data, mask); - debug("new value %#010x\n", readl(addr)); -} - -void reg_set_silent(void __iomem *addr, u32 data, u32 mask) -{ - u32 reg_data; - - reg_data = readl(addr); - reg_data &= ~mask; - reg_data |= data; - writel(reg_data, addr); -} - -void reg_set16(void __iomem *addr, u16 data, u16 mask) -{ - debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ", - (unsigned long)addr, data, mask); - debug("old value = %#06x ==> ", readw(addr)); - reg_set_silent16(addr, data, mask); - debug("new value %#06x\n", readw(addr)); -} - -void reg_set_silent16(void __iomem *addr, u16 data, u16 mask) -{ - u16 reg_data; - - reg_data = readw(addr); - reg_data &= ~mask; - reg_data |= data; - writew(reg_data, addr); -} - void comphy_print(struct chip_serdes_phy_config *chip_cfg, struct comphy_map *comphy_map_data) { From patchwork Wed Mar 7 21:52:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882821 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="lVniUTKr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSJT2yqNz9sgy for ; Thu, 8 Mar 2018 09:00:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0231DC21E79; Wed, 7 Mar 2018 22:00:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C1CBEC22014; Wed, 7 Mar 2018 21:55:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6716EC21E3B; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 54F6FC21E3B for ; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 154B3626D6; Wed, 7 Mar 2018 22:55:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459704; bh=Bw8d8LXnCC+CioBunCmrOgFPwMruqAQR6OSefw+xaC0=; h=From:To:Date; b=lVniUTKr5w15sOibxS7SagPg4fuofI7TAICu8RcJ0t61dR3jAAh3PlNJaZiV8bskJ /f5OcnQxJncYv0CPnHuAjSzZp2xIkJ0JcDns6Zm+vZ9o0NC7Ie5Atri5QRthAwcCHo KDGjGOkaQKyLVZ/gewNCxOCke0bRcXbJDHCSZgoo= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:16 +0100 Message-Id: <20180307215216.10418-20-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 19/19] net: mvneta: Fix fault when wrong device tree X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The driver does not check id phy_connect failed (for example on wrong property name in device tree). In such a case a fault occurs and the CPU is restarted. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/net/mvneta.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 83e3153768..7403ccbd3c 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -1554,6 +1554,10 @@ static int mvneta_start(struct udevice *dev) phydev = phy_connect(pp->bus, pp->phyaddr, dev, pp->phy_interface); + if (!phydev) { + printf("phy_connect failed\n"); + return -1; + } pp->phydev = phydev; phy_config(phydev);