From patchwork Wed Mar 7 20:43:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 882786 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=eik.bme.hu Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zxQrJ6l76z9sdq for ; Thu, 8 Mar 2018 07:54:55 +1100 (AEDT) Received: from localhost ([::1]:35576 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1etg5M-0004fI-Rn for incoming@patchwork.ozlabs.org; Wed, 07 Mar 2018 15:54:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54628) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1etg53-0004cV-58 for qemu-devel@nongnu.org; Wed, 07 Mar 2018 15:54:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1etg50-0007HE-13 for qemu-devel@nongnu.org; Wed, 07 Mar 2018 15:54:33 -0500 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:11370) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1etg4z-0007Gs-Pz; Wed, 07 Mar 2018 15:54:29 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 552917456D7; Wed, 7 Mar 2018 21:54:27 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 3A2877456C6; Wed, 7 Mar 2018 21:54:27 +0100 (CET) From: BALATON Zoltan Date: Wed, 7 Mar 2018 21:43:59 +0100 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Message-Id: <20180307205427.3A2877456C6@zero.eik.bme.hu> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH] ppc440_pcix: Add dummy implementation of BRDGOPT registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" I don't know what should be the correct implementation for these so these are just stored and returned as is without doing anything for now only to silence warnings when u-boot accesses these registers. Signed-off-by: BALATON Zoltan Reviewed-by: Thomas Huth --- hw/ppc/ppc440_pcix.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c index ab2626a..3f177d3 100644 --- a/hw/ppc/ppc440_pcix.c +++ b/hw/ppc/ppc440_pcix.c @@ -55,6 +55,8 @@ typedef struct PPC440PCIXState { PCIDevice *dev; struct PLBOutMap pom[PPC440_PCIX_NR_POMS]; struct PLBInMap pim[PPC440_PCIX_NR_PIMS]; + uint32_t brdgopt1; + uint32_t brdgopt2; uint32_t sts; qemu_irq irq[PCI_NUM_PINS]; AddressSpace bm_as; @@ -95,6 +97,8 @@ typedef struct PPC440PCIXState { #define PCIX0_PIM0SAH 0xf8 #define PCIX0_PIM2SAH 0xfc +#define PCIX0_BRDGOPT1 0x40 +#define PCIX0_BRDGOPT2 0x44 #define PCIX0_STS 0xe0 #define PCI_ALL_SIZE (PPC440_REG_BASE + PPC440_REG_SIZE) @@ -270,6 +274,12 @@ static void ppc440_pcix_reg_write4(void *opaque, hwaddr addr, ppc440_pcix_update_pim(s, 2); break; + case PCIX0_BRDGOPT1: + s->brdgopt1 = val; + break; + case PCIX0_BRDGOPT2: + s->brdgopt2 = val; + break; case PCIX0_STS: s->sts = val; break; @@ -365,6 +375,12 @@ static uint64_t ppc440_pcix_reg_read4(void *opaque, hwaddr addr, val = s->pim[2].la >> 32; break; + case PCIX0_BRDGOPT1: + val = s->brdgopt1; + break; + case PCIX0_BRDGOPT2: + val = s->brdgopt2; + break; case PCIX0_STS: val = s->sts; break; @@ -408,6 +424,8 @@ static void ppc440_pcix_reset(DeviceState *dev) for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) { s->pim[i].sa = 0xffffffff00000000ULL; } + s->brdgopt1 = 0; + s->brdgopt2 = 0; s->sts = 0; }