From patchwork Wed Oct 12 08:26:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Zhong X-Patchwork-Id: 1689065 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=gxxff5ka; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MnQmh2r3Fz23jX for ; Wed, 12 Oct 2022 19:29:24 +1100 (AEDT) Received: from localhost ([::1]:40742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oiX7C-0000Rt-4z for incoming@patchwork.ozlabs.org; Wed, 12 Oct 2022 04:29:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oiX4Y-0007dU-Vn for qemu-devel@nongnu.org; Wed, 12 Oct 2022 04:26:39 -0400 Received: from mga18.intel.com ([134.134.136.126]:15814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oiX4V-0003ZI-KE for qemu-devel@nongnu.org; Wed, 12 Oct 2022 04:26:38 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665563195; x=1697099195; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=fv5pzCMFah14N76NZnLkhaoomaR/jmWxzAJexkibh/0=; b=gxxff5kayof0zaMkyqtjcI7jGPISpe2Icj5x/R0KaVtypq/tKoYfh8Du wljgbq+ExU1Qc3Kj1UB5gGSV9bqQ3BD8XZWa53U1+ofOWKnaJ530Jbnq/ at7mbcOlek936sg7XEoiamRiuXioC8cMZ97uWu8/MP6L9b50a0RBtNfLy KXSgV8FqU6ZE21O1UP2ZZintbOvLzKQkF+ZINwm182ffT1q7vsyXxsZGu IAdfr8EQ4qfrfiQDaBWO10JxP71bI2dpurxZwWzbasqhvWXxFzt74clPV iIBwSpSy/+rcyA9rxz4mu7ULY6gm8TfQ2PvWSkrsnGe/JJ6RUAAV+PoZY Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="288002210" X-IronPort-AV: E=Sophos;i="5.95,178,1661842800"; d="scan'208";a="288002210" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2022 01:26:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="731332114" X-IronPort-AV: E=Sophos;i="5.95,178,1661842800"; d="scan'208";a="731332114" Received: from icx.bj.intel.com ([10.240.192.136]) by fmsmga002.fm.intel.com with ESMTP; 12 Oct 2022 01:26:30 -0700 From: Yang Zhong To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, weijiang.yang@intel.com, yang.zhong@linux.intel.com, Yang Zhong Subject: [PATCH] target/i386: Switch back XFRM value Date: Wed, 12 Oct 2022 04:26:09 -0400 Message-Id: <20221012082609.922631-1-yang.zhong@intel.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.126; envelope-from=yang.zhong@intel.com; helo=mga18.intel.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):ECX, which made SGX enclave only supported SSE and x87 feature(xfrm=0x3). Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features") Signed-off-by: Yang Zhong Reviewed-by: Kai Huang --- target/i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ad623d91e4..19aaed877b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } else { *eax &= env->features[FEAT_SGX_12_1_EAX]; *ebx &= 0; /* ebx reserve */ - *ecx &= env->features[FEAT_XSAVE_XSS_LO]; - *edx &= env->features[FEAT_XSAVE_XSS_HI]; + *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; + *edx &= env->features[FEAT_XSAVE_XCR0_HI]; /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;