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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 08:45:17.4963 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f52aaafa-f116-4c67-fe93-08da9c76c67a X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT060.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR02MB9066 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam Added standard mode for AXI I2C controller to enable read transfers of size more than 255 bytes. The driver selects standard mode in the following scenarios. 1. If a single message request comes from user space, requesting a read of more than 255 bytes 2. If a message set request comes from user space consisting of many messages and if any one of them is a read operation, irrespective of the size of transfer. (This is done because it is observed that repeated start operation is not happening in dynamic mode read as expected in a message set request from user space.) Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- Changes for v2: Merged the logic of xiic_std_fill_tx_fifo into xiic_fill_tx_fifo to remove duplicate code. Handled i2c msg->len == 0 case. Squashed "Use 'nmsgs' variable instead of repeated_start" patch. Squashed "Correct the BNB interrupt enable sequence" patch. Squashed "remove unsupported flag I2C_M_NOSTART code" patch. --- drivers/i2c/busses/i2c-xiic.c | 266 ++++++++++++++++++++++++++++------ 1 file changed, 225 insertions(+), 41 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index b3fe6b2aa3ca..2aa43e067fee 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -60,6 +60,7 @@ enum xiic_endian { * @clk: Pointer to AXI4-lite input clock * @state: See STATE_ * @singlemaster: Indicates bus is single master + * @dynamic: Mode of controller */ struct xiic_i2c { struct device *dev; @@ -76,6 +77,7 @@ struct xiic_i2c { struct clk *clk; enum xilinx_i2c_state state; bool singlemaster; + bool dynamic; }; #define XIIC_MSB_OFFSET 0 @@ -143,6 +145,9 @@ struct xiic_i2c { #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ +/* Dynamic mode constants */ +#define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */ + /* * The following constants define the register offsets for the Interrupt * registers. There are some holes in the memory map for reserved addresses @@ -316,13 +321,14 @@ static void xiic_deinit(struct xiic_i2c *i2c) static void xiic_read_rx(struct xiic_i2c *i2c) { - u8 bytes_in_fifo; + u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; + u32 bytes_rem = 0; int i; bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; dev_dbg(i2c->adap.dev.parent, - "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", + "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n", __func__, bytes_in_fifo, xiic_rx_space(i2c), xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); @@ -330,13 +336,52 @@ static void xiic_read_rx(struct xiic_i2c *i2c) if (bytes_in_fifo > xiic_rx_space(i2c)) bytes_in_fifo = xiic_rx_space(i2c); - for (i = 0; i < bytes_in_fifo; i++) + bytes_to_read = bytes_in_fifo; + + if (!i2c->dynamic) { + bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; + + if (bytes_rem > IIC_RX_FIFO_DEPTH) { + bytes_to_read = bytes_in_fifo; + } else if (bytes_rem > 1) { + bytes_to_read = bytes_rem - 1; + } else if (bytes_rem == 1) { + bytes_to_read = 1; + /* Set NACK in CR to indicate slave transmitter */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | + XIIC_CR_NO_ACK_MASK); + } else if (bytes_rem == 0) { + bytes_to_read = bytes_in_fifo; + + /* Generate stop on the bus if it is last message */ + if (i2c->nmsgs == 1) { + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & + ~XIIC_CR_MSMS_MASK); + } + + /* Make TXACK=0, clean up for next transaction */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & + ~XIIC_CR_NO_ACK_MASK); + } + } + + /* Read the fifo */ + for (i = 0; i < bytes_to_read; i++) { i2c->rx_msg->buf[i2c->rx_pos++] = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); + } - xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, - (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? - IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); + if (i2c->dynamic) { + u8 bytes; + + /* Receive remaining bytes if less than fifo depth */ + bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH); + bytes--; + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); + } } static int xiic_tx_fifo_space(struct xiic_i2c *i2c) @@ -360,7 +405,15 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { /* last message in transfer -> STOP */ - data |= XIIC_TX_DYN_STOP_MASK; + if (i2c->dynamic) { + data |= XIIC_TX_DYN_STOP_MASK; + } else { + u8 cr; + /* Write to CR to stop */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & + ~XIIC_CR_MSMS_MASK); + } dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); } xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); @@ -401,7 +454,9 @@ static irqreturn_t xiic_process(int irq, void *dev_id) dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), i2c->tx_msg, i2c->nmsgs); - + dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n", + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); /* Service requesting interrupt */ if ((pend & XIIC_INTR_ARB_LOST_MASK) || @@ -579,31 +634,101 @@ static int xiic_busy(struct xiic_i2c *i2c) static void xiic_start_recv(struct xiic_i2c *i2c) { u16 rx_watermark; + u8 cr = 0, rfd_set = 0; struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; + unsigned long flags; - /* Clear and enable Rx full interrupt. */ - xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); + dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); - /* we want to get all but last byte, because the TX_ERROR IRQ is used - * to inidicate error ACK on the address, and negative ack on the last - * received byte, so to not mix them receive all but last. - * In the case where there is only one byte to receive - * we can check if ERROR and RX full is set at the same time - */ - rx_watermark = msg->len; - if (rx_watermark > IIC_RX_FIFO_DEPTH) - rx_watermark = IIC_RX_FIFO_DEPTH; - xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, (u8)(rx_watermark - 1)); + /* Disable Tx interrupts */ + xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); + + if (i2c->dynamic) { + u8 bytes; + u16 val; + + /* Clear and enable Rx full interrupt. */ + xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | + XIIC_INTR_TX_ERROR_MASK); + + /* + * We want to get all but last byte, because the TX_ERROR IRQ + * is used to indicate error ACK on the address, and + * negative ack on the last received byte, so to not mix + * them receive all but last. + * In the case where there is only one byte to receive + * we can check if ERROR and RX full is set at the same time + */ + rx_watermark = msg->len; + bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH); + + if (rx_watermark > 0) + bytes--; + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); + + local_irq_save(flags); - if (!(msg->flags & I2C_M_NOSTART)) /* write the address */ xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, - i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); + i2c_8bit_addr_from_msg(msg) | + XIIC_TX_DYN_START_MASK); + + /* If last message, include dynamic stop bit with length */ + val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; + val |= msg->len; + + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); + + xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + + local_irq_restore(flags); + } else { + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + + /* Set Receive fifo depth */ + rx_watermark = msg->len; + if (rx_watermark > IIC_RX_FIFO_DEPTH) { + rfd_set = IIC_RX_FIFO_DEPTH - 1; + } else if (rx_watermark == 1) { + rfd_set = rx_watermark - 1; + /* Handle single byte transfer separately */ + cr |= XIIC_CR_NO_ACK_MASK; + } else if (rx_watermark == 0) { + rfd_set = rx_watermark; + cr |= XIIC_CR_NO_ACK_MASK; + } else { + rfd_set = rx_watermark - 2; + } + /* Check if RSTA should be set */ + if (cr & XIIC_CR_MSMS_MASK) { + /* Already a master, RSTA should be set */ + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | + XIIC_CR_REPEATED_START_MASK) & + ~(XIIC_CR_DIR_IS_TX_MASK)); + } - xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); - xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, - msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); + /* Clear and enable Rx full and transmit complete interrupts */ + xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | + XIIC_INTR_TX_ERROR_MASK); + + /* Write the address */ + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, + i2c_8bit_addr_from_msg(msg)); + + /* Write to Control Register,to start transaction in Rx mode */ + if ((cr & XIIC_CR_MSMS_MASK) == 0) { + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | + XIIC_CR_MSMS_MASK) + & ~(XIIC_CR_DIR_IS_TX_MASK)); + } + dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); + } if (i2c->nmsgs == 1) /* very last, enable bus not busy as well */ @@ -611,10 +736,15 @@ static void xiic_start_recv(struct xiic_i2c *i2c) /* the message is tx:ed */ i2c->tx_pos = msg->len; + + /* Enable interrupts */ + xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); } static void xiic_start_send(struct xiic_i2c *i2c) { + u8 cr = 0; + u16 data; struct i2c_msg *msg = i2c->tx_msg; dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", @@ -623,24 +753,56 @@ static void xiic_start_send(struct xiic_i2c *i2c) __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); - if (!(msg->flags & I2C_M_NOSTART)) { + if (i2c->dynamic) { /* write the address */ - u16 data = i2c_8bit_addr_from_msg(msg) | - XIIC_TX_DYN_START_MASK; - if ((i2c->nmsgs == 1) && msg->len == 0) + data = i2c_8bit_addr_from_msg(msg) | + XIIC_TX_DYN_START_MASK; + + if (i2c->nmsgs == 1 && msg->len == 0) /* no data and last message -> add STOP */ data |= XIIC_TX_DYN_STOP_MASK; xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); - } - /* Clear any pending Tx empty, Tx Error and then enable them. */ - xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | - XIIC_INTR_BNB_MASK | - ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? - XIIC_INTR_TX_HALF_MASK : 0)); + /* Clear any pending Tx empty, Tx Error and then enable them */ + xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | + XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_BNB_MASK | + ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? + XIIC_INTR_TX_HALF_MASK : 0)); + + xiic_fill_tx_fifo(i2c); + } else { + /* Check if RSTA should be set */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + if (cr & XIIC_CR_MSMS_MASK) { + /* Already a master, RSTA should be set */ + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | + XIIC_CR_REPEATED_START_MASK | + XIIC_CR_DIR_IS_TX_MASK) & + ~(XIIC_CR_NO_ACK_MASK)); + } + + /* Write address to FIFO */ + data = i2c_8bit_addr_from_msg(msg); + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); - xiic_fill_tx_fifo(i2c); + /* Fill fifo */ + xiic_fill_tx_fifo(i2c); + + if ((cr & XIIC_CR_MSMS_MASK) == 0) { + /* Start Tx by writing to CR */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | + XIIC_CR_MSMS_MASK | + XIIC_CR_DIR_IS_TX_MASK); + } + + /* Clear any pending Tx empty, Tx Error and then enable them */ + xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | + XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_BNB_MASK); + } } static void __xiic_start_xfer(struct xiic_i2c *i2c) @@ -701,6 +863,33 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) if (err < 0) return err; + /* Decide standard mode or Dynamic mode */ + i2c->dynamic = true; + + /* + * If number of messages is 1 and read length is > 255 bytes, + * enter standard mode + */ + + if (i2c->nmsgs == 1 && (i2c->tx_msg->flags & I2C_M_RD) && + i2c->tx_msg->len > MAX_READ_LENGTH_DYNAMIC) { + i2c->dynamic = false; + } else if (i2c->nmsgs > 1) { + int count; + + /* + * If number of messages is more than 1 and one of them is + * a read message, enter standard mode. Since repeated start + * operation in dynamic mode read is not happenning + */ + for (count = 0; count < i2c->nmsgs; count++) { + if (i2c->tx_msg[count].flags & I2C_M_RD) { + i2c->dynamic = false; + break; + } + } + } + err = xiic_start_xfer(i2c, msgs, num); if (err < 0) { dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); @@ -737,15 +926,10 @@ static const struct i2c_algorithm xiic_algorithm = { .functionality = xiic_func, }; -static const struct i2c_adapter_quirks xiic_quirks = { - .max_read_len = 255, -}; - static const struct i2c_adapter xiic_adapter = { .owner = THIS_MODULE, .class = I2C_CLASS_DEPRECATED, .algo = &xiic_algorithm, - .quirks = &xiic_quirks, }; static int xiic_i2c_probe(struct platform_device *pdev) From patchwork Thu Sep 22 08:44:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 1680964 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 22 Sep 2022 01:45:30 -0700 Envelope-to: michal.simek@amd.com, radhey.shyam.pandey@amd.com, shubhrajyoti.datta@amd.com, srinivas.goud@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.6] (port=54840 helo=xhdvnc106.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1obHpp-0005X3-TM; Thu, 22 Sep 2022 01:45:30 -0700 Received: by xhdvnc106.xilinx.com (Postfix, from userid 90444) id EA82D610BE; Thu, 22 Sep 2022 14:15:05 +0530 (IST) From: Manikanta Guntupalli To: , , , , CC: , , , Raviteja Narayanam , Manikanta Guntupalli Subject: [PATCH V2 2/9] i2c: xiic: Fix Rx and Tx paths in standard mode Date: Thu, 22 Sep 2022 14:14:47 +0530 Message-ID: <1663836294-5698-3-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1663836294-5698-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1663836294-5698-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1NAM02FT050:EE_|BL3PR02MB7906:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d69a598-3254-4a9b-461f-08da9c76dab5 X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 08:45:51.4171 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d69a598-3254-4a9b-461f-08da9c76dab5 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT050.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR02MB7906 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam When a combined message request comes from user space, the controller has to initiate repeated start sequence. In standard mode, this repeated start sequence is corrupted if there is still data in the Tx FIFO. So, always make sure that all the bytes are completely transmitted out of the FIFO by waiting for TXEMPTY, if the previous message is of Tx type. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 53 +++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 2aa43e067fee..79802fffa26c 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -61,6 +61,7 @@ enum xiic_endian { * @state: See STATE_ * @singlemaster: Indicates bus is single master * @dynamic: Mode of controller + * @prev_msg_tx: Previous message is Tx */ struct xiic_i2c { struct device *dev; @@ -78,6 +79,7 @@ struct xiic_i2c { enum xilinx_i2c_state state; bool singlemaster; bool dynamic; + bool prev_msg_tx; }; #define XIIC_MSB_OFFSET 0 @@ -280,6 +282,24 @@ static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) return 0; } +static int xiic_wait_tx_empty(struct xiic_i2c *i2c) +{ + u8 isr; + unsigned long timeout; + + timeout = jiffies + XIIC_I2C_TIMEOUT; + for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); + !(isr & XIIC_INTR_TX_EMPTY_MASK); + isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) { + if (time_after(jiffies, timeout)) { + dev_err(i2c->dev, "Timeout waiting at Tx empty\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + static int xiic_reinit(struct xiic_i2c *i2c) { int ret; @@ -685,6 +705,20 @@ static void xiic_start_recv(struct xiic_i2c *i2c) local_irq_restore(flags); } else { + /* + * If previous message is Tx, make sure that Tx FIFO is empty + * before starting a new transfer as the repeated start in + * standard mode can corrupt the transaction if there are + * still bytes to be transmitted in FIFO + */ + if (i2c->prev_msg_tx) { + int status; + + status = xiic_wait_tx_empty(i2c); + if (status) + return; + } + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); /* Set Receive fifo depth */ @@ -739,6 +773,8 @@ static void xiic_start_recv(struct xiic_i2c *i2c) /* Enable interrupts */ xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); + + i2c->prev_msg_tx = false; } static void xiic_start_send(struct xiic_i2c *i2c) @@ -773,6 +809,19 @@ static void xiic_start_send(struct xiic_i2c *i2c) xiic_fill_tx_fifo(i2c); } else { + /* + * If previous message is Tx, make sure that Tx FIFO is empty + * before starting a new transfer as the repeated start in + * standard mode can corrupt the transaction if there are + * still bytes to be transmitted in FIFO + */ + if (i2c->prev_msg_tx) { + int status; + + status = xiic_wait_tx_empty(i2c); + if (status) + return; + } /* Check if RSTA should be set */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); if (cr & XIIC_CR_MSMS_MASK) { @@ -803,6 +852,7 @@ static void xiic_start_send(struct xiic_i2c *i2c) XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK); } + i2c->prev_msg_tx = true; } static void __xiic_start_xfer(struct xiic_i2c *i2c) @@ -866,6 +916,9 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) /* Decide standard mode or Dynamic mode */ i2c->dynamic = true; + /* Initialize prev message type */ + i2c->prev_msg_tx = false; + /* * If number of messages is 1 and read length is > 255 bytes, * enter standard mode From patchwork Thu Sep 22 08:44:48 2022 Content-Type: text/plain; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 08:46:02.5270 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f45eeda3-6450-4a71-e7d2-08da9c76e156 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT033.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB6513 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam Xilinx I2C IP has two modes of operation, both of which implement I2C transactions. The only difference from sw perspective is the programming sequence for these modes. Dynamic mode -> Simple to program, less number of steps in sequence. Standard mode -> Gives flexibility, more number of steps in sequence. In dynamic mode, during the i2c-read transactions, if there is a delay(> 200us) between the register writes (address & byte count), read transaction fails. On a system with load, this scenario is occurring frequently. To avoid this, switch to standard mode if there is a read request. Added a quirk to identify the IP version effected by this and follow the standard mode. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 96 +++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 39 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 79802fffa26c..10e0fafb25f1 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -32,6 +32,7 @@ #include #define DRIVER_NAME "xiic-i2c" +#define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0) enum xilinx_i2c_state { STATE_DONE, @@ -62,6 +63,7 @@ enum xiic_endian { * @singlemaster: Indicates bus is single master * @dynamic: Mode of controller * @prev_msg_tx: Previous message is Tx + * @quirks: To hold platform specific bug info */ struct xiic_i2c { struct device *dev; @@ -80,6 +82,11 @@ struct xiic_i2c { bool singlemaster; bool dynamic; bool prev_msg_tx; + u32 quirks; +}; + +struct xiic_version_data { + u32 quirks; }; #define XIIC_MSB_OFFSET 0 @@ -878,7 +885,8 @@ static void __xiic_start_xfer(struct xiic_i2c *i2c) static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) { - int ret; + bool broken_read, max_read_len, smbus_blk_read; + int ret, count; mutex_lock(&i2c->lock); @@ -891,6 +899,34 @@ static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) i2c->nmsgs = num; init_completion(&i2c->completion); + /* Decide standard mode or Dynamic mode */ + i2c->dynamic = true; + + /* Initialize prev message type */ + i2c->prev_msg_tx = false; + + /* + * Scan through nmsgs, use dynamic mode when none of the below three + * conditions occur. We need standard mode even if one condition holds + * true in the entire array of messages in a single transfer. + * If read transaction as dynamic mode is broken for delayed reads + * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions. + * If read length is > 255 bytes. + * If smbus_block_read transaction. + */ + for (count = 0; count < i2c->nmsgs; count++) { + broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) && + (i2c->tx_msg[count].flags & I2C_M_RD); + max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) && + (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC); + smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN); + + if (broken_read || max_read_len || smbus_blk_read) { + i2c->dynamic = false; + break; + } + } + ret = xiic_reinit(i2c); if (!ret) __xiic_start_xfer(i2c); @@ -913,36 +949,6 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) if (err < 0) return err; - /* Decide standard mode or Dynamic mode */ - i2c->dynamic = true; - - /* Initialize prev message type */ - i2c->prev_msg_tx = false; - - /* - * If number of messages is 1 and read length is > 255 bytes, - * enter standard mode - */ - - if (i2c->nmsgs == 1 && (i2c->tx_msg->flags & I2C_M_RD) && - i2c->tx_msg->len > MAX_READ_LENGTH_DYNAMIC) { - i2c->dynamic = false; - } else if (i2c->nmsgs > 1) { - int count; - - /* - * If number of messages is more than 1 and one of them is - * a read message, enter standard mode. Since repeated start - * operation in dynamic mode read is not happenning - */ - for (count = 0; count < i2c->nmsgs; count++) { - if (i2c->tx_msg[count].flags & I2C_M_RD) { - i2c->dynamic = false; - break; - } - } - } - err = xiic_start_xfer(i2c, msgs, num); if (err < 0) { dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); @@ -985,10 +991,23 @@ static const struct i2c_adapter xiic_adapter = { .algo = &xiic_algorithm, }; +static const struct xiic_version_data xiic_2_00 = { + .quirks = DYNAMIC_MODE_READ_BROKEN_BIT, +}; + +#if defined(CONFIG_OF) +static const struct of_device_id xiic_of_match[] = { + { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 }, + {}, +}; +MODULE_DEVICE_TABLE(of, xiic_of_match); +#endif + static int xiic_i2c_probe(struct platform_device *pdev) { struct xiic_i2c *i2c; struct xiic_i2c_platform_data *pdata; + const struct of_device_id *match; struct resource *res; int ret, irq; u8 i; @@ -998,6 +1017,13 @@ static int xiic_i2c_probe(struct platform_device *pdev) if (!i2c) return -ENOMEM; + match = of_match_node(xiic_of_match, pdev->dev.of_node); + if (match && match->data) { + const struct xiic_version_data *data = match->data; + + i2c->quirks = data->quirks; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); i2c->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(i2c->base)) @@ -1109,14 +1135,6 @@ static int xiic_i2c_remove(struct platform_device *pdev) return 0; } -#if defined(CONFIG_OF) -static const struct of_device_id xiic_of_match[] = { - { .compatible = "xlnx,xps-iic-2.00.a", }, - {}, -}; -MODULE_DEVICE_TABLE(of, xiic_of_match); -#endif - static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) { struct xiic_i2c *i2c = dev_get_drvdata(dev); From patchwork Thu Sep 22 08:44:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 1680966 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 22 Sep 2022 01:45:56 -0700 Envelope-to: michal.simek@amd.com, radhey.shyam.pandey@amd.com, shubhrajyoti.datta@amd.com, srinivas.goud@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.6] (port=54842 helo=xhdvnc106.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1obHqG-0005Yh-HM; Thu, 22 Sep 2022 01:45:56 -0700 Received: by xhdvnc106.xilinx.com (Postfix, from userid 90444) id 349BF61050; Thu, 22 Sep 2022 14:15:10 +0530 (IST) From: Manikanta Guntupalli To: , , , , CC: , , , Raviteja Narayanam , Manikanta Guntupalli Subject: [PATCH V2 4/9] i2c: xiic: Add wait for FIFO empty in send_tx Date: Thu, 22 Sep 2022 14:14:49 +0530 Message-ID: <1663836294-5698-5-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1663836294-5698-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1663836294-5698-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1NAM02FT050:EE_|SJ0PR02MB7232:EE_ X-MS-Office365-Filtering-Correlation-Id: 4efbda05-ef01-4860-a43f-08da9c76e785 X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 08:46:12.9153 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4efbda05-ef01-4860-a43f-08da9c76e785 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT050.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR02MB7232 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam If the tx_half_empty interrupt comes first instead of tx_empty, STOP bit is generated even before all the bytes are transmitted out on the bus. STOP bit should be sent only after all the bytes in the FIFO are transmitted out of the FIFO. So wait until FIFO is empty before sending the STOP bit. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 10e0fafb25f1..1149104074a7 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -436,6 +436,13 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) data |= XIIC_TX_DYN_STOP_MASK; } else { u8 cr; + int status; + + /* Wait till FIFO is empty so STOP is sent last */ + status = xiic_wait_tx_empty(i2c); + if (status) + return; + /* Write to CR to stop */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & From patchwork Thu Sep 22 08:44:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 1680968 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 22 Sep 2022 01:46:10 -0700 Envelope-to: michal.simek@amd.com, radhey.shyam.pandey@amd.com, shubhrajyoti.datta@amd.com, srinivas.goud@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.6] (port=54843 helo=xhdvnc106.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1obHqT-0001o1-L9; Thu, 22 Sep 2022 01:46:10 -0700 Received: by xhdvnc106.xilinx.com (Postfix, from userid 90444) id 5786761053; Thu, 22 Sep 2022 14:15:12 +0530 (IST) From: Manikanta Guntupalli To: , , , , CC: , , , Raviteja Narayanam , Manikanta Guntupalli Subject: [PATCH V2 5/9] i2c: xiic: Add smbus_block_read functionality Date: Thu, 22 Sep 2022 14:14:50 +0530 Message-ID: <1663836294-5698-6-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1663836294-5698-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1663836294-5698-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1NAM02FT033:EE_|SA0PR02MB7274:EE_ X-MS-Office365-Filtering-Correlation-Id: ee6b69e9-ce3e-49cc-5a19-08da9c76efc1 X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 08:46:26.7284 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee6b69e9-ce3e-49cc-5a19-08da9c76efc1 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT033.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR02MB7274 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam smbus_block_read is added to xiic driver to read from few sensors which support this command. Since the number of bytes to read is not known prior to transfer, xiic standard mode is being used for low level control of IP. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 82 +++++++++++++++++++++++++++++++++-- 1 file changed, 78 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 1149104074a7..8bd33dfdff91 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -33,6 +33,7 @@ #define DRIVER_NAME "xiic-i2c" #define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0) +#define SMBUS_BLOCK_READ_MIN_LEN 3 enum xilinx_i2c_state { STATE_DONE, @@ -64,6 +65,7 @@ enum xiic_endian { * @dynamic: Mode of controller * @prev_msg_tx: Previous message is Tx * @quirks: To hold platform specific bug info + * @smbus_block_read: Flag to handle block read */ struct xiic_i2c { struct device *dev; @@ -83,6 +85,7 @@ struct xiic_i2c { bool dynamic; bool prev_msg_tx; u32 quirks; + bool smbus_block_read; }; struct xiic_version_data { @@ -346,6 +349,62 @@ static void xiic_deinit(struct xiic_i2c *i2c) xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); } +static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c) +{ + u8 rxmsg_len, rfd_set = 0; + + /* + * Clear the I2C_M_RECV_LEN flag to avoid setting + * message length again + */ + i2c->rx_msg->flags &= ~I2C_M_RECV_LEN; + + /* Set smbus_block_read flag to identify in isr */ + i2c->smbus_block_read = true; + + /* Read byte from rx fifo and set message length */ + rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); + + i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len; + + /* Check if received length is valid */ + if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) { + /* Set Receive fifo depth */ + if (rxmsg_len > IIC_RX_FIFO_DEPTH) { + /* + * When Rx msg len greater than or equal to Rx fifo capacity + * Receive fifo depth should set to Rx fifo capacity minus 1 + */ + rfd_set = IIC_RX_FIFO_DEPTH - 1; + i2c->rx_msg->len = rxmsg_len + 1; + } else if ((rxmsg_len == 1) || + (rxmsg_len == 0)) { + /* + * Minimum of 3 bytes required to exit cleanly. 1 byte + * already received, Second byte is being received. Have + * to set NACK in read_rx before receiving the last byte + */ + rfd_set = 0; + i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN; + } else { + /* + * When Rx msg len less than Rx fifo capacity + * Receive fifo depth should set to Rx msg len minus 2 + */ + rfd_set = rxmsg_len - 2; + i2c->rx_msg->len = rxmsg_len + 1; + } + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); + + return; + } + + /* Invalid message length, trigger STATE_ERROR with tx_msg_len in ISR */ + i2c->tx_msg->len = 3; + i2c->smbus_block_read = false; + dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n"); +} + static void xiic_read_rx(struct xiic_i2c *i2c) { u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; @@ -368,6 +427,12 @@ static void xiic_read_rx(struct xiic_i2c *i2c) if (!i2c->dynamic) { bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; + /* Set msg length if smbus_block_read */ + if (i2c->rx_msg->flags & I2C_M_RECV_LEN) { + xiic_smbus_block_read_setup(i2c); + return; + } + if (bytes_rem > IIC_RX_FIFO_DEPTH) { bytes_to_read = bytes_in_fifo; } else if (bytes_rem > 1) { @@ -601,6 +666,12 @@ static irqreturn_t xiic_process(int irq, void *dev_id) /* The bus is not busy, disable BusNotBusy interrupt */ xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); + if (i2c->tx_msg && i2c->smbus_block_read) { + i2c->smbus_block_read = false; + /* Set requested message len=1 to indicate STATE_DONE */ + i2c->tx_msg->len = 1; + } + if (!i2c->tx_msg) goto out; @@ -741,11 +812,14 @@ static void xiic_start_recv(struct xiic_i2c *i2c) rfd_set = IIC_RX_FIFO_DEPTH - 1; } else if (rx_watermark == 1) { rfd_set = rx_watermark - 1; - /* Handle single byte transfer separately */ - cr |= XIIC_CR_NO_ACK_MASK; + + /* Set No_ACK, except for smbus_block_read */ + if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) { + /* Handle single byte transfer separately */ + cr |= XIIC_CR_NO_ACK_MASK; + } } else if (rx_watermark == 0) { rfd_set = rx_watermark; - cr |= XIIC_CR_NO_ACK_MASK; } else { rfd_set = rx_watermark - 2; } @@ -984,7 +1058,7 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) static u32 xiic_func(struct i2c_adapter *adap) { - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; } static const struct i2c_algorithm xiic_algorithm = { From patchwork Thu Sep 22 08:44:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 1680969 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-xilinx-onmicrosoft-com header.b=GhqpYESJ; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MY86j51dcz1yqL for ; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 08:46:37.3151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28796093-bc21-4c53-6016-08da9c76f60e X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT058.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN4PR0201MB8712 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam 'DYNAMIC_MODE_READ_BROKEN_BIT' quirk added in the driver, effected IP versions no longer enter dynamic mode. So, remove local_irq_save/local_irq_restore APIs from driver. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 8bd33dfdff91..31296e252279 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -741,7 +741,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) u16 rx_watermark; u8 cr = 0, rfd_set = 0; struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; - unsigned long flags; dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), @@ -773,8 +772,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) bytes--; xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); - local_irq_save(flags); - /* write the address */ xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, i2c_8bit_addr_from_msg(msg) | @@ -787,8 +784,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 08:46:56.7849 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03060c63-1d27-4651-9b7f-08da9c7701ab X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT043.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR02MB8706 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam Added the xilinx I2C new version 'xlnx,axi-iic-2.1' string to compatible Added clock-frequency as optional property. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- .../devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml index 715dcfa5a922..be6c18b2c19e 100644 --- a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml +++ b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml @@ -14,7 +14,9 @@ allOf: properties: compatible: - const: xlnx,xps-iic-2.00.a + enum: + - xlnx,xps-iic-2.00.a + - xlnx,axi-iic-2.1 reg: maxItems: 1 @@ -36,6 +38,9 @@ required: - interrupts - clocks +optional: + - clock-frequency + unevaluatedProperties: false examples: From patchwork Thu Sep 22 08:44:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 1680972 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 08:47:10.2161 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1714b3fd-76a6-4561-aa2a-08da9c7709aa X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT053.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR02MB8577 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam Xilinx AXI I2C IP is updated with a bug fix for dynamic mode reads. Older IPs are handled with a workaround in which they are using xiic standard mode for all these effected use cases. Added the new IP version to compatible. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 31296e252279..0f03feb2ff78 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -1074,6 +1074,7 @@ static const struct xiic_version_data xiic_2_00 = { #if defined(CONFIG_OF) static const struct of_device_id xiic_of_match[] = { { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 }, + { .compatible = "xlnx,axi-iic-2.1", }, {}, }; MODULE_DEVICE_TABLE(of, xiic_of_match); From patchwork Thu Sep 22 08:44:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 1680973 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 08:47:21.1930 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f499798-2154-4e1e-fcd2-08da9c771037 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT019.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN4PR0201MB8821 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam From 'clock-frequency' device tree property, configure I2C SCL frequency by calculating the timing register values according to input clock. After soft reset in reinit function, the timing registers are set to default values (configured in design tool). So, setting SCL frequency is done inside reinit function after the soft reset. This allows configuration of SCL frequency exclusively through software via device tree property, overriding the design. If the clock-frequency parameter is not specified in DT, driver doesn't configure frequency, making it backward compatible. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 148 ++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 0f03feb2ff78..d079aa7868c4 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -46,6 +46,12 @@ enum xiic_endian { BIG }; +enum i2c_scl_freq { + REG_VALUES_100KHZ = 0, + REG_VALUES_400KHZ = 1, + REG_VALUES_1MHZ = 2 +}; + /** * struct xiic_i2c - Internal representation of the XIIC I2C bus * @dev: Pointer to device structure @@ -66,6 +72,8 @@ enum xiic_endian { * @prev_msg_tx: Previous message is Tx * @quirks: To hold platform specific bug info * @smbus_block_read: Flag to handle block read + * @input_clk: Input clock to I2C controller + * @i2c_clk: I2C SCL frequency */ struct xiic_i2c { struct device *dev; @@ -86,12 +94,37 @@ struct xiic_i2c { bool prev_msg_tx; u32 quirks; bool smbus_block_read; + unsigned long input_clk; + unsigned int i2c_clk; }; struct xiic_version_data { u32 quirks; }; +/** + * struct timing_regs - AXI I2C timing registers that depend on I2C spec + * @tsusta: setup time for a repeated START condition + * @tsusto: setup time for a STOP condition + * @thdsta: hold time for a repeated START condition + * @tsudat: setup time for data + * @tbuf: bus free time between STOP and START + */ +struct timing_regs { + unsigned int tsusta; + unsigned int tsusto; + unsigned int thdsta; + unsigned int tsudat; + unsigned int tbuf; +}; + +/* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */ +static const struct timing_regs timing_reg_values[] = { + { 5700, 5000, 4300, 550, 5000 }, /* Reg values for 100KHz */ + { 900, 900, 900, 400, 1600 }, /* Reg values for 400KHz */ + { 380, 380, 380, 170, 620 }, /* Reg values for 1MHz */ +}; + #define XIIC_MSB_OFFSET 0 #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET) @@ -110,6 +143,19 @@ struct xiic_version_data { #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ #define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */ +/* + * Timing register offsets from RegisterBase. These are used only for + * setting i2c clock frequency for the line. + */ +#define XIIC_TSUSTA_REG_OFFSET (0x28 + XIIC_REG_OFFSET) /* TSUSTA Register */ +#define XIIC_TSUSTO_REG_OFFSET (0x2C + XIIC_REG_OFFSET) /* TSUSTO Register */ +#define XIIC_THDSTA_REG_OFFSET (0x30 + XIIC_REG_OFFSET) /* THDSTA Register */ +#define XIIC_TSUDAT_REG_OFFSET (0x34 + XIIC_REG_OFFSET) /* TSUDAT Register */ +#define XIIC_TBUF_REG_OFFSET (0x38 + XIIC_REG_OFFSET) /* TBUF Register */ +#define XIIC_THIGH_REG_OFFSET (0x3C + XIIC_REG_OFFSET) /* THIGH Register */ +#define XIIC_TLOW_REG_OFFSET (0x40 + XIIC_REG_OFFSET) /* TLOW Register */ +#define XIIC_THDDAT_REG_OFFSET (0x44 + XIIC_REG_OFFSET) /* THDDAT Register */ + /* Control Register masks */ #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ @@ -310,12 +356,102 @@ static int xiic_wait_tx_empty(struct xiic_i2c *i2c) return 0; } +/** + * xiic_setclk - Sets the configured clock rate + * @i2c: Pointer to the xiic device structure + * + * The timing register values are calculated according to the input clock + * frequency and configured scl frequency. For details, please refer the + * AXI I2C PG and NXP I2C Spec. + * Supported frequencies are 100KHz, 400KHz and 1MHz. + * + * Return: 0 on success (Supported frequency selected or not configurable in SW) + * -EINVAL on failure (scl frequency not supported or THIGH is 0) + */ +static int xiic_setclk(struct xiic_i2c *i2c) +{ + unsigned int clk_in_mhz; + unsigned int index = 0; + u32 reg_val; + + dev_dbg(i2c->adap.dev.parent, + "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n", + __func__, i2c->input_clk, i2c->i2c_clk); + + /* If not specified in DT, do not configure in SW. Rely only on Vivado design */ + if (!i2c->i2c_clk || !i2c->input_clk) + return 0; + + clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000); + + switch (i2c->i2c_clk) { + case I2C_MAX_FAST_MODE_PLUS_FREQ: + index = REG_VALUES_1MHZ; + break; + case I2C_MAX_FAST_MODE_FREQ: + index = REG_VALUES_400KHZ; + break; + case I2C_MAX_STANDARD_MODE_FREQ: + index = REG_VALUES_100KHZ; + break; + default: + dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n"); + return -EINVAL; + } + + /* + * Value to be stored in a register is the number of clock cycles required + * for the time duration. So the time is divided by the input clock time + * period to get the number of clock cycles required. Refer Xilinx AXI I2C + * PG document and I2C specification for further details. + */ + + /* THIGH - Depends on SCL clock frequency(i2c_clk) as below */ + reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7; + if (reg_val == 0) + return -EINVAL; + + xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1); + + /* TLOW - Value same as THIGH */ + xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1); + + /* TSUSTA */ + reg_val = (timing_reg_values[index].tsusta * clk_in_mhz) / 1000; + xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1); + + /* TSUSTO */ + reg_val = (timing_reg_values[index].tsusto * clk_in_mhz) / 1000; + xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1); + + /* THDSTA */ + reg_val = (timing_reg_values[index].thdsta * clk_in_mhz) / 1000; + xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1); + + /* TSUDAT */ + reg_val = (timing_reg_values[index].tsudat * clk_in_mhz) / 1000; + xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1); + + /* TBUF */ + reg_val = (timing_reg_values[index].tbuf * clk_in_mhz) / 1000; + xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1); + + /* THDDAT */ + xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1); + + return 0; +} + static int xiic_reinit(struct xiic_i2c *i2c) { int ret; xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); + ret = xiic_setclk(i2c); + if (ret) + return ret; + /* Set receive Fifo depth to maximum (zero based). */ xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); @@ -1138,6 +1274,15 @@ static int xiic_i2c_probe(struct platform_device *pdev) pm_runtime_use_autosuspend(i2c->dev); pm_runtime_set_active(i2c->dev); pm_runtime_enable(i2c->dev); + + /* SCL frequency configuration */ + i2c->input_clk = clk_get_rate(i2c->clk); + ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", + &i2c->i2c_clk); + /* If clock-frequency not specified in DT, do not configure in SW */ + if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ) + i2c->i2c_clk = 0; + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, xiic_process, IRQF_ONESHOT, pdev->name, i2c); @@ -1181,6 +1326,9 @@ static int xiic_i2c_probe(struct platform_device *pdev) i2c_new_client_device(&i2c->adap, pdata->devices + i); } + dev_dbg(&pdev->dev, "mmio %08lx irq %d scl clock frequency %d\n", + (unsigned long)res->start, irq, i2c->i2c_clk); + return 0; err_clk_dis: