From patchwork Fri Sep 16 14:00:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chong, Teik Heng" X-Patchwork-Id: 1678707 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=ZsNuf0Dw; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MTbP15Mn3z1yp0 for ; Sat, 17 Sep 2022 00:02:27 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2657484BAC; Fri, 16 Sep 2022 16:02:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ZsNuf0Dw"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9F5FD84BAC; Fri, 16 Sep 2022 16:01:14 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2059380E94 for ; Fri, 16 Sep 2022 16:01:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=teik.heng.chong@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663336872; x=1694872872; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=e4x/Duq0sIqbuVxSD7HNe17e4C8lG4UqFHhQ/pEKj80=; b=ZsNuf0DwvHK9YZ2g6M3Sg9nWpyJj1CyQUXAb0JvJsh1MXqAb7ojNrEEO /7BNLORr1nxl4yCp6XjKJLlPwhRlCY0lC9WyeSIuhnwc+6C9cFyg+Iwnw ZN1vbWAXTzzuth8dOhQePg08/y+3BBjprk7aZnh4CfdAVMsWCvEM5449H 64KHmMFXFRGX0BaQIfQCY1LdsHy124Fxbw4JCisaUJI65yyDMl69RsugC AAkriDRe2s92WvsyBweaj43ppHMeNbAa8G7Ii7xFjawKDBag5PQP30vLK rBx5ylfFKaBiqk/pQnG97KTn7/SjS9RqyfIzEa4RbGOZASMWkdeDR64HV Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10472"; a="385286411" X-IronPort-AV: E=Sophos;i="5.93,320,1654585200"; d="scan'208";a="385286411" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 07:01:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,320,1654585200"; d="scan'208";a="706761586" Received: from pgli4336.png.intel.com ([10.221.172.41]) by FMSMGA003.fm.intel.com with ESMTP; 16 Sep 2022 07:00:59 -0700 From: teik.heng.chong@intel.com To: u-boot@lists.denx.de Cc: Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH] ddr: socfpga: Disable the useeccasdata when ECC is enabled Date: Fri, 16 Sep 2022 22:00:47 +0800 Message-Id: <20220916140047.6826-1-teik.heng.chong@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 16 Sep 2022 16:02:11 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee This field allows the FPGA ports to directly access the extra data bits that are normally used to hold the ECC code, so this field must be clear when it's used for ECC data. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- drivers/ddr/altera/sdram_gen5.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 9d69f009e9..085d146179 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -659,6 +659,9 @@ static int altera_gen5_sdram_probe(struct udevice *dev) debug("SDRAM: %ld MiB\n", sdram_size >> 20); if (sdram_is_ecc_enabled(sdr_ctrl)) { + /* Must set USEECCASDATA to 0 if ECC is enabled */ + clrbits_le32(&sdr_ctrl->static_cfg, + SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK); sdram_init_ecc_bits(sdram_size); }